提交 ffb8b1ee 编写于 作者: A Andrzej Hajda 提交者: Kukjin Kim

ARM: dts: add async-bridge clocks to disp1 power domain for exynos5420

FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER),
therefore their clocks should be enabled during power domain switch.
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>
上级 472c95a6
......@@ -283,9 +283,11 @@
<&clock CLK_MOUT_SW_ACLK300>,
<&clock CLK_MOUT_USER_ACLK300_DISP1>,
<&clock CLK_MOUT_SW_ACLK400>,
<&clock CLK_MOUT_USER_ACLK400_DISP1>;
<&clock CLK_MOUT_USER_ACLK400_DISP1>,
<&clock CLK_FIMD1>, <&clock CLK_MIXER>;
clock-names = "oscclk", "pclk0", "clk0",
"pclk1", "clk1", "pclk2", "clk2";
"pclk1", "clk1", "pclk2", "clk2",
"asb0", "asb1";
};
pinctrl_0: pinctrl@13400000 {
......
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