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提交 ff31c54c 编写于 作者: A Arend van Spriel 提交者： Greg Kroah-Hartman
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staging: brcm80211: remove usage of struct osl_info for register access 

Register access to the device uses a flag in struct osl_info to determine
whether to use memory mapped access or not. This check was not needed as
it boils down to memory mapped for brcmsmac driver and not for brcmfmac
driver. Only use of struct osl_info is reduced to keeping track of the
number of allocated sk_buffs within the driver(s).
Reviewed-by: NRoland Vossen <rvossen@broadcom.com>
Reviewed-by: NBrett Rudley <brudley@broadcom.com>
Signed-off-by: NArend van Spriel <arend@broadcom.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
上级 cecf826d
展开全部 隐藏空白更改
内联 并排
Showing with 782 addition and 800 deletion
drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
浏览文件 @ ff31c54c
......@@ -391,7 +391,7 @@ static bool dhd_readahead;
do { \
retryvar = 0; \
do { \
regvar = R_REG(bus->dhd->osh, regaddr); \
regvar = R_REG(regaddr); \
} while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
if (retryvar) { \
bus->regfails += (retryvar-1); \
......@@ -407,7 +407,7 @@ do { \
do { \
retryvar = 0; \
do { \
W_REG(bus->dhd->osh, regaddr, regval); \
W_REG(regaddr, regval); \
} while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
if (retryvar) { \
bus->regfails += (retryvar-1); \
......@@ -5370,7 +5370,7 @@ dhdsdio_probe_attach(struct dhd_bus *bus, struct osl_info *osh, void *sdh,
bus->sdpcmrev = si_corerev(bus->sih);
/* Set core control so an SDIO reset does a backplane reset */
OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
......
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c
浏览文件 @ ff31c54c
......@@ -212,7 +212,7 @@ void wlc_radioreg_exit(wlc_phy_t *pih)
phy_info_t *pi = (phy_info_t *) pih;
volatile u16 dummy;
dummy = R_REG(pi->sh->osh, &pi->regs->phyversion);
dummy = R_REG(&pi->regs->phyversion);
pi->phy_wreg = 0;
wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0);
}
......@@ -248,23 +248,23 @@ u16 read_radio_reg(phy_info_t *pi, u16 addr)
if ((D11REV_GE(pi->sh->corerev, 24)) ||
(D11REV_IS(pi->sh->corerev, 22)
&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
W_REG(pi->sh->osh, &pi->regs->radioregaddr, addr);
W_REG(&pi->regs->radioregaddr, addr);
#ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
(void)R_REG(&pi->regs->radioregaddr);
#endif
data = R_REG(pi->sh->osh, &pi->regs->radioregdata);
data = R_REG(&pi->regs->radioregdata);
} else {
W_REG(pi->sh->osh, &pi->regs->phy4waddr, addr);
W_REG(&pi->regs->phy4waddr, addr);
#ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->phy4waddr);
(void)R_REG(&pi->regs->phy4waddr);
#endif
#ifdef __ARM_ARCH_4T__
__asm__(" .align 4 ");
__asm__(" nop ");
data = R_REG(pi->sh->osh, &pi->regs->phy4wdatalo);
data = R_REG(&pi->regs->phy4wdatalo);
#else
data = R_REG(pi->sh->osh, &pi->regs->phy4wdatalo);
data = R_REG(&pi->regs->phy4wdatalo);
#endif
}
......@@ -286,22 +286,22 @@ void write_radio_reg(phy_info_t *pi, u16 addr, u16 val)
(D11REV_IS(pi->sh->corerev, 22)
&& (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
W_REG(osh, &pi->regs->radioregaddr, addr);
W_REG(&pi->regs->radioregaddr, addr);
#ifdef __mips__
(void)R_REG(osh, &pi->regs->radioregaddr);
(void)R_REG(&pi->regs->radioregaddr);
#endif
W_REG(osh, &pi->regs->radioregdata, val);
W_REG(&pi->regs->radioregdata, val);
} else {
W_REG(osh, &pi->regs->phy4waddr, addr);
W_REG(&pi->regs->phy4waddr, addr);
#ifdef __mips__
(void)R_REG(osh, &pi->regs->phy4waddr);
(void)R_REG(&pi->regs->phy4waddr);
#endif
W_REG(osh, &pi->regs->phy4wdatalo, val);
W_REG(&pi->regs->phy4wdatalo, val);
}
if (pi->sh->bustype == PCI_BUS) {
if (++pi->phy_wreg >= pi->phy_wreg_limit) {
(void)R_REG(osh, &pi->regs->maccontrol);
(void)R_REG(&pi->regs->maccontrol);
pi->phy_wreg = 0;
}
}
......@@ -317,31 +317,31 @@ static u32 read_radio_id(phy_info_t *pi)
if (D11REV_GE(pi->sh->corerev, 24)) {
u32 b0, b1, b2;
W_REG(pi->sh->osh, &pi->regs->radioregaddr, 0);
W_REG(&pi->regs->radioregaddr, 0);
#ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
(void)R_REG(&pi->regs->radioregaddr);
#endif
b0 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
W_REG(pi->sh->osh, &pi->regs->radioregaddr, 1);
b0 = (u32) R_REG(&pi->regs->radioregdata);
W_REG(&pi->regs->radioregaddr, 1);
#ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
(void)R_REG(&pi->regs->radioregaddr);
#endif
b1 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
W_REG(pi->sh->osh, &pi->regs->radioregaddr, 2);
b1 = (u32) R_REG(&pi->regs->radioregdata);
W_REG(&pi->regs->radioregaddr, 2);
#ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
(void)R_REG(&pi->regs->radioregaddr);
#endif
b2 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
b2 = (u32) R_REG(&pi->regs->radioregdata);
id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
& 0xf);
} else {
W_REG(pi->sh->osh, &pi->regs->phy4waddr, RADIO_IDCODE);
W_REG(&pi->regs->phy4waddr, RADIO_IDCODE);
#ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->phy4waddr);
(void)R_REG(&pi->regs->phy4waddr);
#endif
id = (u32) R_REG(pi->sh->osh, &pi->regs->phy4wdatalo);
id |= (u32) R_REG(pi->sh->osh, &pi->regs->phy4wdatahi) << 16;
id = (u32) R_REG(&pi->regs->phy4wdatalo);
id |= (u32) R_REG(&pi->regs->phy4wdatahi) << 16;
}
pi->phy_wreg = 0;
return id;
......@@ -393,13 +393,13 @@ void mod_radio_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)
void write_phy_channel_reg(phy_info_t *pi, uint val)
{
W_REG(pi->sh->osh, &pi->regs->phychannel, val);
W_REG(&pi->regs->phychannel, val);
}
#if defined(BCMDBG)
static bool wlc_phy_war41476(phy_info_t *pi)
{
u32 mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);
u32 mc = R_REG(&pi->regs->maccontrol);
return ((mc & MCTL_EN_MAC) == 0)
|| ((mc & MCTL_PHYLOCK) == MCTL_PHYLOCK);
......@@ -414,9 +414,9 @@ u16 read_phy_reg(phy_info_t *pi, u16 addr)
osh = pi->sh->osh;
regs = pi->regs;
W_REG(osh, &regs->phyregaddr, addr);
W_REG(&regs->phyregaddr, addr);
#ifdef __mips__
(void)R_REG(osh, &regs->phyregaddr);
(void)R_REG(&regs->phyregaddr);
#endif
ASSERT(!
......@@ -424,7 +424,7 @@ u16 read_phy_reg(phy_info_t *pi, u16 addr)
|| D11REV_IS(pi->sh->corerev, 12)) || wlc_phy_war41476(pi));
pi->phy_wreg = 0;
return R_REG(osh, &regs->phyregdata);
return R_REG(&regs->phyregdata);
}
void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
......@@ -436,18 +436,18 @@ void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
regs = pi->regs;
#ifdef __mips__
W_REG(osh, &regs->phyregaddr, addr);
(void)R_REG(osh, &regs->phyregaddr);
W_REG(osh, &regs->phyregdata, val);
W_REG(&regs->phyregaddr, addr);
(void)R_REG(&regs->phyregaddr);
W_REG(&regs->phyregdata, val);
if (addr == 0x72)
(void)R_REG(osh, &regs->phyregdata);
(void)R_REG(&regs->phyregdata);
#else
W_REG(osh, (u32 *)(&regs->phyregaddr),
W_REG((u32 *)(&regs->phyregaddr),
addr | (val << 16));
if (pi->sh->bustype == PCI_BUS) {
if (++pi->phy_wreg >= pi->phy_wreg_limit) {
pi->phy_wreg = 0;
(void)R_REG(osh, &regs->phyversion);
(void)R_REG(&regs->phyversion);
}
}
#endif
......@@ -461,16 +461,16 @@ void and_phy_reg(phy_info_t *pi, u16 addr, u16 val)
osh = pi->sh->osh;
regs = pi->regs;
W_REG(osh, &regs->phyregaddr, addr);
W_REG(&regs->phyregaddr, addr);
#ifdef __mips__
(void)R_REG(osh, &regs->phyregaddr);
(void)R_REG(&regs->phyregaddr);
#endif
ASSERT(!
(D11REV_IS(pi->sh->corerev, 11)
|| D11REV_IS(pi->sh->corerev, 12)) || wlc_phy_war41476(pi));
W_REG(osh, &regs->phyregdata, (R_REG(osh, &regs->phyregdata) & val));
W_REG(&regs->phyregdata, (R_REG(&regs->phyregdata) & val));
pi->phy_wreg = 0;
}
......@@ -482,16 +482,16 @@ void or_phy_reg(phy_info_t *pi, u16 addr, u16 val)
osh = pi->sh->osh;
regs = pi->regs;
W_REG(osh, &regs->phyregaddr, addr);
W_REG(&regs->phyregaddr, addr);
#ifdef __mips__
(void)R_REG(osh, &regs->phyregaddr);
(void)R_REG(&regs->phyregaddr);
#endif
ASSERT(!
(D11REV_IS(pi->sh->corerev, 11)
|| D11REV_IS(pi->sh->corerev, 12)) || wlc_phy_war41476(pi));
W_REG(osh, &regs->phyregdata, (R_REG(osh, &regs->phyregdata) | val));
W_REG(&regs->phyregdata, (R_REG(&regs->phyregdata) | val));
pi->phy_wreg = 0;
}
......@@ -503,17 +503,17 @@ void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)
osh = pi->sh->osh;
regs = pi->regs;
W_REG(osh, &regs->phyregaddr, addr);
W_REG(&regs->phyregaddr, addr);
#ifdef __mips__
(void)R_REG(osh, &regs->phyregaddr);
(void)R_REG(&regs->phyregaddr);
#endif
ASSERT(!
(D11REV_IS(pi->sh->corerev, 11)
|| D11REV_IS(pi->sh->corerev, 12)) || wlc_phy_war41476(pi));
W_REG(osh, &regs->phyregdata,
((R_REG(osh, &regs->phyregdata) & ~mask) | (val & mask)));
W_REG(&regs->phyregdata,
((R_REG(&regs->phyregdata) & ~mask) | (val & mask)));
pi->phy_wreg = 0;
}
......@@ -658,7 +658,7 @@ wlc_phy_t *wlc_phy_attach(shared_phy_t *sh, void *regs, int bandtype, char *vars
}
wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
phyversion = R_REG(osh, &pi->regs->phyversion);
phyversion = R_REG(&pi->regs->phyversion);
pi->pubpi.phy_type = PHY_TYPE(phyversion);
pi->pubpi.phy_rev = phyversion & PV_PV_MASK;
......@@ -985,7 +985,7 @@ void WLBANDINITFN(wlc_phy_init) (wlc_phy_t *pih, chanspec_t chanspec)
pi->radio_chanspec = chanspec;
mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);
mc = R_REG(&pi->regs->maccontrol);
if ((mc & MCTL_EN_MAC) != 0) {
ASSERT((const char *)
"wlc_phy_init: Called with the MAC running!" == NULL);
......@@ -1037,7 +1037,7 @@ void wlc_phy_cal_init(wlc_phy_t *pih)
phy_info_t *pi = (phy_info_t *) pih;
initfn_t cal_init = NULL;
ASSERT((R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) == 0);
ASSERT((R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) == 0);
if (!pi->initialized) {
cal_init = pi->pi_fptr.calinit;
......@@ -1267,34 +1267,34 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
};
u32 *dummypkt;
ASSERT((R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) == 0);
ASSERT((R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) == 0);
dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
dummypkt);
W_REG(pi->sh->osh, &regs->xmtsel, 0);
W_REG(&regs->xmtsel, 0);
if (D11REV_GE(pi->sh->corerev, 11))
W_REG(pi->sh->osh, &regs->wepctl, 0x100);
W_REG(&regs->wepctl, 0x100);
else
W_REG(pi->sh->osh, &regs->wepctl, 0);
W_REG(&regs->wepctl, 0);
W_REG(pi->sh->osh, &regs->txe_phyctl, (ofdm ? 1 : 0) | PHY_TXC_ANT_0);
W_REG(&regs->txe_phyctl, (ofdm ? 1 : 0) | PHY_TXC_ANT_0);
if (ISNPHY(pi) || ISLCNPHY(pi)) {
ASSERT(ofdm);
W_REG(pi->sh->osh, &regs->txe_phyctl1, 0x1A02);
W_REG(&regs->txe_phyctl1, 0x1A02);
}
W_REG(pi->sh->osh, &regs->txe_wm_0, 0);
W_REG(pi->sh->osh, &regs->txe_wm_1, 0);
W_REG(&regs->txe_wm_0, 0);
W_REG(&regs->txe_wm_1, 0);
W_REG(pi->sh->osh, &regs->xmttplatetxptr, 0);
W_REG(pi->sh->osh, &regs->xmttxcnt, DUMMY_PKT_LEN);
W_REG(&regs->xmttplatetxptr, 0);
W_REG(&regs->xmttxcnt, DUMMY_PKT_LEN);
W_REG(pi->sh->osh, &regs->xmtsel, ((8 << 8) | (1 << 5) | (1 << 2) | 2));
W_REG(&regs->xmtsel, ((8 << 8) | (1 << 5) | (1 << 2) | 2));
W_REG(pi->sh->osh, &regs->txe_ctl, 0);
W_REG(&regs->txe_ctl, 0);
if (!pa_on) {
if (ISNPHY(pi))
......@@ -1302,11 +1302,11 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
}
if (ISNPHY(pi) || ISLCNPHY(pi))
W_REG(pi->sh->osh, &regs->txe_aux, 0xD0);
W_REG(&regs->txe_aux, 0xD0);
else
W_REG(pi->sh->osh, &regs->txe_aux, ((1 << 5) | (1 << 4)));
W_REG(&regs->txe_aux, ((1 << 5) | (1 << 4)));
(void)R_REG(pi->sh->osh, &regs->txe_aux);
(void)R_REG(&regs->txe_aux);
i = 0;
count = ofdm ? 30 : 250;
......@@ -1316,22 +1316,22 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
}
while ((i++ < count)
&& (R_REG(pi->sh->osh, &regs->txe_status) & (1 << 7))) {
&& (R_REG(&regs->txe_status) & (1 << 7))) {
udelay(10);
}
i = 0;
while ((i++ < 10)
&& ((R_REG(pi->sh->osh, &regs->txe_status) & (1 << 10)) == 0)) {
&& ((R_REG(&regs->txe_status) & (1 << 10)) == 0)) {
udelay(10);
}
i = 0;
while ((i++ < 10) && ((R_REG(pi->sh->osh, &regs->ifsstat) & (1 << 8)))) {
while ((i++ < 10) && ((R_REG(&regs->ifsstat) & (1 << 8))))
udelay(10);
}
if (!pa_on) {
if (ISNPHY(pi))
wlc_phy_pa_override_nphy(pi, ON);
......@@ -1396,7 +1396,7 @@ void wlc_phy_switch_radio(wlc_phy_t *pih, bool on)
{
uint mc;
mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);
mc = R_REG(&pi->regs->maccontrol);
}
if (ISNPHY(pi)) {
......@@ -1648,7 +1648,7 @@ void wlc_phy_txpower_target_set(wlc_phy_t *ppi, struct txpwr_limits *txpwr)
memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SDM],
&txpwr->mcs_40_mimo[0], WLC_NUM_RATES_MCS_2_STREAM);
if (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC)
if (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC)
mac_enabled = true;
if (mac_enabled)
......@@ -1680,7 +1680,7 @@ int wlc_phy_txpower_set(wlc_phy_t *ppi, uint qdbm, bool override)
suspend =
(0 ==
(R_REG(pi->sh->osh, &pi->regs->maccontrol) &
(R_REG(&pi->regs->maccontrol) &
MCTL_EN_MAC));
if (!suspend)
......@@ -2096,18 +2096,18 @@ void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end)
if (NREV_IS(pi->pubpi.phy_rev, 3)
|| NREV_IS(pi->pubpi.phy_rev, 4)) {
W_REG(pi->sh->osh, &pi->regs->phyregaddr, 0xa0);
(void)R_REG(pi->sh->osh, &pi->regs->phyregaddr);
rxc = R_REG(pi->sh->osh, &pi->regs->phyregdata);
W_REG(pi->sh->osh, &pi->regs->phyregdata,
W_REG(&pi->regs->phyregaddr, 0xa0);
(void)R_REG(&pi->regs->phyregaddr);
rxc = R_REG(&pi->regs->phyregdata);
W_REG(&pi->regs->phyregdata,
(0x1 << 15) | rxc);
}
} else {
if (NREV_IS(pi->pubpi.phy_rev, 3)
|| NREV_IS(pi->pubpi.phy_rev, 4)) {
W_REG(pi->sh->osh, &pi->regs->phyregaddr, 0xa0);
(void)R_REG(pi->sh->osh, &pi->regs->phyregaddr);
W_REG(pi->sh->osh, &pi->regs->phyregdata, rxc);
W_REG(&pi->regs->phyregaddr, 0xa0);
(void)R_REG(&pi->regs->phyregaddr);
W_REG(&pi->regs->phyregdata, rxc);
}
wlc_phy_por_inform(ppi);
......@@ -2234,7 +2234,7 @@ void wlc_phy_txpower_hw_ctrl_set(wlc_phy_t *ppi, bool hwpwrctrl)
if (ISNPHY(pi)) {
suspend =
(0 ==
(R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!suspend)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
......@@ -2476,7 +2476,7 @@ void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val)
return;
suspend =
(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!suspend)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
......@@ -2590,7 +2590,7 @@ wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch)
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
OR_REG(pi->sh->osh, &pi->regs->maccommand,
OR_REG(&pi->regs->maccommand,
MCMD_BG_NOISE);
} else {
wlapi_suspend_mac_and_wait(pi->sh->physhim);
......@@ -2609,7 +2609,7 @@ wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch)
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
OR_REG(pi->sh->osh, &pi->regs->maccommand,
OR_REG(&pi->regs->maccommand,
MCMD_BG_NOISE);
} else {
phy_iq_est_t est[PHY_CORE_MAX];
......
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_int.h
浏览文件 @ ff31c54c
......@@ -1159,7 +1159,7 @@ extern void wlc_phy_table_write_nphy(phy_info_t *pi, u32, u32, u32,
#define WLC_PHY_WAR_PR51571(pi) \
if (((pi)->sh->bustype == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \
(void)R_REG((pi)->sh->osh, &(pi)->regs->maccontrol)
(void)R_REG(&(pi)->regs->maccontrol)
extern void wlc_phy_cal_perical_nphy_run(phy_info_t *pi, u8 caltype);
extern void wlc_phy_aci_reset_nphy(phy_info_t *pi);
......
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_lcn.c
浏览文件 @ ff31c54c
......@@ -2100,7 +2100,7 @@ static void wlc_lcnphy_idle_tssi_est(wlc_phy_t *ppi)
idleTssi = read_phy_reg(pi, 0x4ab);
suspend =
(0 ==
(R_REG(pi->sh->osh, &((phy_info_t *) pi)->regs->maccontrol) &
(R_REG(&((phy_info_t *) pi)->regs->maccontrol) &
MCTL_EN_MAC));
if (!suspend)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
......@@ -2176,7 +2176,7 @@ static void wlc_lcnphy_vbat_temp_sense_setup(phy_info_t *pi, u8 mode)
for (i = 0; i < 14; i++)
values_to_save[i] = read_phy_reg(pi, tempsense_phy_regs[i]);
suspend =
(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!suspend)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
save_txpwrCtrlEn = read_radio_reg(pi, 0x4a4);
......@@ -2303,7 +2303,7 @@ void WLBANDINITFN(wlc_lcnphy_tx_pwr_ctrl_init) (wlc_phy_t *ppi)
phy_info_t *pi = (phy_info_t *) ppi;
suspend =
(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!suspend)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
......@@ -2989,7 +2989,7 @@ s16 wlc_lcnphy_tempsense_new(phy_info_t *pi, bool mode)
if (mode == 1) {
suspend =
(0 ==
(R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!suspend)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
......@@ -3036,7 +3036,7 @@ u16 wlc_lcnphy_tempsense(phy_info_t *pi, bool mode)
if (mode == 1) {
suspend =
(0 ==
(R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!suspend)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
wlc_lcnphy_vbat_temp_sense_setup(pi, TEMPSENSE);
......@@ -3104,7 +3104,7 @@ s8 wlc_lcnphy_vbatsense(phy_info_t *pi, bool mode)
if (mode == 1) {
suspend =
(0 ==
(R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!suspend)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
wlc_lcnphy_vbat_temp_sense_setup(pi, VBATSENSE);
......@@ -3459,7 +3459,7 @@ static void wlc_lcnphy_glacial_timer_based_cal(phy_info_t *pi)
u16 SAVE_pwrctrl = wlc_lcnphy_get_tx_pwr_ctrl(pi);
phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
suspend =
(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!suspend)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
wlc_lcnphy_deaf_mode(pi, true);
......@@ -3501,7 +3501,7 @@ static void wlc_lcnphy_periodic_cal(phy_info_t *pi)
index = pi_lcn->lcnphy_current_index;
suspend =
(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!suspend) {
wlapi_bmac_write_shm(pi->sh->physhim, M_CTS_DURATION, 10000);
......@@ -3859,15 +3859,15 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
timer = 0;
old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
curval1 = R_REG(pi->sh->osh, &pi->regs->psm_corectlsts);
curval1 = R_REG(&pi->regs->psm_corectlsts);
ptr[130] = 0;
W_REG(pi->sh->osh, &pi->regs->psm_corectlsts, ((1 << 6) | curval1));
W_REG(&pi->regs->psm_corectlsts, ((1 << 6) | curval1));
W_REG(pi->sh->osh, &pi->regs->smpl_clct_strptr, 0x7E00);
W_REG(pi->sh->osh, &pi->regs->smpl_clct_stpptr, 0x8000);
W_REG(&pi->regs->smpl_clct_strptr, 0x7E00);
W_REG(&pi->regs->smpl_clct_stpptr, 0x8000);
udelay(20);
curval2 = R_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param);
W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, curval2 | 0x30);
curval2 = R_REG(&pi->regs->psm_phy_hdr_param);
W_REG(&pi->regs->psm_phy_hdr_param, curval2 | 0x30);
write_phy_reg(pi, 0x555, 0x0);
write_phy_reg(pi, 0x5a6, 0x5);
......@@ -3884,19 +3884,19 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
sslpnCalibClkEnCtrl = read_phy_reg(pi, 0x6da);
write_phy_reg(pi, 0x6da, (u32) (sslpnCalibClkEnCtrl | 0x2008));
stpptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_stpptr);
curptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_curptr);
stpptr = R_REG(&pi->regs->smpl_clct_stpptr);
curptr = R_REG(&pi->regs->smpl_clct_curptr);
do {
udelay(10);
curptr = R_REG(pi->sh->osh, &pi->regs->smpl_clct_curptr);
curptr = R_REG(&pi->regs->smpl_clct_curptr);
timer++;
} while ((curptr != stpptr) && (timer < 500));
W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, 0x2);
W_REG(&pi->regs->psm_phy_hdr_param, 0x2);
strptr = 0x7E00;
W_REG(pi->sh->osh, &pi->regs->tplatewrptr, strptr);
W_REG(&pi->regs->tplatewrptr, strptr);
while (strptr < 0x8000) {
val = R_REG(pi->sh->osh, &pi->regs->tplatewrdata);
val = R_REG(&pi->regs->tplatewrdata);
imag = ((val >> 16) & 0x3ff);
real = ((val) & 0x3ff);
if (imag > 511) {
......@@ -3919,8 +3919,8 @@ wlc_lcnphy_samp_cap(phy_info_t *pi, int clip_detect_algo, u16 thresh,
}
write_phy_reg(pi, 0x6da, old_sslpnCalibClkEnCtrl);
W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, curval2);
W_REG(pi->sh->osh, &pi->regs->psm_corectlsts, curval1);
W_REG(&pi->regs->psm_phy_hdr_param, curval2);
W_REG(&pi->regs->psm_corectlsts, curval1);
}
static void wlc_lcnphy_tx_iqlo_soft_cal_full(phy_info_t *pi)
......
drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_n.c
浏览文件 @ ff31c54c
......@@ -14569,11 +14569,11 @@ void WLBANDINITFN(wlc_phy_init_nphy) (phy_info_t *pi)
&origidx, &intr_val);
ASSERT(regs != NULL);
d11_clk_ctl_st = R_REG(pi->sh->osh, &regs->clk_ctl_st);
AND_REG(pi->sh->osh, &regs->clk_ctl_st,
d11_clk_ctl_st = R_REG(&regs->clk_ctl_st);
AND_REG(&regs->clk_ctl_st,
~(CCS_FORCEHT | CCS_HTAREQ));
W_REG(pi->sh->osh, &regs->clk_ctl_st, d11_clk_ctl_st);
W_REG(&regs->clk_ctl_st, d11_clk_ctl_st);
si_restore_core(pi->sh->sih, origidx, intr_val);
}
......@@ -14964,7 +14964,7 @@ static void wlc_phy_resetcca_nphy(phy_info_t *pi)
{
u16 val;
ASSERT(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
ASSERT(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
......@@ -15057,7 +15057,7 @@ void wlc_phy_rxcore_setstate_nphy(wlc_phy_t *pih, u8 rxcore_bitmask)
return;
suspend =
(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!suspend)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
......@@ -18983,28 +18983,28 @@ wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chanspec,
val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
if (CHSPEC_IS5G(chanspec) && !val) {
val = R_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param);
W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param,
val = R_REG(&pi->regs->psm_phy_hdr_param);
W_REG(&pi->regs->psm_phy_hdr_param,
(val | MAC_PHY_FORCE_CLK));
or_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
(BBCFG_RESETCCA | BBCFG_RESETRX));
W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, val);
W_REG(&pi->regs->psm_phy_hdr_param, val);
or_phy_reg(pi, 0x09, NPHY_BandControl_currentBand);
} else if (!CHSPEC_IS5G(chanspec) && val) {
and_phy_reg(pi, 0x09, ~NPHY_BandControl_currentBand);
val = R_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param);
W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param,
val = R_REG(&pi->regs->psm_phy_hdr_param);
W_REG(&pi->regs->psm_phy_hdr_param,
(val | MAC_PHY_FORCE_CLK));
and_phy_reg(pi, (NPHY_TO_BPHY_OFF + BPHY_BB_CONFIG),
(u16) (~(BBCFG_RESETCCA | BBCFG_RESETRX)));
W_REG(pi->sh->osh, &pi->regs->psm_phy_hdr_param, val);
W_REG(&pi->regs->psm_phy_hdr_param, val);
}
write_phy_reg(pi, 0x1ce, ci->PHY_BW1a);
......@@ -19095,15 +19095,15 @@ wlc_phy_chanspec_nphy_setup(phy_info_t *pi, chanspec_t chanspec,
if (spuravoid == 1) {
W_REG(pi->sh->osh, &pi->regs->tsf_clk_frac_l,
W_REG(&pi->regs->tsf_clk_frac_l,
0x5341);
W_REG(pi->sh->osh, &pi->regs->tsf_clk_frac_h,
W_REG(&pi->regs->tsf_clk_frac_h,
0x8);
} else {
W_REG(pi->sh->osh, &pi->regs->tsf_clk_frac_l,
W_REG(&pi->regs->tsf_clk_frac_l,
0x8889);
W_REG(pi->sh->osh, &pi->regs->tsf_clk_frac_h,
W_REG(&pi->regs->tsf_clk_frac_h,
0x8);
}
}
......@@ -19609,13 +19609,13 @@ void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init)
si_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);
mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);
mc = R_REG(&pi->regs->maccontrol);
mc &= ~MCTL_GPOUT_SEL_MASK;
W_REG(pi->sh->osh, &pi->regs->maccontrol, mc);
W_REG(&pi->regs->maccontrol, mc);
OR_REG(pi->sh->osh, &pi->regs->psm_gpio_oe, mask);
OR_REG(&pi->regs->psm_gpio_oe, mask);
AND_REG(pi->sh->osh, &pi->regs->psm_gpio_out, ~mask);
AND_REG(&pi->regs->psm_gpio_out, ~mask);
if (lut_init) {
write_phy_reg(pi, 0xf8, 0x02d8);
......@@ -19633,7 +19633,7 @@ u16 wlc_phy_classifier_nphy(phy_info_t *pi, u16 mask, u16 val)
if (D11REV_IS(pi->sh->corerev, 16)) {
suspended =
(R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) ?
(R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) ?
false : true;
if (!suspended)
wlapi_suspend_mac_and_wait(pi->sh->physhim);
......@@ -27257,7 +27257,7 @@ static void wlc_phy_a4(phy_info_t *pi, bool full_cal)
return;
phy_b3 =
(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (!phy_b3) {
wlapi_suspend_mac_and_wait(pi->sh->physhim);
}
......@@ -28221,7 +28221,7 @@ void wlc_phy_txpower_recalc_target_nphy(phy_info_t *pi)
if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
(void)R_REG(pi->sh->osh, &pi->regs->maccontrol);
(void)R_REG(&pi->regs->maccontrol);
udelay(1);
}
......@@ -28492,7 +28492,7 @@ static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)
if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
(void)R_REG(pi->sh->osh, &pi->regs->maccontrol);
(void)R_REG(&pi->regs->maccontrol);
udelay(1);
}
......@@ -28649,7 +28649,7 @@ static void wlc_phy_txpwrctrl_pwr_setup_nphy(phy_info_t *pi)
if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12)) {
wlapi_bmac_mctrl(pi->sh->physhim, MCTL_PHYLOCK, MCTL_PHYLOCK);
(void)R_REG(pi->sh->osh, &pi->regs->maccontrol);
(void)R_REG(&pi->regs->maccontrol);
udelay(1);
}
......@@ -29194,7 +29194,7 @@ void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable)
{
u16 clip_off[] = { 0xffff, 0xffff };
ASSERT(0 == (R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC));
ASSERT(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
if (enable) {
if (pi->nphy_deaf_count == 0) {
......
drivers/staging/brcm80211/brcmsmac/wlc_ampdu.c
浏览文件 @ ff31c54c
......@@ -920,9 +920,7 @@ wlc_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
u8 status_delay = 0;
/* wait till the next 8 bytes of txstatus is available */
while (((s1 =
R_REG(wlc->osh,
&wlc->regs->frmtxstatus)) & TXS_V) == 0) {
while (((s1 = R_REG(&wlc->regs->frmtxstatus)) & TXS_V) == 0) {
udelay(1);
status_delay++;
if (status_delay > 10) {
......@@ -933,7 +931,7 @@ wlc_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
ASSERT(!(s1 & TX_STATUS_INTERMEDIATE));
ASSERT(s1 & TX_STATUS_AMPDU);
s2 = R_REG(wlc->osh, &wlc->regs->frmtxstatus2);
s2 = R_REG(&wlc->regs->frmtxstatus2);
}
wlc_ampdu_dotxstatus_complete(ampdu, scb, p, txs, s1, s2);
......
drivers/staging/brcm80211/brcmsmac/wlc_mac80211.c
浏览文件 @ ff31c54c
......@@ -333,16 +333,16 @@ void wlc_get_rcmta(struct wlc_info *wlc, int idx, u8 *addr)
osh = wlc->osh;
W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
(void)R_REG(osh, &regs->objaddr);
v32 = R_REG(osh, &regs->objdata);
W_REG(&regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
(void)R_REG(&regs->objaddr);
v32 = R_REG(&regs->objdata);
addr[0] = (u8) v32;
addr[1] = (u8) (v32 >> 8);
addr[2] = (u8) (v32 >> 16);
addr[3] = (u8) (v32 >> 24);
W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
(void)R_REG(osh, &regs->objaddr);
v32 = R_REG(osh, (volatile u16 *)&regs->objdata);
W_REG(&regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
(void)R_REG(&regs->objaddr);
v32 = R_REG(&regs->objdata);
addr[4] = (u8) v32;
addr[5] = (u8) (v32 >> 8);
}
......@@ -485,11 +485,13 @@ void wlc_init(struct wlc_info *wlc)
if (bsscfg->up) {
u32 bi;
/* get beacon period from bsscfg and convert to uS */
/* get beacon period and convert to uS */
bi = bsscfg->current_bss->beacon_period << 10;
/* update the tsf_cfprep register */
/* since init path would reset to default value */
W_REG(wlc->osh, &regs->tsf_cfprep,
/*
* update since init path would reset
* to default value
*/
W_REG(&regs->tsf_cfprep,
(bi << CFPREP_CBI_SHIFT));
/* Update maccontrol PM related bits */
......@@ -526,7 +528,7 @@ void wlc_init(struct wlc_info *wlc)
/* Enable EDCF mode (while the MAC is suspended) */
if (EDCF_ENAB(wlc->pub)) {
OR_REG(wlc->osh, &regs->ifs_ctl, IFS_USEEDCF);
OR_REG(&regs->ifs_ctl, IFS_USEEDCF);
wlc_edcf_setparams(wlc->cfg, false);
}
......@@ -550,7 +552,7 @@ void wlc_init(struct wlc_info *wlc)
wlc->tx_suspended = false;
/* enable the RF Disable Delay timer */
W_REG(wlc->osh, &wlc->regs->rfdisabledly, RFDISABLE_DEFAULT);
W_REG(&wlc->regs->rfdisabledly, RFDISABLE_DEFAULT);
/* initialize mpc delay */
wlc->mpc_delay_off = wlc->mpc_dlycnt = WLC_MPC_MIN_DELAYCNT;
......@@ -615,12 +617,13 @@ bool wlc_ps_check(struct wlc_info *wlc)
bool wake_ok;
if (!AP_ACTIVE(wlc)) {
volatile u32 tmp;
tmp = R_REG(wlc->osh, &wlc->regs->maccontrol);
u32 tmp;
tmp = R_REG(&wlc->regs->maccontrol);
/* If deviceremoved is detected, then don't take any action as this can be called
* in any context. Assume that caller will take care of the condition. This is just
* to avoid assert
/*
* If deviceremoved is detected, then don't take any action as
* this can be called in any context. Assume that caller will
* take care of the condition. This is just to avoid assert
*/
if (tmp == 0xffffffff) {
WL_ERROR("wl%d: %s: dead chip\n",
......@@ -670,7 +673,7 @@ void wlc_set_ps_ctrl(struct wlc_info *wlc)
WL_TRACE("wl%d: wlc_set_ps_ctrl: hps %d wake %d\n",
wlc->pub->unit, hps, wake);
v1 = R_REG(wlc->osh, &wlc->regs->maccontrol);
v1 = R_REG(&wlc->regs->maccontrol);
v2 = 0;
if (hps)
v2 |= MCTL_HPS;
......@@ -1414,7 +1417,7 @@ void wlc_wme_setparams(struct wlc_info *wlc, u16 aci, void *arg, bool suspend)
acp_shm.cwmax = params->cw_max;
acp_shm.cwcur = acp_shm.cwmin;
acp_shm.bslots =
R_REG(wlc->osh, &wlc->regs->tsf_random) & acp_shm.cwcur;
R_REG(&wlc->regs->tsf_random) & acp_shm.cwcur;
acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
/* Indicate the new params to the ucode */
acp_shm.status = wlc_read_shm(wlc, (M_EDCF_QINFO +
......@@ -1501,7 +1504,7 @@ void wlc_edcf_setparams(wlc_bsscfg_t *cfg, bool suspend)
>> EDCF_ECWMAX_SHIFT);
acp_shm.cwcur = acp_shm.cwmin;
acp_shm.bslots =
R_REG(wlc->osh, &wlc->regs->tsf_random) & acp_shm.cwcur;
R_REG(&wlc->regs->tsf_random) & acp_shm.cwcur;
acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
/* Indicate the new params to the ucode */
acp_shm.status = wlc_read_shm(wlc, (M_EDCF_QINFO +
......@@ -3319,13 +3322,11 @@ _wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
}
if (r->size == sizeof(u32))
r->val =
R_REG(osh,
(u32 *)((unsigned char *)(unsigned long)regs +
R_REG((u32 *)((unsigned char *)(unsigned long)regs +
r->byteoff));
else if (r->size == sizeof(u16))
r->val =
R_REG(osh,
(u16 *)((unsigned char *)(unsigned long)regs +
R_REG((u16 *)((unsigned char *)(unsigned long)regs +
r->byteoff));
else
bcmerror = BCME_BADADDR;
......@@ -3354,12 +3355,10 @@ _wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
break;
}
if (r->size == sizeof(u32))
W_REG(osh,
(u32 *)((unsigned char *)(unsigned long) regs +
W_REG((u32 *)((unsigned char *)(unsigned long) regs +
r->byteoff), r->val);
else if (r->size == sizeof(u16))
W_REG(osh,
(u16 *)((unsigned char *)(unsigned long) regs +
W_REG((u16 *)((unsigned char *)(unsigned long) regs +
r->byteoff), r->val);
else
bcmerror = BCME_BADADDR;
......@@ -3429,7 +3428,7 @@ _wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
break;
}
rxstatus = R_REG(wlc->osh, &wlc->regs->phyrxstatus0);
rxstatus = R_REG(&wlc->regs->phyrxstatus0);
if (rxstatus == 0xdead || rxstatus == (u16) -1) {
bcmerror = BCME_ERROR;
break;
......@@ -6433,12 +6432,12 @@ void wlc_tbtt(struct wlc_info *wlc, d11regs_t *regs)
/* GP timer is a freerunning 32 bit counter, decrements at 1 us rate */
void wlc_hwtimer_gptimer_set(struct wlc_info *wlc, uint us)
{
W_REG(wlc->osh, &wlc->regs->gptimer, us);
W_REG(&wlc->regs->gptimer, us);
}
void wlc_hwtimer_gptimer_abort(struct wlc_info *wlc)
{
W_REG(wlc->osh, &wlc->regs->gptimer, 0);
W_REG(&wlc->regs->gptimer, 0);
}
static void wlc_hwtimer_gptimer_cb(struct wlc_info *wlc)
......@@ -6446,7 +6445,7 @@ static void wlc_hwtimer_gptimer_cb(struct wlc_info *wlc)
/* when interrupt is generated, the counter is loaded with last value
* written and continue to decrement. So it has to be cleaned first
*/
W_REG(wlc->osh, &wlc->regs->gptimer, 0);
W_REG(&wlc->regs->gptimer, 0);
}
/*
......@@ -6529,9 +6528,9 @@ void wlc_high_dpc(struct wlc_info *wlc, u32 macintstatus)
if (macintstatus & MI_RFDISABLE) {
WL_ERROR("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n",
wlc->pub->unit,
R_REG(wlc->osh, &regs->phydebug) & PDBG_RFD);
R_REG(&regs->phydebug) & PDBG_RFD);
/* delay the cleanup to wl_down in IBSS case */
if ((R_REG(wlc->osh, &regs->phydebug) & PDBG_RFD)) {
if ((R_REG(&regs->phydebug) & PDBG_RFD)) {
int idx;
wlc_bsscfg_t *bsscfg;
FOREACH_BSS(wlc, idx, bsscfg) {
......@@ -7738,8 +7737,9 @@ void wlc_bss_update_beacon(struct wlc_info *wlc, wlc_bsscfg_t *cfg)
return;
}
if (MBSS_BCN_ENAB(cfg)) { /* Optimize: Some of if/else could be combined */
} else if (HWBCN_ENAB(cfg)) { /* Hardware beaconing for this config */
/* Optimize: Some of if/else could be combined */
if (!MBSS_BCN_ENAB(cfg) && HWBCN_ENAB(cfg)) {
/* Hardware beaconing for this config */
u16 bcn[BCN_TMPL_LEN / 2];
u32 both_valid = MCMD_BCN0VLD | MCMD_BCN1VLD;
d11regs_t *regs = wlc->regs;
......@@ -7750,14 +7750,14 @@ void wlc_bss_update_beacon(struct wlc_info *wlc, wlc_bsscfg_t *cfg)
/* Check if both templates are in use, if so sched. an interrupt
* that will call back into this routine
*/
if ((R_REG(osh, &regs->maccommand) & both_valid) == both_valid) {
if ((R_REG(&regs->maccommand) & both_valid) == both_valid) {
/* clear any previous status */
W_REG(osh, &regs->macintstatus, MI_BCNTPL);
W_REG(&regs->macintstatus, MI_BCNTPL);
}
/* Check that after scheduling the interrupt both of the
* templates are still busy. if not clear the int. & remask
*/
if ((R_REG(osh, &regs->maccommand) & both_valid) == both_valid) {
if ((R_REG(&regs->maccommand) & both_valid) == both_valid) {
wlc->defmacintmask |= MI_BCNTPL;
return;
}
......
drivers/staging/brcm80211/brcmsmac/wlc_mac80211.h
浏览文件 @ ff31c54c
......@@ -194,7 +194,7 @@ extern const u8 prio2fifo[];
*/
#define DEVICEREMOVED(wlc) \
((wlc->hw->clk) ? \
((R_REG(wlc->hw->osh, &wlc->hw->regs->maccontrol) & \
((R_REG(&wlc->hw->regs->maccontrol) & \
(MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN) : \
(si_deviceremoved(wlc->hw->sih)))
......
drivers/staging/brcm80211/include/bcmutils.h
浏览文件 @ ff31c54c
......@@ -361,11 +361,11 @@ extern struct sk_buff *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
#endif
/* Register operations */
#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
#define SET_REG(osh, r, mask, val) \
W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
#define SET_REG(r, mask, val) \
W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
#ifndef setbit
#ifndef NBBY /* the BSD family defines NBBY */
......
drivers/staging/brcm80211/include/osl.h
浏览文件 @ ff31c54c
......@@ -59,9 +59,9 @@ extern uint osl_pci_slot(struct osl_info *osh);
#ifdef BRCM_FULLMAC
#include <bcmsdh.h>
#endif
#define OSL_WRITE_REG(osh, r, v) \
#define OSL_WRITE_REG(r, v) \
(bcmsdh_reg_write(NULL, (unsigned long)(r), sizeof(*(r)), (v)))
#define OSL_READ_REG(osh, r) \
#define OSL_READ_REG(r) \
(bcmsdh_reg_read(NULL, (unsigned long)(r), sizeof(*(r))))
#endif
......@@ -85,14 +85,14 @@ extern uint osl_pci_slot(struct osl_info *osh);
/* register access macros */
#ifndef IL_BIGENDIAN
#ifndef __mips__
#define R_REG(osh, r) (\
#define R_REG(r) (\
SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \
readb((volatile u8*)(r)) : \
sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
readl((volatile u32*)(r)), OSL_READ_REG(osh, r)) \
readl((volatile u32*)(r)), OSL_READ_REG(r)) \
)
#else /* __mips__ */
#define R_REG(osh, r) (\
#define R_REG(r) (\
SELECT_BUS_READ( \
({ \
__typeof(*(r)) __osl_v; \
......@@ -115,14 +115,14 @@ extern uint osl_pci_slot(struct osl_info *osh);
({ \
__typeof(*(r)) __osl_v; \
__asm__ __volatile__("sync"); \
__osl_v = OSL_READ_REG(osh, r); \
__osl_v = OSL_READ_REG(r); \
__asm__ __volatile__("sync"); \
__osl_v; \
})) \
)
#endif /* __mips__ */
#define W_REG(osh, r, v) do { \
#define W_REG(r, v) do { \
SELECT_BUS_WRITE( \
switch (sizeof(*(r))) { \
case sizeof(u8): \
......@@ -132,10 +132,10 @@ extern uint osl_pci_slot(struct osl_info *osh);
case sizeof(u32): \
writel((u32)(v), (volatile u32*)(r)); break; \
}, \
(OSL_WRITE_REG(osh, r, v))); \
(OSL_WRITE_REG(r, v))); \
} while (0)
#else /* IL_BIGENDIAN */
#define R_REG(osh, r) (\
#define R_REG(r) (\
SELECT_BUS_READ( \
({ \
__typeof(*(r)) __osl_v; \
......@@ -154,9 +154,9 @@ extern uint osl_pci_slot(struct osl_info *osh);
} \
__osl_v; \
}), \
OSL_READ_REG(osh, r)) \
OSL_READ_REG(r)) \
)
#define W_REG(osh, r, v) do { \
#define W_REG(r, v) do { \
SELECT_BUS_WRITE( \
switch (sizeof(*(r))) { \
case sizeof(u8): \
......@@ -169,7 +169,7 @@ extern uint osl_pci_slot(struct osl_info *osh);
writel((u32)(v), \
(volatile u32*)(r)); break; \
}, \
(OSL_WRITE_REG(osh, r, v))); \
(OSL_WRITE_REG(r, v))); \
} while (0)
#endif /* IL_BIGENDIAN */
......
drivers/staging/brcm80211/util/aiutils.c
浏览文件 @ ff31c54c
......@@ -41,7 +41,7 @@ get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
uint inv = 0, nom = 0;
while (true) {
ent = R_REG(si_osh(sih), *eromptr);
ent = R_REG(*eromptr);
(*eromptr)++;
if (mask == 0)
......@@ -115,7 +115,7 @@ void ai_scan(si_t *sih, void *regs, uint devid)
chipcregs_t *cc = (chipcregs_t *) regs;
u32 erombase, *eromptr, *eromlim;
erombase = R_REG(sii->osh, &cc->eromptr);
erombase = R_REG(&cc->eromptr);
switch (sih->bustype) {
case SI_BUS:
......@@ -427,7 +427,7 @@ uint ai_flag(si_t *sih)
}
ai = sii->curwrap;
return R_REG(sii->osh, &ai->oobselouta30) & 0x1f;
return R_REG(&ai->oobselouta30) & 0x1f;
}
void ai_setint(si_t *sih, int siflag)
......@@ -438,7 +438,7 @@ void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val)
{
si_info_t *sii = SI_INFO(sih);
u32 *w = (u32 *) sii->curwrap;
W_REG(sii->osh, w + (offset / 4), val);
W_REG(w + (offset / 4), val);
return;
}
......@@ -470,9 +470,9 @@ bool ai_iscoreup(si_t *sih)
sii = SI_INFO(sih);
ai = sii->curwrap;
return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
return (((R_REG(&ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
SICF_CLOCK_EN)
&& ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
&& ((R_REG(&ai->resetctrl) & AIRC_RESET) == 0));
}
/*
......@@ -553,12 +553,12 @@ uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
/* mask and set */
if (mask || val) {
w = (R_REG(sii->osh, r) & ~mask) | val;
W_REG(sii->osh, r, w);
w = (R_REG(r) & ~mask) | val;
W_REG(r, w);
}
/* readback */
w = R_REG(sii->osh, r);
w = R_REG(r);
if (!fast) {
/* restore core index */
......@@ -583,14 +583,14 @@ void ai_core_disable(si_t *sih, u32 bits)
ai = sii->curwrap;
/* if core is already in reset, just return */
if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
if (R_REG(&ai->resetctrl) & AIRC_RESET)
return;
W_REG(sii->osh, &ai->ioctrl, bits);
dummy = R_REG(sii->osh, &ai->ioctrl);
W_REG(&ai->ioctrl, bits);
dummy = R_REG(&ai->ioctrl);
udelay(10);
W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
W_REG(&ai->resetctrl, AIRC_RESET);
udelay(1);
}
......@@ -617,13 +617,13 @@ void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
/*
* Now do the initialization sequence.
*/
W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
dummy = R_REG(sii->osh, &ai->ioctrl);
W_REG(sii->osh, &ai->resetctrl, 0);
W_REG(&ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
dummy = R_REG(&ai->ioctrl);
W_REG(&ai->resetctrl, 0);
udelay(1);
W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
dummy = R_REG(sii->osh, &ai->ioctrl);
W_REG(&ai->ioctrl, (bits | SICF_CLOCK_EN));
dummy = R_REG(&ai->ioctrl);
udelay(1);
}
......@@ -647,8 +647,8 @@ void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
ASSERT((val & ~mask) == 0);
if (mask || val) {
w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
W_REG(sii->osh, &ai->ioctrl, w);
w = ((R_REG(&ai->ioctrl) & ~mask) | val);
W_REG(&ai->ioctrl, w);
}
}
......@@ -671,11 +671,11 @@ u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
ASSERT((val & ~mask) == 0);
if (mask || val) {
w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
W_REG(sii->osh, &ai->ioctrl, w);
w = ((R_REG(&ai->ioctrl) & ~mask) | val);
W_REG(&ai->ioctrl, w);
}
return R_REG(sii->osh, &ai->ioctrl);
return R_REG(&ai->ioctrl);
}
u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
......@@ -697,10 +697,10 @@ u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
ASSERT((mask & ~SISF_CORE_BITS) == 0);
if (mask || val) {
w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
W_REG(sii->osh, &ai->iostatus, w);
w = ((R_REG(&ai->iostatus) & ~mask) | val);
W_REG(&ai->iostatus, w);
}
return R_REG(sii->osh, &ai->iostatus);
return R_REG(&ai->iostatus);
}
drivers/staging/brcm80211/util/bcmotp.c
浏览文件 @ ff31c54c
......@@ -182,7 +182,7 @@ static u16 ipxotp_otpr(void *oh, chipcregs_t *cc, uint wn)
ASSERT(wn < oi->wsize);
ASSERT(cc != NULL);
return R_REG(oi->osh, &cc->sromotp[wn]);
return R_REG(&cc->sromotp[wn]);
}
static u16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off)
......@@ -198,10 +198,10 @@ static u16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off)
((OTPPOC_READ << OTPP_OC_SHIFT) & OTPP_OC_MASK) |
((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) |
((col << OTPP_COL_SHIFT) & OTPP_COL_MASK);
W_REG(oi->osh, &cc->otpprog, otpp);
W_REG(&cc->otpprog, otpp);
for (k = 0;
((st = R_REG(oi->osh, &cc->otpprog)) & OTPP_START_BUSY)
((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
&& (k < OTPP_TRIES); k++)
;
if (k >= OTPP_TRIES) {
......@@ -260,9 +260,9 @@ static void _ipxotp_init(otpinfo_t *oi, chipcregs_t *cc)
otpp =
OTPP_START_BUSY | ((OTPPOC_INIT << OTPP_OC_SHIFT) & OTPP_OC_MASK);
W_REG(oi->osh, &cc->otpprog, otpp);
W_REG(&cc->otpprog, otpp);
for (k = 0;
((st = R_REG(oi->osh, &cc->otpprog)) & OTPP_START_BUSY)
((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
&& (k < OTPP_TRIES); k++)
;
if (k >= OTPP_TRIES) {
......@@ -270,7 +270,7 @@ static void _ipxotp_init(otpinfo_t *oi, chipcregs_t *cc)
}
/* Read OTP lock bits and subregion programmed indication bits */
oi->status = R_REG(oi->osh, &cc->otpstatus);
oi->status = R_REG(&cc->otpstatus);
if ((oi->sih->chip == BCM43224_CHIP_ID)
|| (oi->sih->chip == BCM43225_CHIP_ID)) {
......@@ -579,7 +579,7 @@ static u16 hndotp_otpr(void *oh, chipcregs_t *cc, uint wn)
osh = si_osh(oi->sih);
ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP);
return R_REG(osh, &ptr[wn]);
return R_REG(&ptr[wn]);
}
static u16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff)
......@@ -596,7 +596,7 @@ static u16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff)
ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP);
return R_REG(osh, &ptr[(oi->size / 2) + woff]);
return R_REG(&ptr[(oi->size / 2) + woff]);
}
static u16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx)
......@@ -613,12 +613,12 @@ static u16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx)
otpp = OTPP_START_BUSY | OTPP_READ |
((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) | (col & OTPP_COL_MASK);
W_REG(osh, &cc->otpprog, otpp);
st = R_REG(osh, &cc->otpprog);
W_REG(&cc->otpprog, otpp);
st = R_REG(&cc->otpprog);
for (k = 0;
((st & OTPP_START_BUSY) == OTPP_START_BUSY) && (k < OTPP_TRIES);
k++)
st = R_REG(osh, &cc->otpprog);
st = R_REG(&cc->otpprog);
if (k >= OTPP_TRIES) {
return 0xffff;
......@@ -647,7 +647,7 @@ static void *hndotp_init(si_t *sih)
/* Check for otp */
cc = si_setcoreidx(sih, SI_CC_IDX);
if (cc != NULL) {
cap = R_REG(osh, &cc->capabilities);
cap = R_REG(&cc->capabilities);
if ((cap & CC_CAP_OTPSIZE) == 0) {
/* Nothing there */
goto out;
......@@ -670,7 +670,7 @@ static void *hndotp_init(si_t *sih)
if (oi->ccrev >= 18)
oi->size -= ((OTP_RC0_OFF - OTP_BOUNDARY_OFF) * 2);
oi->hwprot = (int)(R_REG(osh, &cc->otpstatus) & OTPS_PROTECT);
oi->hwprot = (int)(R_REG(&cc->otpstatus) & OTPS_PROTECT);
oi->boundary = -1;
/* Check the region signature */
......@@ -690,10 +690,10 @@ static void *hndotp_init(si_t *sih)
otpdiv = 12;
if (otpdiv) {
clkdiv = R_REG(osh, &cc->clkdiv);
clkdiv = R_REG(&cc->clkdiv);
clkdiv =
(clkdiv & ~CLKD_OTP) | (otpdiv << CLKD_OTP_SHIFT);
W_REG(osh, &cc->clkdiv, clkdiv);
W_REG(&cc->clkdiv, clkdiv);
}
udelay(10);
......
drivers/staging/brcm80211/util/bcmsrom.c
浏览文件 @ ff31c54c
......@@ -1415,15 +1415,15 @@ srom_cc_cmd(si_t *sih, struct osl_info *osh, void *ccregs, u32 cmd,
uint wait_cnt = 1000;
if ((cmd == SRC_OP_READ) || (cmd == SRC_OP_WRITE)) {
W_REG(osh, &cc->sromaddress, wordoff * 2);
W_REG(&cc->sromaddress, wordoff * 2);
if (cmd == SRC_OP_WRITE)
W_REG(osh, &cc->sromdata, data);
W_REG(&cc->sromdata, data);
}
W_REG(osh, &cc->sromcontrol, SRC_START | cmd);
W_REG(&cc->sromcontrol, SRC_START | cmd);
while (wait_cnt--) {
if ((R_REG(osh, &cc->sromcontrol) & SRC_BUSY) == 0)
if ((R_REG(&cc->sromcontrol) & SRC_BUSY) == 0)
break;
}
......@@ -1432,7 +1432,7 @@ srom_cc_cmd(si_t *sih, struct osl_info *osh, void *ccregs, u32 cmd,
return 0xffff;
}
if (cmd == SRC_OP_READ)
return (u16) R_REG(osh, &cc->sromdata);
return (u16) R_REG(&cc->sromdata);
else
return 0xffff;
}
......@@ -1476,9 +1476,9 @@ sprom_read_pci(struct osl_info *osh, si_t *sih, u16 *sprom, uint wordoff,
} else {
if (ISSIM_ENAB(sih))
buf[i] = R_REG(osh, &sprom[wordoff + i]);
buf[i] = R_REG(&sprom[wordoff + i]);
buf[i] = R_REG(osh, &sprom[wordoff + i]);
buf[i] = R_REG(&sprom[wordoff + i]);
}
}
......
drivers/staging/brcm80211/util/hnddma.c
浏览文件 @ ff31c54c
......@@ -590,13 +590,13 @@ static bool _dma_descriptor_align(dma_info_t *di)
/* Check to see if the descriptors need to be aligned on 4K/8K or not */
if (di->d64txregs != NULL) {
W_REG(di->osh, &di->d64txregs->addrlow, 0xff0);
addrl = R_REG(di->osh, &di->d64txregs->addrlow);
W_REG(&di->d64txregs->addrlow, 0xff0);
addrl = R_REG(&di->d64txregs->addrlow);
if (addrl != 0)
return false;
} else if (di->d64rxregs != NULL) {
W_REG(di->osh, &di->d64rxregs->addrlow, 0xff0);
addrl = R_REG(di->osh, &di->d64rxregs->addrlow);
W_REG(&di->d64rxregs->addrlow, 0xff0);
addrl = R_REG(&di->d64rxregs->addrlow);
if (addrl != 0)
return false;
}
......@@ -640,14 +640,14 @@ static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
if ((di->ddoffsetlow == 0)
|| !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
if (direction == DMA_TX) {
W_REG(di->osh, &di->d64txregs->addrlow,
W_REG(&di->d64txregs->addrlow,
(PHYSADDRLO(pa) + di->ddoffsetlow));
W_REG(di->osh, &di->d64txregs->addrhigh,
W_REG(&di->d64txregs->addrhigh,
(PHYSADDRHI(pa) + di->ddoffsethigh));
} else {
W_REG(di->osh, &di->d64rxregs->addrlow,
W_REG(&di->d64rxregs->addrlow,
(PHYSADDRLO(pa) + di->ddoffsetlow));
W_REG(di->osh, &di->d64rxregs->addrhigh,
W_REG(&di->d64rxregs->addrhigh,
(PHYSADDRHI(pa) + di->ddoffsethigh));
}
} else {
......@@ -662,18 +662,18 @@ static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
if (direction == DMA_TX) {
W_REG(di->osh, &di->d64txregs->addrlow,
W_REG(&di->d64txregs->addrlow,
(PHYSADDRLO(pa) + di->ddoffsetlow));
W_REG(di->osh, &di->d64txregs->addrhigh,
W_REG(&di->d64txregs->addrhigh,
di->ddoffsethigh);
SET_REG(di->osh, &di->d64txregs->control,
SET_REG(&di->d64txregs->control,
D64_XC_AE, (ae << D64_XC_AE_SHIFT));
} else {
W_REG(di->osh, &di->d64rxregs->addrlow,
W_REG(&di->d64rxregs->addrlow,
(PHYSADDRLO(pa) + di->ddoffsetlow));
W_REG(di->osh, &di->d64rxregs->addrhigh,
W_REG(&di->d64rxregs->addrhigh,
di->ddoffsethigh);
SET_REG(di->osh, &di->d64rxregs->control,
SET_REG(&di->d64rxregs->control,
D64_RC_AE, (ae << D64_RC_AE_SHIFT));
}
}
......@@ -683,7 +683,7 @@ static void _dma_fifoloopbackenable(dma_info_t *di)
{
DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
OR_REG(di->osh, &di->d64txregs->control, D64_XC_LE);
OR_REG(&di->d64txregs->control, D64_XC_LE);
}
static void _dma_rxinit(dma_info_t *di)
......@@ -719,7 +719,7 @@ static void _dma_rxenable(dma_info_t *di)
DMA_TRACE(("%s: dma_rxenable\n", di->name));
control =
(R_REG(di->osh, &di->d64rxregs->control) & D64_RC_AE) |
(R_REG(&di->d64rxregs->control) & D64_RC_AE) |
D64_RC_RE;
if ((dmactrlflags & DMA_CTRL_PEN) == 0)
......@@ -728,7 +728,7 @@ static void _dma_rxenable(dma_info_t *di)
if (dmactrlflags & DMA_CTRL_ROC)
control |= D64_RC_OC;
W_REG(di->osh, &di->d64rxregs->control,
W_REG(&di->d64rxregs->control,
((di->rxoffset << D64_RC_RO_SHIFT) | control));
}
......@@ -796,7 +796,7 @@ static void *BCMFASTPATH _dma_rx(dma_info_t *di)
uint cur;
ASSERT(p == NULL);
cur =
B2I(((R_REG(di->osh, &di->d64rxregs->status0) &
B2I(((R_REG(&di->d64rxregs->status0) &
D64_RS0_CD_MASK) -
di->rcvptrbase) & D64_RS0_CD_MASK,
dma64dd_t);
......@@ -904,7 +904,7 @@ static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
di->rxout = rxout;
/* update the chip lastdscr pointer */
W_REG(di->osh, &di->d64rxregs->ptr,
W_REG(&di->d64rxregs->ptr,
di->rcvptrbase + I2B(rxout, dma64dd_t));
return ring_empty;
......@@ -919,7 +919,7 @@ static void *_dma_peeknexttxp(dma_info_t *di)
return NULL;
end =
B2I(((R_REG(di->osh, &di->d64txregs->status0) &
B2I(((R_REG(&di->d64txregs->status0) &
D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
dma64dd_t);
......@@ -939,7 +939,7 @@ static void *_dma_peeknextrxp(dma_info_t *di)
return NULL;
end =
B2I(((R_REG(di->osh, &di->d64rxregs->status0) &
B2I(((R_REG(&di->d64rxregs->status0) &
D64_RS0_CD_MASK) - di->rcvptrbase) & D64_RS0_CD_MASK,
dma64dd_t);
......@@ -988,7 +988,7 @@ static uint _dma_txpending(dma_info_t *di)
uint curr;
curr =
B2I(((R_REG(di->osh, &di->d64txregs->status0) &
B2I(((R_REG(&di->d64txregs->status0) &
D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
dma64dd_t);
......@@ -1003,7 +1003,7 @@ static uint _dma_txcommitted(dma_info_t *di)
if (txin == di->txout)
return 0;
ptr = B2I(R_REG(di->osh, &di->d64txregs->ptr), dma64dd_t);
ptr = B2I(R_REG(&di->d64txregs->ptr), dma64dd_t);
return NTXDACTIVE(di->txin, ptr);
}
......@@ -1039,14 +1039,14 @@ static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
if (dmactrlflags & DMA_CTRL_PEN) {
u32 control;
control = R_REG(di->osh, &di->d64txregs->control);
W_REG(di->osh, &di->d64txregs->control,
control = R_REG(&di->d64txregs->control);
W_REG(&di->d64txregs->control,
control | D64_XC_PD);
if (R_REG(di->osh, &di->d64txregs->control) & D64_XC_PD) {
if (R_REG(&di->d64txregs->control) & D64_XC_PD) {
/* We *can* disable it so it is supported,
* restore control register
*/
W_REG(di->osh, &di->d64txregs->control,
W_REG(&di->d64txregs->control,
control);
} else {
/* Not supported, don't allow it to be enabled */
......@@ -1137,7 +1137,7 @@ static void dma64_txinit(dma_info_t *di)
if ((di->hnddma.dmactrlflags & DMA_CTRL_PEN) == 0)
control |= D64_XC_PD;
OR_REG(di->osh, &di->d64txregs->control, control);
OR_REG(&di->d64txregs->control, control);
/* DMA engine with alignment requirement requires table to be inited
* before enabling the engine
......@@ -1151,7 +1151,7 @@ static bool dma64_txenabled(dma_info_t *di)
u32 xc;
/* If the chip is dead, it is not enabled :-) */
xc = R_REG(di->osh, &di->d64txregs->control);
xc = R_REG(&di->d64txregs->control);
return (xc != 0xffffffff) && (xc & D64_XC_XE);
}
......@@ -1162,7 +1162,7 @@ static void dma64_txsuspend(dma_info_t *di)
if (di->ntxd == 0)
return;
OR_REG(di->osh, &di->d64txregs->control, D64_XC_SE);
OR_REG(&di->d64txregs->control, D64_XC_SE);
}
static void dma64_txresume(dma_info_t *di)
......@@ -1172,13 +1172,13 @@ static void dma64_txresume(dma_info_t *di)
if (di->ntxd == 0)
return;
AND_REG(di->osh, &di->d64txregs->control, ~D64_XC_SE);
AND_REG(&di->d64txregs->control, ~D64_XC_SE);
}
static bool dma64_txsuspended(dma_info_t *di)
{
return (di->ntxd == 0) ||
((R_REG(di->osh, &di->d64txregs->control) & D64_XC_SE) ==
((R_REG(&di->d64txregs->control) & D64_XC_SE) ==
D64_XC_SE);
}
......@@ -1204,13 +1204,13 @@ static void BCMFASTPATH dma64_txreclaim(dma_info_t *di, txd_range_t range)
static bool dma64_txstopped(dma_info_t *di)
{
return ((R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK) ==
return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) ==
D64_XS0_XS_STOPPED);
}
static bool dma64_rxstopped(dma_info_t *di)
{
return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK) ==
return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) ==
D64_RS0_RS_STOPPED);
}
......@@ -1278,15 +1278,15 @@ static bool dma64_txreset(dma_info_t *di)
return true;
/* suspend tx DMA first */
W_REG(di->osh, &di->d64txregs->control, D64_XC_SE);
W_REG(&di->d64txregs->control, D64_XC_SE);
SPINWAIT(((status =
(R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK))
(R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
!= D64_XS0_XS_DISABLED) && (status != D64_XS0_XS_IDLE)
&& (status != D64_XS0_XS_STOPPED), 10000);
W_REG(di->osh, &di->d64txregs->control, 0);
W_REG(&di->d64txregs->control, 0);
SPINWAIT(((status =
(R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK))
(R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
!= D64_XS0_XS_DISABLED), 10000);
/* wait for the last transaction to complete */
......@@ -1302,8 +1302,8 @@ static bool dma64_rxidle(dma_info_t *di)
if (di->nrxd == 0)
return true;
return ((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
(R_REG(di->osh, &di->d64rxregs->ptr) & D64_RS0_CD_MASK));
return ((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
(R_REG(&di->d64rxregs->ptr) & D64_RS0_CD_MASK));
}
static bool dma64_rxreset(dma_info_t *di)
......@@ -1313,9 +1313,9 @@ static bool dma64_rxreset(dma_info_t *di)
if (di->nrxd == 0)
return true;
W_REG(di->osh, &di->d64rxregs->control, 0);
W_REG(&di->d64rxregs->control, 0);
SPINWAIT(((status =
(R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_RS_MASK))
(R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK))
!= D64_RS0_RS_DISABLED), 10000);
return status == D64_RS0_RS_DISABLED;
......@@ -1325,7 +1325,7 @@ static bool dma64_rxenabled(dma_info_t *di)
{
u32 rc;
rc = R_REG(di->osh, &di->d64rxregs->control);
rc = R_REG(&di->d64rxregs->control);
return (rc != 0xffffffff) && (rc & D64_RC_RE);
}
......@@ -1335,10 +1335,10 @@ static bool dma64_txsuspendedidle(dma_info_t *di)
if (di->ntxd == 0)
return true;
if (!(R_REG(di->osh, &di->d64txregs->control) & D64_XC_SE))
if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
return 0;
if ((R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_XS_MASK) ==
if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) ==
D64_XS0_XS_IDLE)
return 1;
......@@ -1357,12 +1357,12 @@ static void *dma64_getpos(dma_info_t *di, bool direction)
if (direction == DMA_TX) {
cd_offset =
R_REG(di->osh, &di->d64txregs->status0) & D64_XS0_CD_MASK;
R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK;
idle = !NTXDACTIVE(di->txin, di->txout);
va = di->txp[B2I(cd_offset, dma64dd_t)];
} else {
cd_offset =
R_REG(di->osh, &di->d64rxregs->status0) & D64_XS0_CD_MASK;
R_REG(&di->d64rxregs->status0) & D64_XS0_CD_MASK;
idle = !NRXDACTIVE(di->rxin, di->rxout);
va = di->rxp[B2I(cd_offset, dma64dd_t)];
}
......@@ -1418,7 +1418,7 @@ static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit)
/* kick the chip */
if (commit) {
W_REG(di->osh, &di->d64txregs->ptr,
W_REG(&di->d64txregs->ptr,
di->xmtptrbase + I2B(txout, dma64dd_t));
}
......@@ -1538,7 +1538,7 @@ static int BCMFASTPATH dma64_txfast(dma_info_t *di, struct sk_buff *p0,
/* kick the chip */
if (commit)
W_REG(di->osh, &di->d64txregs->ptr,
W_REG(&di->d64txregs->ptr,
di->xmtptrbase + I2B(txout, dma64dd_t));
/* tx flow control */
......@@ -1589,13 +1589,13 @@ static void *BCMFASTPATH dma64_getnexttxp(dma_info_t *di, txd_range_t range)
end =
(u16) (B2I
(((R_REG(di->osh, &dregs->status0) &
(((R_REG(&dregs->status0) &
D64_XS0_CD_MASK) -
di->xmtptrbase) & D64_XS0_CD_MASK, dma64dd_t));
if (range == HNDDMA_RANGE_TRANSFERED) {
active_desc =
(u16) (R_REG(di->osh, &dregs->status1) &
(u16) (R_REG(&dregs->status1) &
D64_XS1_AD_MASK);
active_desc =
(active_desc - di->xmtptrbase) & D64_XS0_CD_MASK;
......@@ -1672,7 +1672,7 @@ static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall)
return NULL;
curr =
B2I(((R_REG(di->osh, &di->d64rxregs->status0) & D64_RS0_CD_MASK) -
B2I(((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) -
di->rcvptrbase) & D64_RS0_CD_MASK, dma64dd_t);
/* ignore curr if forceall */
......@@ -1705,9 +1705,9 @@ static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall)
static bool _dma64_addrext(struct osl_info *osh, dma64regs_t * dma64regs)
{
u32 w;
OR_REG(osh, &dma64regs->control, D64_XC_AE);
w = R_REG(osh, &dma64regs->control);
AND_REG(osh, &dma64regs->control, ~D64_XC_AE);
OR_REG(&dma64regs->control, D64_XC_AE);
w = R_REG(&dma64regs->control);
AND_REG(&dma64regs->control, ~D64_XC_AE);
return (w & D64_XC_AE) == D64_XC_AE;
}
......@@ -1727,7 +1727,7 @@ static void dma64_txrotate(dma_info_t *di)
nactive = _dma_txactive(di);
ad = (u16) (B2I
((((R_REG(di->osh, &di->d64txregs->status1) &
((((R_REG(&di->d64txregs->status1) &
D64_XS1_AD_MASK)
- di->xmtptrbase) & D64_XS1_AD_MASK), dma64dd_t));
rot = TXD(ad - di->txin);
......@@ -1786,7 +1786,7 @@ static void dma64_txrotate(dma_info_t *di)
di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
/* kick the chip */
W_REG(di->osh, &di->d64txregs->ptr,
W_REG(&di->d64txregs->ptr,
di->xmtptrbase + I2B(di->txout, dma64dd_t));
}
......
drivers/staging/brcm80211/util/nicpci.c
浏览文件 @ ff31c54c
......@@ -194,14 +194,14 @@ pcie_readreg(struct osl_info *osh, sbpcieregs_t *pcieregs, uint addrtype,
switch (addrtype) {
case PCIE_CONFIGREGS:
W_REG(osh, (&pcieregs->configaddr), offset);
(void)R_REG(osh, (&pcieregs->configaddr));
retval = R_REG(osh, &(pcieregs->configdata));
W_REG((&pcieregs->configaddr), offset);
(void)R_REG((&pcieregs->configaddr));
retval = R_REG(&(pcieregs->configdata));
break;
case PCIE_PCIEREGS:
W_REG(osh, &(pcieregs->pcieindaddr), offset);
(void)R_REG(osh, (&pcieregs->pcieindaddr));
retval = R_REG(osh, &(pcieregs->pcieinddata));
W_REG(&(pcieregs->pcieindaddr), offset);
(void)R_REG((&pcieregs->pcieindaddr));
retval = R_REG(&(pcieregs->pcieinddata));
break;
default:
ASSERT(0);
......@@ -219,12 +219,12 @@ pcie_writereg(struct osl_info *osh, sbpcieregs_t *pcieregs, uint addrtype,
switch (addrtype) {
case PCIE_CONFIGREGS:
W_REG(osh, (&pcieregs->configaddr), offset);
W_REG(osh, (&pcieregs->configdata), val);
W_REG((&pcieregs->configaddr), offset);
W_REG((&pcieregs->configdata), val);
break;
case PCIE_PCIEREGS:
W_REG(osh, (&pcieregs->pcieindaddr), offset);
W_REG(osh, (&pcieregs->pcieinddata), val);
W_REG((&pcieregs->pcieindaddr), offset);
W_REG((&pcieregs->pcieinddata), val);
break;
default:
ASSERT(0);
......@@ -244,12 +244,12 @@ static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk)
MDIODATA_DEVADDR_SHF) |
(MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) | MDIODATA_TA | (blk <<
4);
W_REG(pi->osh, &pcieregs->mdiodata, mdiodata);
W_REG(&pcieregs->mdiodata, mdiodata);
PR28829_DELAY();
/* retry till the transaction is complete */
while (i < pcie_serdes_spinwait) {
if (R_REG(pi->osh, &(pcieregs->mdiocontrol)) &
if (R_REG(&(pcieregs->mdiocontrol)) &
MDIOCTL_ACCESS_DONE) {
break;
}
......@@ -275,7 +275,7 @@ pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
uint pcie_serdes_spinwait = 10;
/* enable mdio access to SERDES */
W_REG(pi->osh, (&pcieregs->mdiocontrol),
W_REG((&pcieregs->mdiocontrol),
MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
if (pi->sih->buscorerev >= 10) {
......@@ -296,22 +296,22 @@ pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
mdiodata |=
(MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA | *val);
W_REG(pi->osh, &pcieregs->mdiodata, mdiodata);
W_REG(&pcieregs->mdiodata, mdiodata);
PR28829_DELAY();
/* retry till the transaction is complete */
while (i < pcie_serdes_spinwait) {
if (R_REG(pi->osh, &(pcieregs->mdiocontrol)) &
if (R_REG(&(pcieregs->mdiocontrol)) &
MDIOCTL_ACCESS_DONE) {
if (!write) {
PR28829_DELAY();
*val =
(R_REG(pi->osh, &(pcieregs->mdiodata)) &
(R_REG(&(pcieregs->mdiodata)) &
MDIODATA_MASK);
}
/* Disable mdio access to SERDES */
W_REG(pi->osh, (&pcieregs->mdiocontrol), 0);
W_REG((&pcieregs->mdiocontrol), 0);
return 0;
}
udelay(1000);
......@@ -320,7 +320,7 @@ pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
PCI_ERROR(("pcie_mdioop: timed out op: %d\n", write));
/* Disable mdio access to SERDES */
W_REG(pi->osh, (&pcieregs->mdiocontrol), 0);
W_REG((&pcieregs->mdiocontrol), 0);
return 1;
}
......@@ -466,7 +466,7 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
if (!ISSIM_ENAB(sih)) {
reg16 = &pcieregs->sprom[SRSH_ASPM_OFFSET];
val16 = R_REG(pi->osh, reg16);
val16 = R_REG(reg16);
val16 &= ~SRSH_ASPM_ENB;
if (pi->pcie_war_aspm_ovr == PCIE_ASPM_ENAB)
......@@ -476,7 +476,7 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L0s_ENAB)
val16 |= SRSH_ASPM_L0s_ENB;
W_REG(pi->osh, reg16, val16);
W_REG(reg16, val16);
pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset,
&w);
......@@ -487,7 +487,7 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
}
reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5];
val16 = R_REG(pi->osh, reg16);
val16 = R_REG(reg16);
if (pi->pcie_war_aspm_ovr != PCIE_ASPM_DISAB) {
val16 |= SRSH_CLKREQ_ENB;
......@@ -495,7 +495,7 @@ static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
} else
val16 &= ~SRSH_CLKREQ_ENB;
W_REG(pi->osh, reg16, val16);
W_REG(reg16, val16);
}
/* Apply the polarity determined at the start */
......@@ -523,11 +523,11 @@ static void pcie_misc_config_fixup(pcicore_info_t *pi)
u16 val16, *reg16;
reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG];
val16 = R_REG(pi->osh, reg16);
val16 = R_REG(reg16);
if ((val16 & SRSH_L23READY_EXIT_NOPERST) == 0) {
val16 |= SRSH_L23READY_EXIT_NOPERST;
W_REG(pi->osh, reg16, val16);
W_REG(reg16, val16);
}
}
......@@ -546,7 +546,7 @@ static void pcie_war_noplldown(pcicore_info_t *pi)
/* clear srom shadow backdoor */
reg16 = &pcieregs->sprom[SRSH_BD_OFFSET];
W_REG(pi->osh, reg16, 0);
W_REG(reg16, 0);
}
/* Needs to happen when coming out of 'standby'/'hibernate' */
......
drivers/staging/brcm80211/util/nvram/nvram_ro.c
浏览文件 @ ff31c54c
......@@ -48,13 +48,10 @@ static char *findvar(char *vars, char *lim, const char *name);
/* copy flash to ram */
static void get_flash_nvram(si_t *sih, struct nvram_header *nvh)
{
struct osl_info *osh;
uint nvs, bufsz;
vars_t *new;
osh = si_osh(sih);
nvs = R_REG(osh, &nvh->len) - sizeof(struct nvram_header);
nvs = R_REG(&nvh->len) - sizeof(struct nvram_header);
bufsz = nvs + VARS_T_OH;
new = kmalloc(bufsz, GFP_ATOMIC);
......
drivers/staging/brcm80211/util/sbutils.c
浏览文件 @ ff31c54c
......@@ -54,12 +54,12 @@ static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
static u32 sb_read_sbreg(si_info_t *sii, volatile u32 *sbr)
{
return R_REG(sii->osh, sbr);
return R_REG(sbr);
}
static void sb_write_sbreg(si_info_t *sii, volatile u32 *sbr, u32 v)
{
W_REG(sii->osh, sbr, v);
W_REG(sbr, v);
}
uint sb_coreid(si_t *sih)
......@@ -178,8 +178,8 @@ uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
w = (R_SBREG(sii, r) & ~mask) | val;
W_SBREG(sii, r, w);
} else {
w = (R_REG(sii->osh, r) & ~mask) | val;
W_REG(sii->osh, r, w);
w = (R_REG(r) & ~mask) | val;
W_REG(r, w);
}
}
......@@ -187,7 +187,7 @@ uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
if (regoff >= SBCONFIGOFF)
w = R_SBREG(sii, r);
else
w = R_REG(sii->osh, r);
w = R_REG(r);
if (!fast) {
/* restore core index */
......@@ -246,7 +246,7 @@ static uint _sb_scan(si_info_t *sii, u32 sba, void *regs, uint bus, u32 sbba,
total # cores in the chip */
if (((ccrev == 4) || (ccrev >= 6)))
numcores =
(R_REG(sii->osh, &cc->chipid) & CID_CC_MASK)
(R_REG(&cc->chipid) & CID_CC_MASK)
>> CID_CC_SHIFT;
else {
/* Older chips */
......
drivers/staging/brcm80211/util/siutils.c
浏览文件 @ ff31c54c
......@@ -180,19 +180,19 @@ static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
/* get chipcommon chipstatus */
if (sii->pub.ccrev >= 11)
sii->pub.chipst = R_REG(sii->osh, &cc->chipstatus);
sii->pub.chipst = R_REG(&cc->chipstatus);
/* get chipcommon capabilites */
sii->pub.cccaps = R_REG(sii->osh, &cc->capabilities);
sii->pub.cccaps = R_REG(&cc->capabilities);
/* get chipcommon extended capabilities */
#ifndef BRCM_FULLMAC
if (sii->pub.ccrev >= 35)
sii->pub.cccaps_ext = R_REG(sii->osh, &cc->capabilities_ext);
sii->pub.cccaps_ext = R_REG(&cc->capabilities_ext);
#endif
/* get pmu rev and caps */
if (sii->pub.cccaps & CC_CAP_PMU) {
sii->pub.pmucaps = R_REG(sii->osh, &cc->pmucapabilities);
sii->pub.pmucaps = R_REG(&cc->pmucapabilities);
sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
}
......@@ -404,7 +404,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
* If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
* some way of recognizing them needs to be added here.
*/
w = R_REG(osh, &cc->chipid);
w = R_REG(&cc->chipid);
sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
/* Might as wll fill in chip id rev & pkg */
sih->chip = w & CID_ID_MASK;
......@@ -455,8 +455,8 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
if (sii->pub.ccrev >= 20) {
#endif
cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
W_REG(osh, &cc->gpiopullup, 0);
W_REG(osh, &cc->gpiopulldown, 0);
W_REG(&cc->gpiopullup, 0);
W_REG(&cc->gpiopulldown, 0);
sb_setcoreidx(sih, origidx);
#ifdef BRCM_FULLMAC
}
......@@ -555,7 +555,7 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
* If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
* some way of recognizing them needs to be added here.
*/
w = R_REG(osh, &cc->chipid);
w = R_REG(&cc->chipid);
sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
/* Might as wll fill in chip id rev & pkg */
sih->chip = w & CID_ID_MASK;
......@@ -595,10 +595,10 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
if ((cc->chipstatus & CST43236_BP_CLK) != 0) {
uint clkdiv;
clkdiv = R_REG(osh, &cc->clkdiv);
clkdiv = R_REG(&cc->clkdiv);
/* otp_clk_div is even number, 120/14 < 9mhz */
clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT);
W_REG(osh, &cc->clkdiv, clkdiv);
W_REG(&cc->clkdiv, clkdiv);
SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv));
}
udelay(10);
......@@ -618,8 +618,8 @@ static si_info_t *si_doattach(si_info_t *sii, uint devid, struct osl_info *osh,
/* === NVRAM, clock is ready === */
cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
W_REG(osh, &cc->gpiopullup, 0);
W_REG(osh, &cc->gpiopulldown, 0);
W_REG(&cc->gpiopullup, 0);
W_REG(&cc->gpiopulldown, 0);
si_setcoreidx(sih, origidx);
/* PMU specific initializations */
......@@ -1095,7 +1095,7 @@ static uint si_slowclk_src(si_info_t *sii)
return SCC_SS_XTAL;
} else if (sii->pub.ccrev < 10) {
cc = (chipcregs_t *) si_setcoreidx(&sii->pub, sii->curidx);
return R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_SS_MASK;
return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
} else /* Insta-clock */
return SCC_SS_XTAL;
}
......@@ -1109,7 +1109,7 @@ static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
/* shouldn't be here unless we've established the chip has dynamic clk control */
ASSERT(R_REG(sii->osh, &cc->capabilities) & CC_CAP_PWR_CTL);
ASSERT(R_REG(&cc->capabilities) & CC_CAP_PWR_CTL);
slowclk = si_slowclk_src(sii);
if (sii->pub.ccrev < 6) {
......@@ -1121,7 +1121,7 @@ static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
: (XTALMINFREQ / 32);
} else if (sii->pub.ccrev < 10) {
div = 4 *
(((R_REG(sii->osh, &cc->slow_clk_ctl) & SCC_CD_MASK) >>
(((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >>
SCC_CD_SHIFT) + 1);
if (slowclk == SCC_SS_LPO)
return max_freq ? LPOMAXFREQ : LPOMINFREQ;
......@@ -1135,7 +1135,7 @@ static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
ASSERT(0);
} else {
/* Chipc rev 10 is InstaClock */
div = R_REG(sii->osh, &cc->system_clk_ctl) >> SYCC_CD_SHIFT;
div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
div = 4 * (div + 1);
return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
}
......@@ -1165,8 +1165,8 @@ static void si_clkctl_setdelay(si_info_t *sii, void *chipcregs)
pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
W_REG(sii->osh, &cc->pll_on_delay, pll_on_delay);
W_REG(sii->osh, &cc->fref_sel_delay, fref_sel_delay);
W_REG(&cc->pll_on_delay, pll_on_delay);
W_REG(&cc->fref_sel_delay, fref_sel_delay);
}
/* initialize power control delay registers */
......@@ -1196,7 +1196,7 @@ void si_clkctl_init(si_t *sih)
/* set all Instaclk chip ILP to 1 MHz */
if (sih->ccrev >= 10)
SET_REG(sii->osh, &cc->system_clk_ctl, SYCC_CD_MASK,
SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK,
(ILP_DIV_1MHZ << SYCC_CD_SHIFT));
si_clkctl_setdelay(sii, (void *)cc);
......@@ -1243,7 +1243,7 @@ u16 si_clkctl_fast_pwrup_delay(si_t *sih)
ASSERT(cc != NULL);
slowminfreq = si_slowclk_freq(sii, false, cc);
fpdelay = (((R_REG(sii->osh, &cc->pll_on_delay) + 2) * 1000000) +
fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +
(slowminfreq - 1)) / slowminfreq;
done:
......@@ -1394,20 +1394,20 @@ static bool _si_clkctl_cc(si_info_t *sii, uint mode)
if (sii->pub.ccrev < 10) {
/* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
si_clkctl_xtal(&sii->pub, XTAL, ON);
SET_REG(sii->osh, &cc->slow_clk_ctl,
SET_REG(&cc->slow_clk_ctl,
(SCC_XC | SCC_FS | SCC_IP), SCC_IP);
} else if (sii->pub.ccrev < 20) {
OR_REG(sii->osh, &cc->system_clk_ctl, SYCC_HR);
OR_REG(&cc->system_clk_ctl, SYCC_HR);
} else {
OR_REG(sii->osh, &cc->clk_ctl_st, CCS_FORCEHT);
OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);
}
/* wait for the PLL */
if (PMUCTL_ENAB(&sii->pub)) {
u32 htavail = CCS_HTAVAIL;
SPINWAIT(((R_REG(sii->osh, &cc->clk_ctl_st) & htavail)
SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
== 0), PMU_MAX_TRANSITION_DLY);
ASSERT(R_REG(sii->osh, &cc->clk_ctl_st) & htavail);
ASSERT(R_REG(&cc->clk_ctl_st) & htavail);
} else {
udelay(PLL_DELAY);
}
......@@ -1415,20 +1415,20 @@ static bool _si_clkctl_cc(si_info_t *sii, uint mode)
case CLK_DYNAMIC: /* enable dynamic clock control */
if (sii->pub.ccrev < 10) {
scc = R_REG(sii->osh, &cc->slow_clk_ctl);
scc = R_REG(&cc->slow_clk_ctl);
scc &= ~(SCC_FS | SCC_IP | SCC_XC);
if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
scc |= SCC_XC;
W_REG(sii->osh, &cc->slow_clk_ctl, scc);
W_REG(&cc->slow_clk_ctl, scc);
/* for dynamic control, we have to release our xtal_pu "force on" */
if (scc & SCC_XC)
si_clkctl_xtal(&sii->pub, XTAL, OFF);
} else if (sii->pub.ccrev < 20) {
/* Instaclock */
AND_REG(sii->osh, &cc->system_clk_ctl, ~SYCC_HR);
AND_REG(&cc->system_clk_ctl, ~SYCC_HR);
} else {
AND_REG(sii->osh, &cc->clk_ctl_st, ~CCS_FORCEHT);
AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT);
}
break;
......@@ -1583,8 +1583,8 @@ void si_sdio_init(si_t *sih)
SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih->buscorerev, idx, sii->curidx, sdpregs));
/* enable backplane error and core interrupts */
W_REG(sii->osh, &sdpregs->hostintmask, I_SBINT);
W_REG(sii->osh, &sdpregs->sbintmask,
W_REG(&sdpregs->hostintmask, I_SBINT);
W_REG(&sdpregs->sbintmask,
(I_SB_SERR | I_SB_RESPERR | (1 << idx)));
/* switch back to previous core */
......@@ -1697,15 +1697,15 @@ void si_pci_setup(si_t *sih, uint coremask)
}
if (PCI(sii)) {
OR_REG(sii->osh, &pciregs->sbtopci2,
OR_REG(&pciregs->sbtopci2,
(SBTOPCI_PREF | SBTOPCI_BURST));
if (sii->pub.buscorerev >= 11) {
OR_REG(sii->osh, &pciregs->sbtopci2,
OR_REG(&pciregs->sbtopci2,
SBTOPCI_RC_READMULTI);
w = R_REG(sii->osh, &pciregs->clkrun);
W_REG(sii->osh, &pciregs->clkrun,
w = R_REG(&pciregs->clkrun);
W_REG(&pciregs->clkrun,
(w | PCI_CLKRUN_DSBL));
w = R_REG(sii->osh, &pciregs->clkrun);
w = R_REG(&pciregs->clkrun);
}
/* switch back to previous core */
......@@ -1747,12 +1747,12 @@ int si_pci_fixcfg(si_t *sih)
reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
}
pciidx = si_coreidx(&sii->pub);
val16 = R_REG(sii->osh, reg16);
val16 = R_REG(reg16);
if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) {
val16 =
(u16) (pciidx << SRSH_PI_SHIFT) | (val16 &
~SRSH_PI_MASK);
W_REG(sii->osh, reg16, val16);
W_REG(reg16, val16);
}
/* restore the original index */
......@@ -1793,8 +1793,8 @@ socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index,
ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM);
W_REG(sii->osh, &regs->bankidx, bankidx);
bankinfo = R_REG(sii->osh, &regs->bankinfo);
W_REG(&regs->bankidx, bankidx);
bankinfo = R_REG(&regs->bankinfo);
banksize =
SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1);
return banksize;
......@@ -1829,7 +1829,7 @@ u32 si_socram_size(si_t *sih)
if (!wasup)
si_core_reset(sih, 0, 0);
corerev = si_corerev(sih);
coreinfo = R_REG(sii->osh, &regs->coreinfo);
coreinfo = R_REG(&regs->coreinfo);
/* Calculate size from coreinfo based on rev */
if (corerev == 0)
......@@ -1877,22 +1877,22 @@ void si_chipcontrl_epa4331(si_t *sih, bool on)
cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
val = R_REG(sii->osh, &cc->chipcontrol);
val = R_REG(&cc->chipcontrol);
if (on) {
if (sih->chippkg == 9 || sih->chippkg == 0xb) {
/* Ext PA Controls for 4331 12x9 Package */
W_REG(sii->osh, &cc->chipcontrol, val |
W_REG(&cc->chipcontrol, val |
(CCTRL4331_EXTPA_EN |
CCTRL4331_EXTPA_ON_GPIO2_5));
} else {
/* Ext PA Controls for 4331 12x12 Package */
W_REG(sii->osh, &cc->chipcontrol,
W_REG(&cc->chipcontrol,
val | (CCTRL4331_EXTPA_EN));
}
} else {
val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
W_REG(sii->osh, &cc->chipcontrol, val);
W_REG(&cc->chipcontrol, val);
}
si_setcoreidx(sih, origidx);
......@@ -1911,8 +1911,8 @@ void si_epa_4313war(si_t *sih)
cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
/* EPA Fix */
W_REG(sii->osh, &cc->gpiocontrol,
R_REG(sii->osh, &cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
W_REG(&cc->gpiocontrol,
R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
si_setcoreidx(sih, origidx);
}
......@@ -1950,7 +1950,7 @@ bool si_is_sprom_available(si_t *sih)
sii = SI_INFO(sih);
origidx = sii->curidx;
cc = si_setcoreidx(sih, SI_CC_IDX);
sromctrl = R_REG(sii->osh, &cc->sromcontrol);
sromctrl = R_REG(&cc->sromcontrol);
si_setcoreidx(sih, origidx);
return sromctrl & SRC_PRESENT;
}
......
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