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提交 fc2834a4 编写于 作者: O Olof Johansson
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Merge tag 'renesas-dt-for-v4.6' of... 

Merge tag 'renesas-dt-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM Based SoC DT Updates for v4.6

* Use SCIF and USBHS fallback compatibility strings
* Add Baud Rate Generator (BRG) support for (H)SCIF
* Enable SCIF_CLK frequency and pins
* Use GIC_* defines
* Enable audio on r8a7793/gose
* Enable HDMI vidio out on r8a7793
* Enable i2c on r8a7793/gose
* Enable QSPI on alt
* Enable GPIO keys and leds on gise
* Enable audio on porter
* Enable DU on porter

* tag 'renesas-dt-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (68 commits)
  ARM: dts: silk: Enable SCIF_CLK frequency and pins
  ARM: dts: porter: Enable SCIF_CLK frequency and pins
  ARM: dts: marzen: Enable SCIF_CLK frequency and pins
  ARM: dts: lager: Enable SCIF_CLK frequency and pins
  ARM: dts: koelsch: Enable SCIF_CLK frequency and pins
  ARM: dts: gose: Enable SCIF_CLK frequency and pins
  ARM: dts: bockw: Enable SCIF_CLK frequency and pins
  ARM: dts: alt: Enable SCIF_CLK frequency and pins
  ARM: dts: r8a7794: Add BRG support for (H)SCIF
  ARM: dts: r8a7793: Add BRG support for SCIF
  ARM: dts: r8a7791: Add BRG support for (H)SCIF
  ARM: dts: r8a7790: Add BRG support for (H)SCIF
  ARM: dts: r8a7779: Add BRG support for SCIF
  ARM: dts: r8a7778: Add BRG support for SCIF
  ARM: dts: r8a7794: Rename the serial port clock to fck
  ARM: dts: r8a7793: Rename the serial port clock to fck
  ARM: dts: r8a7791: Rename the serial port clock to fck
  ARM: dts: r8a7790: Rename the serial port clock to fck
  ARM: dts: r8a7779: Rename the serial port clock to fck
  ARM: dts: r8a7778: Rename the serial port clock to fck
  ...
Signed-off-by: NOlof Johansson <olof@lixom.net>
上级 f68a4535 c3373b09
展开全部 隐藏空白更改
内联 并排
Showing with 2569 addition and 1276 deletion
arch/arm/boot/dts/emev2.dtsi
浏览文件 @ fc2834a4
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
*/ */
#include "skeleton.dtsi" #include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
/ { / {
...@@ -53,8 +54,8 @@ ...@@ -53,8 +54,8 @@
pmu { pmu {
compatible = "arm,cortex-a9-pmu"; compatible = "arm,cortex-a9-pmu";
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<0 121 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
}; };
clocks@e0110000 { clocks@e0110000 {
...@@ -158,7 +159,7 @@ ...@@ -158,7 +159,7 @@
timer@e0180000 { timer@e0180000 {
compatible = "renesas,em-sti"; compatible = "renesas,em-sti";
reg = <0xe0180000 0x54>; reg = <0xe0180000 0x54>;
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sti_sclk>; clocks = <&sti_sclk>;
clock-names = "sclk"; clock-names = "sclk";
}; };
...@@ -166,7 +167,7 @@ ...@@ -166,7 +167,7 @@
uart0: serial@e1020000 { uart0: serial@e1020000 {
compatible = "renesas,em-uart"; compatible = "renesas,em-uart";
reg = <0xe1020000 0x38>; reg = <0xe1020000 0x38>;
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usia_u0_sclk>; clocks = <&usia_u0_sclk>;
clock-names = "sclk"; clock-names = "sclk";
}; };
...@@ -174,7 +175,7 @@ ...@@ -174,7 +175,7 @@
uart1: serial@e1030000 { uart1: serial@e1030000 {
compatible = "renesas,em-uart"; compatible = "renesas,em-uart";
reg = <0xe1030000 0x38>; reg = <0xe1030000 0x38>;
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usib_u1_sclk>; clocks = <&usib_u1_sclk>;
clock-names = "sclk"; clock-names = "sclk";
}; };
...@@ -182,7 +183,7 @@ ...@@ -182,7 +183,7 @@
uart2: serial@e1040000 { uart2: serial@e1040000 {
compatible = "renesas,em-uart"; compatible = "renesas,em-uart";
reg = <0xe1040000 0x38>; reg = <0xe1040000 0x38>;
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usib_u2_sclk>; clocks = <&usib_u2_sclk>;
clock-names = "sclk"; clock-names = "sclk";
}; };
...@@ -190,7 +191,7 @@ ...@@ -190,7 +191,7 @@
uart3: serial@e1050000 { uart3: serial@e1050000 {
compatible = "renesas,em-uart"; compatible = "renesas,em-uart";
reg = <0xe1050000 0x38>; reg = <0xe1050000 0x38>;
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&usib_u3_sclk>; clocks = <&usib_u3_sclk>;
clock-names = "sclk"; clock-names = "sclk";
}; };
...@@ -203,8 +204,8 @@ ...@@ -203,8 +204,8 @@
gpio0: gpio@e0050000 { gpio0: gpio@e0050000 {
compatible = "renesas,em-gio"; compatible = "renesas,em-gio";
reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
<0 68 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 0 32>; gpio-ranges = <&pfc 0 0 32>;
#gpio-cells = <2>; #gpio-cells = <2>;
...@@ -215,8 +216,8 @@ ...@@ -215,8 +216,8 @@
gpio1: gpio@e0050080 { gpio1: gpio@e0050080 {
compatible = "renesas,em-gio"; compatible = "renesas,em-gio";
reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>; reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<0 70 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 32 32>; gpio-ranges = <&pfc 0 32 32>;
#gpio-cells = <2>; #gpio-cells = <2>;
...@@ -227,8 +228,8 @@ ...@@ -227,8 +228,8 @@
gpio2: gpio@e0050100 { gpio2: gpio@e0050100 {
compatible = "renesas,em-gio"; compatible = "renesas,em-gio";
reg = <0xe0050100 0x2c>, <0xe0050140 0x20>; reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<0 72 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 64 32>; gpio-ranges = <&pfc 0 64 32>;
#gpio-cells = <2>; #gpio-cells = <2>;
...@@ -239,8 +240,8 @@ ...@@ -239,8 +240,8 @@
gpio3: gpio@e0050180 { gpio3: gpio@e0050180 {
compatible = "renesas,em-gio"; compatible = "renesas,em-gio";
reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>; reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<0 74 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 96 32>; gpio-ranges = <&pfc 0 96 32>;
#gpio-cells = <2>; #gpio-cells = <2>;
...@@ -251,8 +252,8 @@ ...@@ -251,8 +252,8 @@
gpio4: gpio@e0050200 { gpio4: gpio@e0050200 {
compatible = "renesas,em-gio"; compatible = "renesas,em-gio";
reg = <0xe0050200 0x2c>, <0xe0050240 0x20>; reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<0 76 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 128 31>; gpio-ranges = <&pfc 0 128 31>;
#gpio-cells = <2>; #gpio-cells = <2>;
...@@ -266,7 +267,7 @@ ...@@ -266,7 +267,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-emev2"; compatible = "renesas,iic-emev2";
reg = <0xe0070000 0x28>; reg = <0xe0070000 0x28>;
interrupts = <0 32 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
clocks = <&iic0_sclk>; clocks = <&iic0_sclk>;
clock-names = "sclk"; clock-names = "sclk";
status = "disabled"; status = "disabled";
...@@ -277,7 +278,7 @@ ...@@ -277,7 +278,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-emev2"; compatible = "renesas,iic-emev2";
reg = <0xe10a0000 0x28>; reg = <0xe10a0000 0x28>;
interrupts = <0 33 IRQ_TYPE_EDGE_RISING>; interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
clocks = <&iic1_sclk>; clocks = <&iic1_sclk>;
clock-names = "sclk"; clock-names = "sclk";
status = "disabled"; status = "disabled";
......
arch/arm/boot/dts/r7s72100.dtsi
浏览文件 @ fc2834a4
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
*/ */
#include <dt-bindings/clock/r7s72100-clock.h> #include <dt-bindings/clock/r7s72100-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
/ { / {
...@@ -152,12 +153,12 @@ ...@@ -152,12 +153,12 @@
scif0: serial@e8007000 { scif0: serial@e8007000 {
compatible = "renesas,scif-r7s72100", "renesas,scif"; compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8007000 64>; reg = <0xe8007000 64>;
interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<0 191 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<0 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<0 189 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF0>; clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
...@@ -165,12 +166,12 @@ ...@@ -165,12 +166,12 @@
scif1: serial@e8007800 { scif1: serial@e8007800 {
compatible = "renesas,scif-r7s72100", "renesas,scif"; compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8007800 64>; reg = <0xe8007800 64>;
interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
<0 195 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
<0 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
<0 193 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF1>; clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
...@@ -178,12 +179,12 @@ ...@@ -178,12 +179,12 @@
scif2: serial@e8008000 { scif2: serial@e8008000 {
compatible = "renesas,scif-r7s72100", "renesas,scif"; compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8008000 64>; reg = <0xe8008000 64>;
interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<0 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<0 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<0 197 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF2>; clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
...@@ -191,12 +192,12 @@ ...@@ -191,12 +192,12 @@
scif3: serial@e8008800 { scif3: serial@e8008800 {
compatible = "renesas,scif-r7s72100", "renesas,scif"; compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8008800 64>; reg = <0xe8008800 64>;
interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<0 203 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
<0 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
<0 201 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF3>; clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
...@@ -204,12 +205,12 @@ ...@@ -204,12 +205,12 @@
scif4: serial@e8009000 { scif4: serial@e8009000 {
compatible = "renesas,scif-r7s72100", "renesas,scif"; compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8009000 64>; reg = <0xe8009000 64>;
interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
<0 207 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
<0 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
<0 205 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF4>; clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
...@@ -217,12 +218,12 @@ ...@@ -217,12 +218,12 @@
scif5: serial@e8009800 { scif5: serial@e8009800 {
compatible = "renesas,scif-r7s72100", "renesas,scif"; compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe8009800 64>; reg = <0xe8009800 64>;
interrupts = <0 210 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<0 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
<0 212 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
<0 209 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF5>; clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
...@@ -230,12 +231,12 @@ ...@@ -230,12 +231,12 @@
scif6: serial@e800a000 { scif6: serial@e800a000 {
compatible = "renesas,scif-r7s72100", "renesas,scif"; compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe800a000 64>; reg = <0xe800a000 64>;
interrupts = <0 214 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
<0 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
<0 216 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
<0 213 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF6>; clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
...@@ -243,12 +244,12 @@ ...@@ -243,12 +244,12 @@
scif7: serial@e800a800 { scif7: serial@e800a800 {
compatible = "renesas,scif-r7s72100", "renesas,scif"; compatible = "renesas,scif-r7s72100", "renesas,scif";
reg = <0xe800a800 64>; reg = <0xe800a800 64>;
interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<0 219 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<0 220 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<0 217 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R7S72100_CLK_SCIF7>; clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
...@@ -256,9 +257,9 @@ ...@@ -256,9 +257,9 @@
spi0: spi@e800c800 { spi0: spi@e800c800 {
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
reg = <0xe800c800 0x24>; reg = <0xe800c800 0x24>;
interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
<0 239 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
<0 240 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx"; interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI0>; clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -271,9 +272,9 @@ ...@@ -271,9 +272,9 @@
spi1: spi@e800d000 { spi1: spi@e800d000 {
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
reg = <0xe800d000 0x24>; reg = <0xe800d000 0x24>;
interrupts = <0 241 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
<0 242 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<0 243 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx"; interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI1>; clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -286,9 +287,9 @@ ...@@ -286,9 +287,9 @@
spi2: spi@e800d800 { spi2: spi@e800d800 {
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
reg = <0xe800d800 0x24>; reg = <0xe800d800 0x24>;
interrupts = <0 244 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<0 245 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<0 246 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx"; interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI2>; clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -301,9 +302,9 @@ ...@@ -301,9 +302,9 @@
spi3: spi@e800e000 { spi3: spi@e800e000 {
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
reg = <0xe800e000 0x24>; reg = <0xe800e000 0x24>;
interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<0 248 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<0 249 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx"; interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI3>; clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -316,9 +317,9 @@ ...@@ -316,9 +317,9 @@
spi4: spi@e800e800 { spi4: spi@e800e800 {
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz"; compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
reg = <0xe800e800 0x24>; reg = <0xe800e800 0x24>;
interrupts = <0 250 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<0 251 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<0 252 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx"; interrupt-names = "error", "rx", "tx";
clocks = <&mstp10_clks R7S72100_CLK_SPI4>; clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -342,14 +343,14 @@ ...@@ -342,14 +343,14 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
reg = <0xfcfee000 0x44>; reg = <0xfcfee000 0x44>;
interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<0 158 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
<0 159 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
<0 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<0 161 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<0 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
<0 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<0 164 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C0>; clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
clock-frequency = <100000>; clock-frequency = <100000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -361,14 +362,14 @@ ...@@ -361,14 +362,14 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
reg = <0xfcfee400 0x44>; reg = <0xfcfee400 0x44>;
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
<0 166 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
<0 167 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
<0 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<0 169 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<0 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<0 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<0 172 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C1>; clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
clock-frequency = <100000>; clock-frequency = <100000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -380,14 +381,14 @@ ...@@ -380,14 +381,14 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
reg = <0xfcfee800 0x44>; reg = <0xfcfee800 0x44>;
interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
<0 174 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
<0 175 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
<0 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
<0 177 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
<0 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<0 179 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
<0 180 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C2>; clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
clock-frequency = <100000>; clock-frequency = <100000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -399,14 +400,14 @@ ...@@ -399,14 +400,14 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
reg = <0xfcfeec00 0x44>; reg = <0xfcfeec00 0x44>;
interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<0 182 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
<0 183 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
<0 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<0 185 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<0 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<0 187 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<0 188 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R7S72100_CLK_I2C3>; clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
clock-frequency = <100000>; clock-frequency = <100000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -416,7 +417,7 @@ ...@@ -416,7 +417,7 @@
mtu2: timer@fcff0000 { mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>; reg = <0xfcff0000 0x400>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tgi0a"; interrupt-names = "tgi0a";
clocks = <&mstp3_clks R7S72100_CLK_MTU2>; clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
clock-names = "fck"; clock-names = "fck";
......
arch/arm/boot/dts/r8a73a4.dtsi
浏览文件 @ fc2834a4
...@@ -39,10 +39,10 @@ ...@@ -39,10 +39,10 @@
timer { timer {
compatible = "arm,armv7-timer"; compatible = "arm,armv7-timer";
interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
}; };
dbsc1: memory-controller@e6790000 { dbsc1: memory-controller@e6790000 {
...@@ -69,27 +69,27 @@ ...@@ -69,27 +69,27 @@
dma0: dma-controller@e6700020 { dma0: dma-controller@e6700020 {
compatible = "renesas,shdma-r8a73a4"; compatible = "renesas,shdma-r8a73a4";
reg = <0 0xe6700020 0 0x89e0>; reg = <0 0xe6700020 0 0x89e0>;
interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
0 200 IRQ_TYPE_LEVEL_HIGH GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
0 201 IRQ_TYPE_LEVEL_HIGH GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
0 202 IRQ_TYPE_LEVEL_HIGH GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
0 203 IRQ_TYPE_LEVEL_HIGH GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
0 204 IRQ_TYPE_LEVEL_HIGH GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
0 205 IRQ_TYPE_LEVEL_HIGH GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
0 206 IRQ_TYPE_LEVEL_HIGH GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
0 207 IRQ_TYPE_LEVEL_HIGH GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
0 208 IRQ_TYPE_LEVEL_HIGH GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
0 209 IRQ_TYPE_LEVEL_HIGH GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
0 210 IRQ_TYPE_LEVEL_HIGH GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
0 211 IRQ_TYPE_LEVEL_HIGH GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
0 212 IRQ_TYPE_LEVEL_HIGH GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
0 213 IRQ_TYPE_LEVEL_HIGH GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
0 214 IRQ_TYPE_LEVEL_HIGH GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
0 215 IRQ_TYPE_LEVEL_HIGH GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
0 216 IRQ_TYPE_LEVEL_HIGH GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
0 217 IRQ_TYPE_LEVEL_HIGH GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
0 218 IRQ_TYPE_LEVEL_HIGH GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
0 219 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3", "ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7", "ch4", "ch5", "ch6", "ch7",
...@@ -106,7 +106,7 @@ ...@@ -106,7 +106,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x428>; reg = <0 0xe60b0000 0 0x428>;
interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
...@@ -116,7 +116,7 @@ ...@@ -116,7 +116,7 @@
cmt1: timer@e6130000 { cmt1: timer@e6130000 {
compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
reg = <0 0xe6130000 0 0x1004>; reg = <0 0xe6130000 0 0x1004>;
interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&pd_c5>; power-domains = <&pd_c5>;
...@@ -131,38 +131,38 @@ ...@@ -131,38 +131,38 @@
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
reg = <0 0xe61c0000 0 0x200>; reg = <0 0xe61c0000 0 0x200>;
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<0 1 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<0 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<0 3 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<0 4 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<0 5 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<0 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<0 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<0 8 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<0 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<0 10 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<0 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<0 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<0 13 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<0 14 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<0 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<0 16 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<0 17 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<0 18 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<0 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<0 20 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<0 21 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<0 22 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<0 23 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<0 24 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<0 25 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<0 26 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<0 27 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<0 28 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<0 29 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<0 30 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<0 31 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
power-domains = <&pd_c4>; power-domains = <&pd_c4>;
}; };
...@@ -172,32 +172,32 @@ ...@@ -172,32 +172,32 @@
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
reg = <0 0xe61c0200 0 0x200>; reg = <0 0xe61c0200 0 0x200>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<0 33 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<0 34 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<0 35 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<0 36 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<0 37 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<0 38 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<0 39 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<0 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<0 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<0 42 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<0 43 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<0 44 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<0 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<0 46 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<0 47 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<0 48 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<0 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<0 50 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<0 51 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<0 52 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<0 53 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<0 54 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<0 55 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<0 56 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<0 57 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; clocks = <&mstp4_clks R8A73A4_CLK_IRQC>;
power-domains = <&pd_c4>; power-domains = <&pd_c4>;
}; };
...@@ -237,7 +237,7 @@ ...@@ -237,7 +237,7 @@
compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
<0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
power-domains = <&pd_c5>; power-domains = <&pd_c5>;
}; };
...@@ -247,7 +247,7 @@ ...@@ -247,7 +247,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
reg = <0 0xe6500000 0 0x428>; reg = <0 0xe6500000 0 0x428>;
interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
...@@ -258,7 +258,7 @@ ...@@ -258,7 +258,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
reg = <0 0xe6510000 0 0x428>; reg = <0 0xe6510000 0 0x428>;
interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
...@@ -269,7 +269,7 @@ ...@@ -269,7 +269,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
reg = <0 0xe6520000 0 0x428>; reg = <0 0xe6520000 0 0x428>;
interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
...@@ -280,7 +280,7 @@ ...@@ -280,7 +280,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
reg = <0 0xe6530000 0 0x428>; reg = <0 0xe6530000 0 0x428>;
interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
...@@ -291,7 +291,7 @@ ...@@ -291,7 +291,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
reg = <0 0xe6540000 0 0x428>; reg = <0 0xe6540000 0 0x428>;
interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
...@@ -302,7 +302,7 @@ ...@@ -302,7 +302,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
reg = <0 0xe6550000 0 0x428>; reg = <0 0xe6550000 0 0x428>;
interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
...@@ -313,7 +313,7 @@ ...@@ -313,7 +313,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
reg = <0 0xe6560000 0 0x428>; reg = <0 0xe6560000 0 0x428>;
interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
...@@ -324,7 +324,7 @@ ...@@ -324,7 +324,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
reg = <0 0xe6570000 0 0x428>; reg = <0 0xe6570000 0 0x428>;
interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
...@@ -333,9 +333,9 @@ ...@@ -333,9 +333,9 @@
scifb0: serial@e6c20000 { scifb0: serial@e6c20000 {
compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
reg = <0 0xe6c20000 0 0x100>; reg = <0 0xe6c20000 0 0x100>;
interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -343,9 +343,9 @@ ...@@ -343,9 +343,9 @@
scifb1: serial@e6c30000 { scifb1: serial@e6c30000 {
compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
reg = <0 0xe6c30000 0 0x100>; reg = <0 0xe6c30000 0 0x100>;
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -353,9 +353,9 @@ ...@@ -353,9 +353,9 @@
scifa0: serial@e6c40000 { scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
reg = <0 0xe6c40000 0 0x100>; reg = <0 0xe6c40000 0 0x100>;
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -363,9 +363,9 @@ ...@@ -363,9 +363,9 @@
scifa1: serial@e6c50000 { scifa1: serial@e6c50000 {
compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
reg = <0 0xe6c50000 0 0x100>; reg = <0 0xe6c50000 0 0x100>;
interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -373,9 +373,9 @@ ...@@ -373,9 +373,9 @@
scifb2: serial@e6ce0000 { scifb2: serial@e6ce0000 {
compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
reg = <0 0xe6ce0000 0 0x100>; reg = <0 0xe6ce0000 0 0x100>;
interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -383,9 +383,9 @@ ...@@ -383,9 +383,9 @@
scifb3: serial@e6cf0000 { scifb3: serial@e6cf0000 {
compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
reg = <0 0xe6cf0000 0 0x100>; reg = <0 0xe6cf0000 0 0x100>;
interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_c4>; power-domains = <&pd_c4>;
status = "disabled"; status = "disabled";
}; };
...@@ -393,7 +393,7 @@ ...@@ -393,7 +393,7 @@
sdhi0: sd@ee100000 { sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a73a4"; compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee100000 0 0x100>; reg = <0 0xee100000 0 0x100>;
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
cap-sd-highspeed; cap-sd-highspeed;
...@@ -403,7 +403,7 @@ ...@@ -403,7 +403,7 @@
sdhi1: sd@ee120000 { sdhi1: sd@ee120000 {
compatible = "renesas,sdhi-r8a73a4"; compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee120000 0 0x100>; reg = <0 0xee120000 0 0x100>;
interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
cap-sd-highspeed; cap-sd-highspeed;
...@@ -413,7 +413,7 @@ ...@@ -413,7 +413,7 @@
sdhi2: sd@ee140000 { sdhi2: sd@ee140000 {
compatible = "renesas,sdhi-r8a73a4"; compatible = "renesas,sdhi-r8a73a4";
reg = <0 0xee140000 0 0x100>; reg = <0 0xee140000 0 0x100>;
interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
cap-sd-highspeed; cap-sd-highspeed;
...@@ -423,7 +423,7 @@ ...@@ -423,7 +423,7 @@
mmcif0: mmc@ee200000 { mmcif0: mmc@ee200000 {
compatible = "renesas,sh-mmcif"; compatible = "renesas,sh-mmcif";
reg = <0 0xee200000 0 0x80>; reg = <0 0xee200000 0 0x80>;
interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
reg-io-width = <4>; reg-io-width = <4>;
...@@ -433,7 +433,7 @@ ...@@ -433,7 +433,7 @@
mmcif1: mmc@ee220000 { mmcif1: mmc@ee220000 {
compatible = "renesas,sh-mmcif"; compatible = "renesas,sh-mmcif";
reg = <0 0xee220000 0 0x80>; reg = <0 0xee220000 0 0x80>;
interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
reg-io-width = <4>; reg-io-width = <4>;
...@@ -449,7 +449,7 @@ ...@@ -449,7 +449,7 @@
<0 0xf1002000 0 0x1000>, <0 0xf1002000 0 0x1000>,
<0 0xf1004000 0 0x2000>, <0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>; <0 0xf1006000 0 0x2000>;
interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
}; };
bsc: bus@fec10000 { bsc: bus@fec10000 {
......
arch/arm/boot/dts/r8a7740.dtsi
浏览文件 @ fc2834a4
...@@ -11,6 +11,7 @@ ...@@ -11,6 +11,7 @@
/include/ "skeleton.dtsi" /include/ "skeleton.dtsi"
#include <dt-bindings/clock/r8a7740-clock.h> #include <dt-bindings/clock/r8a7740-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
/ { / {
...@@ -41,7 +42,7 @@ ...@@ -41,7 +42,7 @@
L2: cache-controller { L2: cache-controller {
compatible = "arm,pl310-cache"; compatible = "arm,pl310-cache";
reg = <0xf0100000 0x1000>; reg = <0xf0100000 0x1000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_a3sm>; power-domains = <&pd_a3sm>;
arm,data-latency = <3 3 3>; arm,data-latency = <3 3 3>;
arm,tag-latency = <2 2 2>; arm,tag-latency = <2 2 2>;
...@@ -58,7 +59,7 @@ ...@@ -58,7 +59,7 @@
pmu { pmu {
compatible = "arm,cortex-a9-pmu"; compatible = "arm,cortex-a9-pmu";
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
}; };
ptm { ptm {
...@@ -69,7 +70,7 @@ ...@@ -69,7 +70,7 @@
cmt1: timer@e6138000 { cmt1: timer@e6138000 {
compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
reg = <0xe6138000 0x170>; reg = <0xe6138000 0x170>;
interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_CMT1>; clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&pd_c5>; power-domains = <&pd_c5>;
...@@ -89,14 +90,14 @@ ...@@ -89,14 +90,14 @@
<0xe6900020 1>, <0xe6900020 1>,
<0xe6900040 1>, <0xe6900040 1>,
<0xe6900060 1>; <0xe6900060 1>;
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>; power-domains = <&pd_a4s>;
}; };
...@@ -111,14 +112,14 @@ ...@@ -111,14 +112,14 @@
<0xe6900024 1>, <0xe6900024 1>,
<0xe6900044 1>, <0xe6900044 1>,
<0xe6900064 1>; <0xe6900064 1>;
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>; power-domains = <&pd_a4s>;
}; };
...@@ -133,14 +134,14 @@ ...@@ -133,14 +134,14 @@
<0xe6900028 1>, <0xe6900028 1>,
<0xe6900048 1>, <0xe6900048 1>,
<0xe6900068 1>; <0xe6900068 1>;
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>; power-domains = <&pd_a4s>;
}; };
...@@ -155,14 +156,14 @@ ...@@ -155,14 +156,14 @@
<0xe690002c 1>, <0xe690002c 1>,
<0xe690004c 1>, <0xe690004c 1>,
<0xe690006c 1>; <0xe690006c 1>;
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
0 149 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_INTCA>; clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
power-domains = <&pd_a4s>; power-domains = <&pd_a4s>;
}; };
...@@ -171,7 +172,7 @@ ...@@ -171,7 +172,7 @@
compatible = "renesas,gether-r8a7740"; compatible = "renesas,gether-r8a7740";
reg = <0xe9a00000 0x800>, reg = <0xe9a00000 0x800>,
<0xe9a01800 0x800>; <0xe9a01800 0x800>;
interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_GETHER>; clocks = <&mstp3_clks R8A7740_CLK_GETHER>;
power-domains = <&pd_a4s>; power-domains = <&pd_a4s>;
phy-mode = "mii"; phy-mode = "mii";
...@@ -185,10 +186,10 @@ ...@@ -185,10 +186,10 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
reg = <0xfff20000 0x425>; reg = <0xfff20000 0x425>;
interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
0 202 IRQ_TYPE_LEVEL_HIGH GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
0 203 IRQ_TYPE_LEVEL_HIGH GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
0 204 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_IIC0>; clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
power-domains = <&pd_a4r>; power-domains = <&pd_a4r>;
status = "disabled"; status = "disabled";
...@@ -199,10 +200,10 @@ ...@@ -199,10 +200,10 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic"; compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
reg = <0xe6c20000 0x425>; reg = <0xe6c20000 0x425>;
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
0 71 IRQ_TYPE_LEVEL_HIGH GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH
0 72 IRQ_TYPE_LEVEL_HIGH GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
0 73 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_IIC1>; clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
...@@ -211,9 +212,9 @@ ...@@ -211,9 +212,9 @@
scifa0: serial@e6c40000 { scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa"; compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c40000 0x100>; reg = <0xe6c40000 0x100>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -221,9 +222,9 @@ ...@@ -221,9 +222,9 @@
scifa1: serial@e6c50000 { scifa1: serial@e6c50000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa"; compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c50000 0x100>; reg = <0xe6c50000 0x100>;
interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -231,9 +232,9 @@ ...@@ -231,9 +232,9 @@
scifa2: serial@e6c60000 { scifa2: serial@e6c60000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa"; compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c60000 0x100>; reg = <0xe6c60000 0x100>;
interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -241,9 +242,9 @@ ...@@ -241,9 +242,9 @@
scifa3: serial@e6c70000 { scifa3: serial@e6c70000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa"; compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c70000 0x100>; reg = <0xe6c70000 0x100>;
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -251,9 +252,9 @@ ...@@ -251,9 +252,9 @@
scifa4: serial@e6c80000 { scifa4: serial@e6c80000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa"; compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6c80000 0x100>; reg = <0xe6c80000 0x100>;
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -261,9 +262,9 @@ ...@@ -261,9 +262,9 @@
scifa5: serial@e6cb0000 { scifa5: serial@e6cb0000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa"; compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6cb0000 0x100>; reg = <0xe6cb0000 0x100>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -271,9 +272,9 @@ ...@@ -271,9 +272,9 @@
scifa6: serial@e6cc0000 { scifa6: serial@e6cc0000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa"; compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6cc0000 0x100>; reg = <0xe6cc0000 0x100>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -281,9 +282,9 @@ ...@@ -281,9 +282,9 @@
scifa7: serial@e6cd0000 { scifa7: serial@e6cd0000 {
compatible = "renesas,scifa-r8a7740", "renesas,scifa"; compatible = "renesas,scifa-r8a7740", "renesas,scifa";
reg = <0xe6cd0000 0x100>; reg = <0xe6cd0000 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -291,9 +292,9 @@ ...@@ -291,9 +292,9 @@
scifb: serial@e6c30000 { scifb: serial@e6c30000 {
compatible = "renesas,scifb-r8a7740", "renesas,scifb"; compatible = "renesas,scifb-r8a7740", "renesas,scifb";
reg = <0xe6c30000 0x100>; reg = <0xe6c30000 0x100>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; clocks = <&mstp2_clks R8A7740_CLK_SCIFB>;
clock-names = "sci_ick"; clock-names = "fck";
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
}; };
...@@ -329,8 +330,8 @@ ...@@ -329,8 +330,8 @@
mmcif0: mmc@e6bd0000 { mmcif0: mmc@e6bd0000 {
compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif"; compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
reg = <0xe6bd0000 0x100>; reg = <0xe6bd0000 0x100>;
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH
0 57 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_MMC>; clocks = <&mstp3_clks R8A7740_CLK_MMC>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
status = "disabled"; status = "disabled";
...@@ -339,9 +340,9 @@ ...@@ -339,9 +340,9 @@
sdhi0: sd@e6850000 { sdhi0: sd@e6850000 {
compatible = "renesas,sdhi-r8a7740"; compatible = "renesas,sdhi-r8a7740";
reg = <0xe6850000 0x100>; reg = <0xe6850000 0x100>;
interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
0 118 IRQ_TYPE_LEVEL_HIGH GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
0 119 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
cap-sd-highspeed; cap-sd-highspeed;
...@@ -352,9 +353,9 @@ ...@@ -352,9 +353,9 @@
sdhi1: sd@e6860000 { sdhi1: sd@e6860000 {
compatible = "renesas,sdhi-r8a7740"; compatible = "renesas,sdhi-r8a7740";
reg = <0xe6860000 0x100>; reg = <0xe6860000 0x100>;
interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH
0 122 IRQ_TYPE_LEVEL_HIGH GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH
0 123 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
cap-sd-highspeed; cap-sd-highspeed;
...@@ -365,9 +366,9 @@ ...@@ -365,9 +366,9 @@
sdhi2: sd@e6870000 { sdhi2: sd@e6870000 {
compatible = "renesas,sdhi-r8a7740"; compatible = "renesas,sdhi-r8a7740";
reg = <0xe6870000 0x100>; reg = <0xe6870000 0x100>;
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
0 126 IRQ_TYPE_LEVEL_HIGH GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
0 127 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
power-domains = <&pd_a3sp>; power-domains = <&pd_a3sp>;
cap-sd-highspeed; cap-sd-highspeed;
...@@ -379,7 +380,7 @@ ...@@ -379,7 +380,7 @@
#sound-dai-cells = <1>; #sound-dai-cells = <1>;
compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
reg = <0xfe1f0000 0x400>; reg = <0xfe1f0000 0x400>;
interrupts = <0 9 0x4>; interrupts = <GIC_SPI 9 0x4>;
clocks = <&mstp3_clks R8A7740_CLK_FSI>; clocks = <&mstp3_clks R8A7740_CLK_FSI>;
power-domains = <&pd_a4mp>; power-domains = <&pd_a4mp>;
status = "disabled"; status = "disabled";
...@@ -388,9 +389,9 @@ ...@@ -388,9 +389,9 @@
tmu0: timer@fff80000 { tmu0: timer@fff80000 {
compatible = "renesas,tmu-r8a7740", "renesas,tmu"; compatible = "renesas,tmu-r8a7740", "renesas,tmu";
reg = <0xfff80000 0x2c>; reg = <0xfff80000 0x2c>;
interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
<0 199 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
<0 200 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_TMU0>; clocks = <&mstp1_clks R8A7740_CLK_TMU0>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&pd_a4r>; power-domains = <&pd_a4r>;
...@@ -403,9 +404,9 @@ ...@@ -403,9 +404,9 @@
tmu1: timer@fff90000 { tmu1: timer@fff90000 {
compatible = "renesas,tmu-r8a7740", "renesas,tmu"; compatible = "renesas,tmu-r8a7740", "renesas,tmu";
reg = <0xfff90000 0x2c>; reg = <0xfff90000 0x2c>;
interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<0 171 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<0 172 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7740_CLK_TMU1>; clocks = <&mstp1_clks R8A7740_CLK_TMU1>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&pd_a4r>; power-domains = <&pd_a4r>;
......
arch/arm/boot/dts/r8a7778-bockw.dts
浏览文件 @ fc2834a4
...@@ -126,11 +126,19 @@ ...@@ -126,11 +126,19 @@
}; };
&pfc { &pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif0_pins: serial0 { scif0_pins: serial0 {
renesas,groups = "scif0_data_a", "scif0_ctrl"; renesas,groups = "scif0_data_a", "scif0_ctrl";
renesas,function = "scif0"; renesas,function = "scif0";
}; };
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
};
mmc_pins: mmc { mmc_pins: mmc {
renesas,groups = "mmc_data8", "mmc_ctrl"; renesas,groups = "mmc_data8", "mmc_ctrl";
renesas,function = "mmc"; renesas,function = "mmc";
...@@ -217,3 +225,8 @@ ...@@ -217,3 +225,8 @@
status = "okay"; status = "okay";
}; };
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
arch/arm/boot/dts/r8a7778.dtsi
浏览文件 @ fc2834a4
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
/include/ "skeleton.dtsi" /include/ "skeleton.dtsi"
#include <dt-bindings/clock/r8a7778-clock.h> #include <dt-bindings/clock/r8a7778-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
/ { / {
...@@ -51,7 +52,7 @@ ...@@ -51,7 +52,7 @@
ether: ethernet@fde00000 { ether: ethernet@fde00000 {
compatible = "renesas,ether-r8a7778"; compatible = "renesas,ether-r8a7778";
reg = <0xfde00000 0x400>; reg = <0xfde00000 0x400>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7778_CLK_ETHER>; clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
phy-mode = "rmii"; phy-mode = "rmii";
...@@ -79,17 +80,17 @@ ...@@ -79,17 +80,17 @@
<0xfe780024 4>, <0xfe780024 4>,
<0xfe780044 4>, <0xfe780044 4>,
<0xfe780064 4>; <0xfe780064 4>;
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
0 28 IRQ_TYPE_LEVEL_HIGH GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
0 29 IRQ_TYPE_LEVEL_HIGH GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
0 30 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
sense-bitfield-width = <2>; sense-bitfield-width = <2>;
}; };
gpio0: gpio@ffc40000 { gpio0: gpio@ffc40000 {
compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
reg = <0xffc40000 0x2c>; reg = <0xffc40000 0x2c>;
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 0 32>; gpio-ranges = <&pfc 0 0 32>;
...@@ -100,7 +101,7 @@ ...@@ -100,7 +101,7 @@
gpio1: gpio@ffc41000 { gpio1: gpio@ffc41000 {
compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
reg = <0xffc41000 0x2c>; reg = <0xffc41000 0x2c>;
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 32 32>; gpio-ranges = <&pfc 0 32 32>;
...@@ -111,7 +112,7 @@ ...@@ -111,7 +112,7 @@
gpio2: gpio@ffc42000 { gpio2: gpio@ffc42000 {
compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
reg = <0xffc42000 0x2c>; reg = <0xffc42000 0x2c>;
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 64 32>; gpio-ranges = <&pfc 0 64 32>;
...@@ -122,7 +123,7 @@ ...@@ -122,7 +123,7 @@
gpio3: gpio@ffc43000 { gpio3: gpio@ffc43000 {
compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
reg = <0xffc43000 0x2c>; reg = <0xffc43000 0x2c>;
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 96 32>; gpio-ranges = <&pfc 0 96 32>;
...@@ -133,7 +134,7 @@ ...@@ -133,7 +134,7 @@
gpio4: gpio@ffc44000 { gpio4: gpio@ffc44000 {
compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
reg = <0xffc44000 0x2c>; reg = <0xffc44000 0x2c>;
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 128 27>; gpio-ranges = <&pfc 0 128 27>;
...@@ -151,7 +152,7 @@ ...@@ -151,7 +152,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,i2c-r8a7778"; compatible = "renesas,i2c-r8a7778";
reg = <0xffc70000 0x1000>; reg = <0xffc70000 0x1000>;
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C0>; clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -162,7 +163,7 @@ ...@@ -162,7 +163,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,i2c-r8a7778"; compatible = "renesas,i2c-r8a7778";
reg = <0xffc71000 0x1000>; reg = <0xffc71000 0x1000>;
interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C1>; clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -173,7 +174,7 @@ ...@@ -173,7 +174,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,i2c-r8a7778"; compatible = "renesas,i2c-r8a7778";
reg = <0xffc72000 0x1000>; reg = <0xffc72000 0x1000>;
interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C2>; clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -184,7 +185,7 @@ ...@@ -184,7 +185,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,i2c-r8a7778"; compatible = "renesas,i2c-r8a7778";
reg = <0xffc73000 0x1000>; reg = <0xffc73000 0x1000>;
interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C3>; clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -193,9 +194,9 @@ ...@@ -193,9 +194,9 @@
tmu0: timer@ffd80000 { tmu0: timer@ffd80000 {
compatible = "renesas,tmu-r8a7778", "renesas,tmu"; compatible = "renesas,tmu-r8a7778", "renesas,tmu";
reg = <0xffd80000 0x30>; reg = <0xffd80000 0x30>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<0 33 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<0 34 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU0>; clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -208,9 +209,9 @@ ...@@ -208,9 +209,9 @@
tmu1: timer@ffd81000 { tmu1: timer@ffd81000 {
compatible = "renesas,tmu-r8a7778", "renesas,tmu"; compatible = "renesas,tmu-r8a7778", "renesas,tmu";
reg = <0xffd81000 0x30>; reg = <0xffd81000 0x30>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<0 37 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<0 38 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU1>; clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -223,9 +224,9 @@ ...@@ -223,9 +224,9 @@
tmu2: timer@ffd82000 { tmu2: timer@ffd82000 {
compatible = "renesas,tmu-r8a7778", "renesas,tmu"; compatible = "renesas,tmu-r8a7778", "renesas,tmu";
reg = <0xffd82000 0x30>; reg = <0xffd82000 0x30>;
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<0 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<0 42 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_TMU2>; clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -285,72 +286,84 @@ ...@@ -285,72 +286,84 @@
}; };
rcar_sound,ssi { rcar_sound,ssi {
ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; }; ssi3: ssi@3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; }; ssi4: ssi@4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; ssi5: ssi@5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; ssi6: ssi@6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; ssi7: ssi@7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; ssi8: ssi@8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; }; ssi9: ssi@9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
}; };
}; };
scif0: serial@ffe40000 { scif0: serial@ffe40000 {
compatible = "renesas,scif-r8a7778", "renesas,scif"; compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe40000 0x100>; reg = <0xffe40000 0x100>;
interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF0>; clocks = <&mstp0_clks R8A7778_CLK_SCIF0>,
clock-names = "sci_ick"; <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif1: serial@ffe41000 { scif1: serial@ffe41000 {
compatible = "renesas,scif-r8a7778", "renesas,scif"; compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe41000 0x100>; reg = <0xffe41000 0x100>;
interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF1>; clocks = <&mstp0_clks R8A7778_CLK_SCIF1>,
clock-names = "sci_ick"; <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif2: serial@ffe42000 { scif2: serial@ffe42000 {
compatible = "renesas,scif-r8a7778", "renesas,scif"; compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe42000 0x100>; reg = <0xffe42000 0x100>;
interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF2>; clocks = <&mstp0_clks R8A7778_CLK_SCIF2>,
clock-names = "sci_ick"; <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif3: serial@ffe43000 { scif3: serial@ffe43000 {
compatible = "renesas,scif-r8a7778", "renesas,scif"; compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe43000 0x100>; reg = <0xffe43000 0x100>;
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF3>; clocks = <&mstp0_clks R8A7778_CLK_SCIF3>,
clock-names = "sci_ick"; <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif4: serial@ffe44000 { scif4: serial@ffe44000 {
compatible = "renesas,scif-r8a7778", "renesas,scif"; compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe44000 0x100>; reg = <0xffe44000 0x100>;
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF4>; clocks = <&mstp0_clks R8A7778_CLK_SCIF4>,
clock-names = "sci_ick"; <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif5: serial@ffe45000 { scif5: serial@ffe45000 {
compatible = "renesas,scif-r8a7778", "renesas,scif"; compatible = "renesas,scif-r8a7778", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe45000 0x100>; reg = <0xffe45000 0x100>;
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_SCIF5>; clocks = <&mstp0_clks R8A7778_CLK_SCIF5>,
clock-names = "sci_ick"; <&cpg_clocks R8A7778_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
...@@ -358,7 +371,7 @@ ...@@ -358,7 +371,7 @@
mmcif: mmc@ffe4e000 { mmcif: mmc@ffe4e000 {
compatible = "renesas,sh-mmcif"; compatible = "renesas,sh-mmcif";
reg = <0xffe4e000 0x100>; reg = <0xffe4e000 0x100>;
interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_MMC>; clocks = <&mstp3_clks R8A7778_CLK_MMC>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -367,7 +380,7 @@ ...@@ -367,7 +380,7 @@
sdhi0: sd@ffe4c000 { sdhi0: sd@ffe4c000 {
compatible = "renesas,sdhi-r8a7778"; compatible = "renesas,sdhi-r8a7778";
reg = <0xffe4c000 0x100>; reg = <0xffe4c000 0x100>;
interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI0>; clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -376,7 +389,7 @@ ...@@ -376,7 +389,7 @@
sdhi1: sd@ffe4d000 { sdhi1: sd@ffe4d000 {
compatible = "renesas,sdhi-r8a7778"; compatible = "renesas,sdhi-r8a7778";
reg = <0xffe4d000 0x100>; reg = <0xffe4d000 0x100>;
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI1>; clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -385,7 +398,7 @@ ...@@ -385,7 +398,7 @@
sdhi2: sd@ffe4f000 { sdhi2: sd@ffe4f000 {
compatible = "renesas,sdhi-r8a7778"; compatible = "renesas,sdhi-r8a7778";
reg = <0xffe4f000 0x100>; reg = <0xffe4f000 0x100>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7778_CLK_SDHI2>; clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -394,7 +407,7 @@ ...@@ -394,7 +407,7 @@
hspi0: spi@fffc7000 { hspi0: spi@fffc7000 {
compatible = "renesas,hspi-r8a7778", "renesas,hspi"; compatible = "renesas,hspi-r8a7778", "renesas,hspi";
reg = <0xfffc7000 0x18>; reg = <0xfffc7000 0x18>;
interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>; clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
#address-cells = <1>; #address-cells = <1>;
...@@ -405,7 +418,7 @@ ...@@ -405,7 +418,7 @@
hspi1: spi@fffc8000 { hspi1: spi@fffc8000 {
compatible = "renesas,hspi-r8a7778", "renesas,hspi"; compatible = "renesas,hspi-r8a7778", "renesas,hspi";
reg = <0xfffc8000 0x18>; reg = <0xfffc8000 0x18>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>; clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
#address-cells = <1>; #address-cells = <1>;
...@@ -416,7 +429,7 @@ ...@@ -416,7 +429,7 @@
hspi2: spi@fffc6000 { hspi2: spi@fffc6000 {
compatible = "renesas,hspi-r8a7778", "renesas,hspi"; compatible = "renesas,hspi-r8a7778", "renesas,hspi";
reg = <0xfffc6000 0x18>; reg = <0xfffc6000 0x18>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSPI>; clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
#address-cells = <1>; #address-cells = <1>;
...@@ -437,6 +450,15 @@ ...@@ -437,6 +450,15 @@
clock-output-names = "extal"; clock-output-names = "extal";
}; };
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
status = "disabled";
};
/* Special CPG clocks */ /* Special CPG clocks */
cpg_clocks: cpg_clocks@ffc80000 { cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7778-cpg-clocks"; compatible = "renesas,r8a7778-cpg-clocks";
......
arch/arm/boot/dts/r8a7779-marzen.dts
浏览文件 @ fc2834a4
...@@ -165,6 +165,9 @@ ...@@ -165,6 +165,9 @@
}; };
&pfc { &pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
du_pins: du { du_pins: du {
du0 { du0 {
renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0"; renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0";
...@@ -176,6 +179,11 @@ ...@@ -176,6 +179,11 @@
}; };
}; };
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk_b";
renesas,function = "scif_clk";
};
ethernet_pins: ethernet { ethernet_pins: ethernet {
intc { intc {
renesas,groups = "intc_irq1_b"; renesas,groups = "intc_irq1_b";
...@@ -222,6 +230,11 @@ ...@@ -222,6 +230,11 @@
status = "okay"; status = "okay";
}; };
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&sdhi0 { &sdhi0 {
pinctrl-0 = <&sdhi0_pins>; pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
......
arch/arm/boot/dts/r8a7779.dtsi
浏览文件 @ fc2834a4
...@@ -74,7 +74,7 @@ ...@@ -74,7 +74,7 @@
gpio0: gpio@ffc40000 { gpio0: gpio@ffc40000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
reg = <0xffc40000 0x2c>; reg = <0xffc40000 0x2c>;
interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 0 32>; gpio-ranges = <&pfc 0 0 32>;
...@@ -85,7 +85,7 @@ ...@@ -85,7 +85,7 @@
gpio1: gpio@ffc41000 { gpio1: gpio@ffc41000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
reg = <0xffc41000 0x2c>; reg = <0xffc41000 0x2c>;
interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 32 32>; gpio-ranges = <&pfc 0 32 32>;
...@@ -96,7 +96,7 @@ ...@@ -96,7 +96,7 @@
gpio2: gpio@ffc42000 { gpio2: gpio@ffc42000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
reg = <0xffc42000 0x2c>; reg = <0xffc42000 0x2c>;
interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 64 32>; gpio-ranges = <&pfc 0 64 32>;
...@@ -107,7 +107,7 @@ ...@@ -107,7 +107,7 @@
gpio3: gpio@ffc43000 { gpio3: gpio@ffc43000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
reg = <0xffc43000 0x2c>; reg = <0xffc43000 0x2c>;
interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 96 32>; gpio-ranges = <&pfc 0 96 32>;
...@@ -118,7 +118,7 @@ ...@@ -118,7 +118,7 @@
gpio4: gpio@ffc44000 { gpio4: gpio@ffc44000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
reg = <0xffc44000 0x2c>; reg = <0xffc44000 0x2c>;
interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 128 32>; gpio-ranges = <&pfc 0 128 32>;
...@@ -129,7 +129,7 @@ ...@@ -129,7 +129,7 @@
gpio5: gpio@ffc45000 { gpio5: gpio@ffc45000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
reg = <0xffc45000 0x2c>; reg = <0xffc45000 0x2c>;
interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 160 32>; gpio-ranges = <&pfc 0 160 32>;
...@@ -140,7 +140,7 @@ ...@@ -140,7 +140,7 @@
gpio6: gpio@ffc46000 { gpio6: gpio@ffc46000 {
compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
reg = <0xffc46000 0x2c>; reg = <0xffc46000 0x2c>;
interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-controller; gpio-controller;
gpio-ranges = <&pfc 0 192 9>; gpio-ranges = <&pfc 0 192 9>;
...@@ -159,10 +159,10 @@ ...@@ -159,10 +159,10 @@
<0xfe780044 4>, <0xfe780044 4>,
<0xfe780064 4>, <0xfe780064 4>,
<0xfe780000 4>; <0xfe780000 4>;
interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
0 28 IRQ_TYPE_LEVEL_HIGH GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
0 29 IRQ_TYPE_LEVEL_HIGH GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
0 30 IRQ_TYPE_LEVEL_HIGH>; GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
sense-bitfield-width = <2>; sense-bitfield-width = <2>;
}; };
...@@ -171,7 +171,7 @@ ...@@ -171,7 +171,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,i2c-r8a7779"; compatible = "renesas,i2c-r8a7779";
reg = <0xffc70000 0x1000>; reg = <0xffc70000 0x1000>;
interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C0>; clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -182,7 +182,7 @@ ...@@ -182,7 +182,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,i2c-r8a7779"; compatible = "renesas,i2c-r8a7779";
reg = <0xffc71000 0x1000>; reg = <0xffc71000 0x1000>;
interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C1>; clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -193,7 +193,7 @@ ...@@ -193,7 +193,7 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,i2c-r8a7779"; compatible = "renesas,i2c-r8a7779";
reg = <0xffc72000 0x1000>; reg = <0xffc72000 0x1000>;
interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C2>; clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -204,68 +204,80 @@ ...@@ -204,68 +204,80 @@
#size-cells = <0>; #size-cells = <0>;
compatible = "renesas,i2c-r8a7779"; compatible = "renesas,i2c-r8a7779";
reg = <0xffc73000 0x1000>; reg = <0xffc73000 0x1000>;
interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C3>; clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif0: serial@ffe40000 { scif0: serial@ffe40000 {
compatible = "renesas,scif-r8a7779", "renesas,scif"; compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe40000 0x100>; reg = <0xffe40000 0x100>;
interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF0>; clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
clock-names = "sci_ick"; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif1: serial@ffe41000 { scif1: serial@ffe41000 {
compatible = "renesas,scif-r8a7779", "renesas,scif"; compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe41000 0x100>; reg = <0xffe41000 0x100>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF1>; clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
clock-names = "sci_ick"; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif2: serial@ffe42000 { scif2: serial@ffe42000 {
compatible = "renesas,scif-r8a7779", "renesas,scif"; compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe42000 0x100>; reg = <0xffe42000 0x100>;
interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF2>; clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
clock-names = "sci_ick"; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif3: serial@ffe43000 { scif3: serial@ffe43000 {
compatible = "renesas,scif-r8a7779", "renesas,scif"; compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe43000 0x100>; reg = <0xffe43000 0x100>;
interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF3>; clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
clock-names = "sci_ick"; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif4: serial@ffe44000 { scif4: serial@ffe44000 {
compatible = "renesas,scif-r8a7779", "renesas,scif"; compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe44000 0x100>; reg = <0xffe44000 0x100>;
interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF4>; clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
clock-names = "sci_ick"; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
scif5: serial@ffe45000 { scif5: serial@ffe45000 {
compatible = "renesas,scif-r8a7779", "renesas,scif"; compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
"renesas,scif";
reg = <0xffe45000 0x100>; reg = <0xffe45000 0x100>;
interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_SCIF5>; clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
clock-names = "sci_ick"; <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
...@@ -283,9 +295,9 @@ ...@@ -283,9 +295,9 @@
tmu0: timer@ffd80000 { tmu0: timer@ffd80000 {
compatible = "renesas,tmu-r8a7779", "renesas,tmu"; compatible = "renesas,tmu-r8a7779", "renesas,tmu";
reg = <0xffd80000 0x30>; reg = <0xffd80000 0x30>;
interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<0 33 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<0 34 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -298,9 +310,9 @@ ...@@ -298,9 +310,9 @@
tmu1: timer@ffd81000 { tmu1: timer@ffd81000 {
compatible = "renesas,tmu-r8a7779", "renesas,tmu"; compatible = "renesas,tmu-r8a7779", "renesas,tmu";
reg = <0xffd81000 0x30>; reg = <0xffd81000 0x30>;
interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<0 37 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<0 38 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU1>; clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -313,9 +325,9 @@ ...@@ -313,9 +325,9 @@
tmu2: timer@ffd82000 { tmu2: timer@ffd82000 {
compatible = "renesas,tmu-r8a7779", "renesas,tmu"; compatible = "renesas,tmu-r8a7779", "renesas,tmu";
reg = <0xffd82000 0x30>; reg = <0xffd82000 0x30>;
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<0 41 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<0 42 IRQ_TYPE_LEVEL_HIGH>; <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_TMU2>; clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
clock-names = "fck"; clock-names = "fck";
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
...@@ -328,7 +340,7 @@ ...@@ -328,7 +340,7 @@
sata: sata@fc600000 { sata: sata@fc600000 {
compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
reg = <0xfc600000 0x2000>; reg = <0xfc600000 0x2000>;
interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_SATA>; clocks = <&mstp1_clks R8A7779_CLK_SATA>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
}; };
...@@ -336,7 +348,7 @@ ...@@ -336,7 +348,7 @@
sdhi0: sd@ffe4c000 { sdhi0: sd@ffe4c000 {
compatible = "renesas,sdhi-r8a7779"; compatible = "renesas,sdhi-r8a7779";
reg = <0xffe4c000 0x100>; reg = <0xffe4c000 0x100>;
interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -345,7 +357,7 @@ ...@@ -345,7 +357,7 @@
sdhi1: sd@ffe4d000 { sdhi1: sd@ffe4d000 {
compatible = "renesas,sdhi-r8a7779"; compatible = "renesas,sdhi-r8a7779";
reg = <0xffe4d000 0x100>; reg = <0xffe4d000 0x100>;
interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -354,7 +366,7 @@ ...@@ -354,7 +366,7 @@
sdhi2: sd@ffe4e000 { sdhi2: sd@ffe4e000 {
compatible = "renesas,sdhi-r8a7779"; compatible = "renesas,sdhi-r8a7779";
reg = <0xffe4e000 0x100>; reg = <0xffe4e000 0x100>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -363,7 +375,7 @@ ...@@ -363,7 +375,7 @@
sdhi3: sd@ffe4f000 { sdhi3: sd@ffe4f000 {
compatible = "renesas,sdhi-r8a7779"; compatible = "renesas,sdhi-r8a7779";
reg = <0xffe4f000 0x100>; reg = <0xffe4f000 0x100>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -372,7 +384,7 @@ ...@@ -372,7 +384,7 @@
hspi0: spi@fffc7000 { hspi0: spi@fffc7000 {
compatible = "renesas,hspi-r8a7779", "renesas,hspi"; compatible = "renesas,hspi-r8a7779", "renesas,hspi";
reg = <0xfffc7000 0x18>; reg = <0xfffc7000 0x18>;
interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
...@@ -383,7 +395,7 @@ ...@@ -383,7 +395,7 @@
hspi1: spi@fffc8000 { hspi1: spi@fffc8000 {
compatible = "renesas,hspi-r8a7779", "renesas,hspi"; compatible = "renesas,hspi-r8a7779", "renesas,hspi";
reg = <0xfffc8000 0x18>; reg = <0xfffc8000 0x18>;
interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
...@@ -394,7 +406,7 @@ ...@@ -394,7 +406,7 @@
hspi2: spi@fffc6000 { hspi2: spi@fffc6000 {
compatible = "renesas,hspi-r8a7779", "renesas,hspi"; compatible = "renesas,hspi-r8a7779", "renesas,hspi";
reg = <0xfffc6000 0x18>; reg = <0xfffc6000 0x18>;
interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&mstp0_clks R8A7779_CLK_HSPI>; clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
...@@ -405,7 +417,7 @@ ...@@ -405,7 +417,7 @@
du: display@fff80000 { du: display@fff80000 {
compatible = "renesas,du-r8a7779"; compatible = "renesas,du-r8a7779";
reg = <0 0xfff80000 0 0x40000>; reg = <0 0xfff80000 0 0x40000>;
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_DU>; clocks = <&mstp1_clks R8A7779_CLK_DU>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
...@@ -441,6 +453,15 @@ ...@@ -441,6 +453,15 @@
clock-output-names = "extal"; clock-output-names = "extal";
}; };
/* External SCIF clock */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
status = "disabled";
};
/* Special CPG clocks */ /* Special CPG clocks */
cpg_clocks: clocks@ffc80000 { cpg_clocks: clocks@ffc80000 {
compatible = "renesas,r8a7779-cpg-clocks"; compatible = "renesas,r8a7779-cpg-clocks";
......
arch/arm/boot/dts/r8a7790-lager.dts
浏览文件 @ fc2834a4
...@@ -291,6 +291,9 @@ ...@@ -291,6 +291,9 @@
}; };
&pfc { &pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
du_pins: du { du_pins: du {
renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0";
renesas,function = "du"; renesas,function = "du";
...@@ -301,6 +304,11 @@ ...@@ -301,6 +304,11 @@
renesas,function = "scif0"; renesas,function = "scif0";
}; };
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
};
ether_pins: ether { ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth"; renesas,function = "eth";
...@@ -485,6 +493,11 @@ ...@@ -485,6 +493,11 @@
status = "okay"; status = "okay";
}; };
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&msiof1 { &msiof1 {
pinctrl-0 = <&msiof1_pins>; pinctrl-0 = <&msiof1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
......
arch/arm/boot/dts/r8a7790.dtsi
浏览文件 @ fc2834a4
此差异已折叠。
arch/arm/boot/dts/r8a7791-koelsch.dts
浏览文件 @ fc2834a4
...@@ -320,6 +320,9 @@ ...@@ -320,6 +320,9 @@
}; };
&pfc { &pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
i2c2_pins: i2c2 { i2c2_pins: i2c2 {
renesas,groups = "i2c2"; renesas,groups = "i2c2";
renesas,function = "i2c2"; renesas,function = "i2c2";
...@@ -340,6 +343,11 @@ ...@@ -340,6 +343,11 @@
renesas,function = "scif1"; renesas,function = "scif1";
}; };
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
};
ether_pins: ether { ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth"; renesas,function = "eth";
...@@ -440,6 +448,11 @@ ...@@ -440,6 +448,11 @@
status = "okay"; status = "okay";
}; };
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&sdhi0 { &sdhi0 {
pinctrl-0 = <&sdhi0_pins>; pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
......
arch/arm/boot/dts/r8a7791-porter.dts
浏览文件 @ fc2834a4
...@@ -8,6 +8,17 @@ ...@@ -8,6 +8,17 @@
* kind, whether express or implied. * kind, whether express or implied.
*/ */
/*
* SSI-AK4642
*
* SW3: 1: AK4642
* 3: ADV7511
*
* This command is required before playback/capture:
*
* amixer set "LINEOUT Mixer DACL" on
*/
/dts-v1/; /dts-v1/;
#include "r8a7791.dtsi" #include "r8a7791.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
...@@ -78,6 +89,53 @@ ...@@ -78,6 +89,53 @@
states = <3300000 1 states = <3300000 1
1800000 0>; 1800000 0>;
}; };
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
x3_clk: x3-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
x16_clk: x16-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
x14_clk: x14-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-output-names = "audio_clock";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&soundcodec>;
simple-audio-card,frame-master = <&soundcodec>;
simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
soundcodec: simple-audio-card,codec {
sound-dai = <&ak4642>;
clocks = <&x14_clk>;
};
};
}; };
&extal_clk { &extal_clk {
...@@ -85,11 +143,19 @@ ...@@ -85,11 +143,19 @@
}; };
&pfc { &pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif0_pins: serial0 { scif0_pins: serial0 {
renesas,groups = "scif0_data_d"; renesas,groups = "scif0_data_d";
renesas,function = "scif0"; renesas,function = "scif0";
}; };
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
};
ether_pins: ether { ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth"; renesas,function = "eth";
...@@ -139,6 +205,21 @@ ...@@ -139,6 +205,21 @@
renesas,groups = "can0_data"; renesas,groups = "can0_data";
renesas,function = "can0"; renesas,function = "can0";
}; };
du_pins: du {
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
renesas,function = "du";
};
ssi_pins: sound {
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
renesas,function = "ssi";
};
audio_clk_pins: audio_clk {
renesas,groups = "audio_clk_a";
renesas,function = "audio_clk";
};
}; };
&scif0 { &scif0 {
...@@ -148,6 +229,11 @@ ...@@ -148,6 +229,11 @@
status = "okay"; status = "okay";
}; };
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&ether { &ether {
pinctrl-0 = <&ether_pins &phy1_pins>; pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -229,6 +315,12 @@ ...@@ -229,6 +315,12 @@
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
ak4642: codec@12 {
compatible = "asahi-kasei,ak4642";
#sound-dai-cells = <0>;
reg = <0x12>;
};
composite-in@20 { composite-in@20 {
compatible = "adi,adv7180"; compatible = "adi,adv7180";
reg = <0x20>; reg = <0x20>;
...@@ -241,6 +333,38 @@ ...@@ -241,6 +333,38 @@
}; };
}; };
}; };
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
}; };
&sata0 { &sata0 {
...@@ -304,3 +428,44 @@ ...@@ -304,3 +428,44 @@
status = "okay"; status = "okay";
}; };
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7791_CLK_DU0>,
<&mstp7_clks R8A7791_CLK_DU1>,
<&mstp7_clks R8A7791_CLK_LVDS0>,
<&x3_clk>, <&x16_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";
ports {
port@1 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
&rcar_sound {
pinctrl-0 = <&ssi_pins &audio_clk_pins>;
pinctrl-names = "default";
status = "okay";
/* Single DAI */
#sound-dai-cells = <0>;
rcar_sound,dai {
dai0 {
playback = <&ssi0>;
capture = <&ssi1>;
};
};
};
&ssi1 {
shared-pin;
};
arch/arm/boot/dts/r8a7791.dtsi
浏览文件 @ fc2834a4
此差异已折叠。
arch/arm/boot/dts/r8a7793-gose.dts
浏览文件 @ fc2834a4
...@@ -8,6 +8,34 @@ ...@@ -8,6 +8,34 @@
* kind, whether express or implied. * kind, whether express or implied.
*/ */
/*
* SSI-AK4643
*
* SW1: 1: AK4643
* 2: CN22
* 3: ADV7511
*
* This command is required when Playback/Capture
*
* amixer set "LINEOUT Mixer DACL" on
* amixer set "DVC Out" 100%
* amixer set "DVC In" 100%
*
* You can use Mute
*
* amixer set "DVC Out Mute" on
* amixer set "DVC In Mute" on
*
* You can use Volume Ramp
*
* amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
* amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
* amixer set "DVC Out Ramp" on
* aplay xxx.wav &
* amixer set "DVC Out" 80% // Volume Down
* amixer set "DVC Out" 100% // Volume Up
*/
/dts-v1/; /dts-v1/;
#include "r8a7793.dtsi" #include "r8a7793.dtsi"
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
...@@ -31,6 +59,176 @@ ...@@ -31,6 +59,176 @@
device_type = "memory"; device_type = "memory";
reg = <0 0x40000000 0 0x40000000>; reg = <0 0x40000000 0 0x40000000>;
}; };
gpio-keys {
compatible = "gpio-keys";
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
label = "SW2-1";
gpio-key,wakeup;
debounce-interval = <20>;
};
key-2 {
gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_2>;
label = "SW2-2";
gpio-key,wakeup;
debounce-interval = <20>;
};
key-3 {
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
label = "SW2-3";
gpio-key,wakeup;
debounce-interval = <20>;
};
key-4 {
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_4>;
label = "SW2-4";
gpio-key,wakeup;
debounce-interval = <20>;
};
key-a {
gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_A>;
label = "SW30";
gpio-key,wakeup;
debounce-interval = <20>;
};
key-b {
gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_B>;
label = "SW31";
gpio-key,wakeup;
debounce-interval = <20>;
};
key-c {
gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
linux,code = <KEY_C>;
label = "SW32";
gpio-key,wakeup;
debounce-interval = <20>;
};
key-d {
gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
linux,code = <KEY_D>;
label = "SW33";
gpio-key,wakeup;
debounce-interval = <20>;
};
key-e {
gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
linux,code = <KEY_E>;
label = "SW34";
gpio-key,wakeup;
debounce-interval = <20>;
};
key-f {
gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
linux,code = <KEY_F>;
label = "SW35";
gpio-key,wakeup;
debounce-interval = <20>;
};
key-g {
gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_G>;
label = "SW36";
gpio-key,wakeup;
debounce-interval = <20>;
};
};
leds {
compatible = "gpio-leds";
led6 {
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
label = "LED6";
};
led7 {
gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
label = "LED7";
};
led8 {
gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
label = "LED8";
};
};
audio_clock: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <11289600>;
clock-output-names = "audio_clock";
};
rsnd_ak4643: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "left_j";
simple-audio-card,bitclock-master = <&sndcodec>;
simple-audio-card,frame-master = <&sndcodec>;
sndcpu: simple-audio-card,cpu {
sound-dai = <&rcar_sound>;
};
sndcodec: simple-audio-card,codec {
sound-dai = <&ak4643>;
clocks = <&audio_clock>;
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
x13_clk: x13-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&du {
pinctrl-0 = <&du_pins>;
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7793_CLK_DU0>,
<&mstp7_clks R8A7793_CLK_DU1>,
<&mstp7_clks R8A7793_CLK_LVDS0>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
};
port@1 {
lvds_connector: endpoint {
};
};
};
}; };
&extal_clk { &extal_clk {
...@@ -38,6 +236,19 @@ ...@@ -38,6 +236,19 @@
}; };
&pfc { &pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
i2c2_pins: i2c2 {
renesas,groups = "i2c2";
renesas,function = "i2c2";
};
du_pins: du {
renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
renesas,function = "du";
};
scif0_pins: serial0 { scif0_pins: serial0 {
renesas,groups = "scif0_data_d"; renesas,groups = "scif0_data_d";
renesas,function = "scif0"; renesas,function = "scif0";
...@@ -48,6 +259,11 @@ ...@@ -48,6 +259,11 @@
renesas,function = "scif1"; renesas,function = "scif1";
}; };
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
};
ether_pins: ether { ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth"; renesas,function = "eth";
...@@ -62,6 +278,16 @@ ...@@ -62,6 +278,16 @@
renesas,groups = "qspi_ctrl", "qspi_data4"; renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi"; renesas,function = "qspi";
}; };
sound_pins: sound {
renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
renesas,function = "ssi";
};
sound_clk_pins: sound_clk {
renesas,groups = "audio_clk_a";
renesas,function = "audio_clk";
};
}; };
&ether { &ether {
...@@ -98,6 +324,11 @@ ...@@ -98,6 +324,11 @@
status = "okay"; status = "okay";
}; };
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&qspi { &qspi {
pinctrl-0 = <&qspi_pins>; pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -136,3 +367,76 @@ ...@@ -136,3 +367,76 @@
}; };
}; };
}; };
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <100000>;
ak4643: codec@12 {
compatible = "asahi-kasei,ak4643";
#sound-dai-cells = <0>;
reg = <0x12>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
eeprom@50 {
compatible = "renesas,r1ex24002", "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
};
&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;
pinctrl-names = "default";
/* Single DAI */
#sound-dai-cells = <0>;
status = "okay";
rcar_sound,dai {
dai0 {
playback = <&ssi0 &src2 &dvc0>;
capture = <&ssi1 &src3 &dvc1>;
};
};
};
&ssi1 {
shared-pin;
};
arch/arm/boot/dts/r8a7793.dtsi
浏览文件 @ fc2834a4
此差异已折叠。
arch/arm/boot/dts/r8a7794-alt.dts
浏览文件 @ fc2834a4
...@@ -103,6 +103,9 @@ ...@@ -103,6 +103,9 @@
}; };
&pfc { &pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
du_pins: du { du_pins: du {
renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0"; renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
renesas,function = "du"; renesas,function = "du";
...@@ -113,6 +116,11 @@ ...@@ -113,6 +116,11 @@
renesas,function = "scif2"; renesas,function = "scif2";
}; };
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
};
ether_pins: ether { ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth"; renesas,function = "eth";
...@@ -138,6 +146,13 @@ ...@@ -138,6 +146,13 @@
status = "okay"; status = "okay";
}; };
&pfc {
qspi_pins: spi0 {
renesas,groups = "qspi_ctrl", "qspi_data4";
renesas,function = "qspi";
};
};
&ether { &ether {
pinctrl-0 = <&ether_pins &phy1_pins>; pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -197,3 +212,47 @@ ...@@ -197,3 +212,47 @@
status = "okay"; status = "okay";
}; };
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&qspi {
pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fl512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <30000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
spi-cpol;
spi-cpha;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "loader";
reg = <0x00000000 0x00040000>;
read-only;
};
partition@40000 {
label = "system";
reg = <0x00040000 0x00040000>;
read-only;
};
partition@80000 {
label = "user";
reg = <0x00080000 0x03f80000>;
};
};
};
};
arch/arm/boot/dts/r8a7794-silk.dts
浏览文件 @ fc2834a4
...@@ -64,6 +64,61 @@ ...@@ -64,6 +64,61 @@
states = <3300000 1 states = <3300000 1
1800000 0>; 1800000 0>;
}; };
vga-encoder {
compatible = "adi,adv7123";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7123_in: endpoint {
remote-endpoint = <&du_out_rgb1>;
};
};
port@1 {
reg = <1>;
adv7123_out: endpoint {
remote-endpoint = <&vga_in>;
};
};
};
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
vga {
compatible = "vga-connector";
port {
vga_in: endpoint {
remote-endpoint = <&adv7123_out>;
};
};
};
x2_clk: x2-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
x3_clk: x3-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <74250000>;
};
}; };
&extal_clk { &extal_clk {
...@@ -71,11 +126,19 @@ ...@@ -71,11 +126,19 @@
}; };
&pfc { &pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
scif2_pins: serial2 { scif2_pins: serial2 {
renesas,groups = "scif2_data"; renesas,groups = "scif2_data";
renesas,function = "scif2"; renesas,function = "scif2";
}; };
scif_clk_pins: scif_clk {
renesas,groups = "scif_clk";
renesas,function = "scif_clk";
};
ether_pins: ether { ether_pins: ether {
renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
renesas,function = "eth"; renesas,function = "eth";
...@@ -129,6 +192,11 @@ ...@@ -129,6 +192,11 @@
status = "okay"; status = "okay";
}; };
&scif_clk {
clock-frequency = <14745600>;
status = "okay";
};
&ether { &ether {
pinctrl-0 = <&ether_pins &phy1_pins>; pinctrl-0 = <&ether_pins &phy1_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
...@@ -164,6 +232,38 @@ ...@@ -164,6 +232,38 @@
}; };
}; };
}; };
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio5>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&du_out_rgb0>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
}; };
&mmcif0 { &mmcif0 {
...@@ -258,3 +358,25 @@ ...@@ -258,3 +358,25 @@
&usbphy { &usbphy {
status = "okay"; status = "okay";
}; };
&du {
status = "okay";
clocks = <&mstp7_clks R8A7794_CLK_DU0>,
<&mstp7_clks R8A7794_CLK_DU0>,
<&x2_clk>, <&x3_clk>;
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
ports {
port@0 {
endpoint {
remote-endpoint = <&adv7511_in>;
};
};
port@1 {
endpoint {
remote-endpoint = <&adv7123_in>;
};
};
};
};
arch/arm/boot/dts/r8a7794.dtsi
浏览文件 @ fc2834a4
此差异已折叠。
arch/arm/boot/dts/sh73a0.dtsi
浏览文件 @ fc2834a4
此差异已折叠。
include/dt-bindings/clock/r8a7793-clock.h
浏览文件 @ fc2834a4
...@@ -145,6 +145,8 @@ ...@@ -145,6 +145,8 @@
#define R8A7793_CLK_SCU_ALL 17 #define R8A7793_CLK_SCU_ALL 17
#define R8A7793_CLK_SCU_DVC1 18 #define R8A7793_CLK_SCU_DVC1 18
#define R8A7793_CLK_SCU_DVC0 19 #define R8A7793_CLK_SCU_DVC0 19
#define R8A7793_CLK_SCU_CTU1_MIX1 20
#define R8A7793_CLK_SCU_CTU0_MIX0 21
#define R8A7793_CLK_SCU_SRC9 22 #define R8A7793_CLK_SCU_SRC9 22
#define R8A7793_CLK_SCU_SRC8 23 #define R8A7793_CLK_SCU_SRC8 23
#define R8A7793_CLK_SCU_SRC7 24 #define R8A7793_CLK_SCU_SRC7 24
......
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