提交 fba79e32 编写于 作者: T Tomasz Figa 提交者: Kukjin Kim

clk: exynos4: Export mout_core clock of Exynos4210

This patch enables clock lookup registration for mout_core clock used in
Exynos4210 cpufreq driver.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
上级 a8b5a39e
...@@ -311,7 +311,8 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { ...@@ -311,7 +311,8 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4), MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4),
MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4), MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4),
MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"), MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
MUX(none, "mout_core", mout_core_p4210, SRC_CPU, 16, 1), MUX_A(mout_core, "mout_core", mout_core_p4210,
SRC_CPU, 16, 1, "mout_core"),
MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
SRC_TOP0, 8, 1, "sclk_vpll"), SRC_TOP0, 8, 1, "sclk_vpll"),
MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),
......
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