PCI: xilinx-nwl: Enable all MSI interrupts using MSI mask

The current mask enables and allows only one MSI interrupt on each MSI
line.  Enable all MSI interrupts, which will also support Endpoints with
multi-MSI support.
Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

drivers/pci/host/pcie-xilinx-nwl.c

@@ -120,8 +120,8 @@
 					MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
 
 /* MSI interrupt status mask bits */
-#define MSGF_MSI_SR_LO_MASK		BIT(0)
-#define MSGF_MSI_SR_HI_MASK		BIT(0)
+#define MSGF_MSI_SR_LO_MASK		GENMASK(31, 0)
+#define MSGF_MSI_SR_HI_MASK		GENMASK(31, 0)
 
 #define MSII_PRESENT			BIT(0)
 #define MSII_ENABLE			BIT(0)