RDMA/hns: modify v2 gid index num to 32

driver inclusion
category: bugfix
bugzilla: NA
CVE: NA

According to RoCEE UM, RoCEE supports up to 256 gid index num globally.
As for each pf, 32 is an available value.

Feature or Bugfix: Bugfix
Signed-off-by: NWeihang Li <liweihang@hisilicon.com>
Reviewed-by: Noulijun <oulijun@huawei.com>
Reviewed-by: NYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

@@ -1873,7 +1873,7 @@ static int hns_roce_v2_profile(struct hns_roce_dev *hr_dev)
 				  HNS_ROCE_CAP_FLAG_RECORD_DB |
 				  HNS_ROCE_CAP_FLAG_SQ_RECORD_DB;
 	caps->pkey_table_len[0] = 1;
-	caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM(d);
+	caps->gid_table_len[0] = HNS_ROCE_V2_GID_INDEX_NUM;
 	caps->ceqe_depth	= HNS_ROCE_V2_COMP_EQE_NUM;
 	caps->aeqe_depth	= HNS_ROCE_V2_ASYNC_EQE_NUM;
 	caps->local_ca_ack_delay = 0;

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

@@ -122,7 +122,7 @@
 #define HNS_ROCE_IDX_HOP_NUM			1
 #define HNS_ROCE_MEM_PAGE_SUPPORT_8K		2
 
-#define HNS_ROCE_V2_GID_INDEX_NUM(d)		(d ? (8) : (256))
+#define HNS_ROCE_V2_GID_INDEX_NUM		32
 
 #define HNS_ROCE_V2_TABLE_CHUNK_SIZE		(1 << 18)