drm/amd/display: single PSR display not allow CSTATE sw w/a

Description:
HW issue when all the pipes are off, DCE_allow_cstate is 0.
New sequence : blank OTG only instead of previous OTG_master_en=0)
Signed-off-by: NCharlene Liu <charlene.liu@amd.com>
Reviewed-by: NAnthony Koo <Anthony.Koo@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link.c

@@ -1548,6 +1548,12 @@ bool dc_link_setup_psr(struct dc_link *link,
 
 		psr_context->psr_level.u32all = 0;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
+		/*skip power down the single pipe since it blocks the cstate*/
+		if (ASIC_REV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev))
+			psr_context->psr_level.bits.SKIP_SINGLE_OTG_DISABLE = true;
+#endif
+
 		/* SMU will perform additional powerdown sequence.
 		 * For unsupported ASICs, set psr_level flag to skip PSR
 		 *  static screen notification to SMU.

drivers/gpu/drm/amd/display/dc/dc_types.h

@@ -539,7 +539,8 @@ union dmcu_psr_level {
 		unsigned int SKIP_SMU_NOTIFICATION:1;
 		unsigned int SKIP_AUTO_STATE_ADVANCE:1;
 		unsigned int DISABLE_PSR_ENTRY_ABORT:1;
-		unsigned int RESERVED:23;
+		unsigned int SKIP_SINGLE_OTG_DISABLE:1;
+		unsigned int RESERVED:22;
 	} bits;
 	unsigned int u32all;
 };