ASoC: Optimise clock management for WM8915 Speyside
Dynamically enable and disable the FLL on the WM8915, configuring the system clock to 256fs for 48kHz when the device is active but reverting to using the input 32.768kHz clock directly at other times to support features such as jack detection with minimal power consumption. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: NJassi Brar <jassisinghbrar@gmail.com> Acked-by: NLiam Girdwood <lrg@ti.com>
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