mfd: db8500-prcmu: Update stored DSI PLL divider value

Previously the DSI PLL divider rate was initialised statically and
assumed to be 1. Before the common clock framework was enabled for
ux500, a call to clk_set_rate() would always update the HW registers
no matter what the current setting was.

This patch makes sure the actual hw settings and the sw assumed
settings are matched.
Signed-off-by: NPaer-Olof Haakansson <par-olof.hakansson@stericsson.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NSamuel Ortiz <sameo@linux.intel.com>

drivers/mfd/db8500-prcmu.c

@@ -1613,6 +1613,8 @@ static unsigned long dsiclk_rate(u8 n)
 
 	if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
 		divsel = dsiclk[n].divsel;
+	else
+		dsiclk[n].divsel = divsel;
 
 	switch (divsel) {
 	case PRCM_DSI_PLLOUT_SEL_PHI_4: