spi: spi_sh_msiof: Fixed data sampling on the correct edge
The spi_sh_msiof.c driver presently misconfigures REDG and TEDG. TEDG==0 outputs data at the **rising edge** of the clock and REDG==0 samples data at the **falling edge** of the clock. Therefore for SPI, TEDG must be equal to REDG, otherwise the last byte received is not sampled in SPI mode 3. This brings the driver in line with the SH7723 HW Reference Manual settings documented in Figures 20.20 and 20.21 ("SPI Clock and data timing"). Signed-off-by: NMarkus Pietrek <Markus.Pietrek@emtrion.de> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
Showing
想要评论请 注册 或 登录