drm/nouveau/pm: several fixes for nvc0 memory timings

This patch fixes two small issues in timing generation as spotted on
several NVCx cards.

In addition, the header of the file is updated to also contain (some of)
the current developers of this code.
Signed-off-by: NRoy Spliet <r.spliet@student.tudelft.nl>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nouveau_mem.c

@@ -26,7 +26,8 @@
  * DEALINGS IN THE SOFTWARE.
  *
  * Authors:
- *    Keith Whitwell <keith@tungstengraphics.com>
+ *    Ben Skeggs <bskeggs@redhat.com>
+ *    Roy Spliet <r.spliet@student.tudelft.nl>
  */
 
 
@@ -613,13 +614,13 @@ nvc0_mem_timing_calc(struct drm_device *dev, u32 freq,
 	t->reg[1] = (boot->reg[1] & 0xff000000) |
 		    (e->tRCDWR & 0x0f) << 20 |
 		    (e->tRCDRD & 0x0f) << 14 |
-		    (e->tCWL << 7) |
+		    (t->tCWL << 7) |
 		    (e->tCL & 0x0f);
 
 	t->reg[2] = (boot->reg[2] & 0xff0000ff) |
 		    e->tWR << 16 | e->tWTR << 8;
 
-	t->reg[3] = (e->tUNK_20 & 0xf) << 9 |
+	t->reg[3] = (e->tUNK_20 & 0x1f) << 9 |
 		    (e->tUNK_21 & 0xf) << 5 |
 		    (e->tUNK_13 & 0x1f);
 
@@ -930,6 +931,8 @@ nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t)
 	t->tCWL = 0;
 	if (dev_priv->card_type < NV_C0) {
 		t->tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1;
+	} else if (dev_priv->card_type <= NV_D0) {
+		t->tCWL = ((nv_rd32(dev, 0x10f294) & 0x00000f80) >> 7);
 	}
 
 	t->mr[0] = nv_rd32(dev, mr_base);