drm/nouveau/device: switch to dev_printk macros

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

@@ -414,14 +414,11 @@ nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		}
 
 		if (ret) {
-			nv_error(device, "unknown chipset, 0x%08x\n", boot0);
+			nvdev_error(device, "unknown chipset (%08x)\n", boot0);
 			return ret;
 		}
 
-		nv_info(device, "BOOT0  : 0x%08x\n", boot0);
-		nv_info(device, "Chipset: %s (NV%02X)\n",
-			device->cname, device->chipset);
-		nv_info(device, "Family : NV%02X\n", device->card_type);
+		nvdev_info(device, "NVIDIA %s (%08x)\n", device->cname, boot0);
 
 		/* determine frequency of timing crystal */
 		if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
@@ -436,8 +433,6 @@ nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		case 0x00400000: device->crystal = 27000; break;
 		case 0x00400040: device->crystal = 25000; break;
 		}
-
-		nv_debug(device, "crystal freq: %dKHz\n", device->crystal);
 	} else
 	if ( (args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY)) {
 		device->cname = "NULL";
@@ -447,7 +442,7 @@ nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_MMIO) && !device->pri) {
 		device->pri = ioremap(mmio_base, mmio_size);
 		if (!device->pri) {
-			nv_error(device, "unable to map device registers\n");
+			nvdev_error(device, "unable to map PRI\n");
 			return -ENOMEM;
 		}
 	}

drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c

@@ -350,7 +350,6 @@ gf100_identify(struct nvkm_device *device)
 		device->oclass[NVDEV_ENGINE_PM     ] = gf117_pm_oclass;
 		break;
 	default:
-		nv_fatal(device, "unknown Fermi chipset\n");
 		return -EINVAL;
 	}
 

drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c

@@ -318,7 +318,6 @@ gk104_identify(struct nvkm_device *device)
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 		break;
 	default:
-		nv_fatal(device, "unknown Kepler chipset\n");
 		return -EINVAL;
 	}
 

drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

@@ -202,7 +202,6 @@ gm100_identify(struct nvkm_device *device)
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
 		break;
 	default:
-		nv_fatal(device, "unknown Maxwell chipset\n");
 		return -EINVAL;
 	}
 

drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c

@@ -81,7 +81,6 @@ nv04_identify(struct nvkm_device *device)
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	default:
-		nv_fatal(device, "unknown RIVA chipset\n");
 		return -EINVAL;
 	}
 

drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c

@@ -196,7 +196,6 @@ nv10_identify(struct nvkm_device *device)
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	default:
-		nv_fatal(device, "unknown Celsius chipset\n");
 		return -EINVAL;
 	}
 

drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c

@@ -123,7 +123,6 @@ nv20_identify(struct nvkm_device *device)
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	default:
-		nv_fatal(device, "unknown Kelvin chipset\n");
 		return -EINVAL;
 	}
 

drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c

@@ -145,7 +145,6 @@ nv30_identify(struct nvkm_device *device)
 		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
 		break;
 	default:
-		nv_fatal(device, "unknown Rankine chipset\n");
 		return -EINVAL;
 	}
 

drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c

@@ -419,7 +419,6 @@ nv40_identify(struct nvkm_device *device)
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv40_pm_oclass;
 		break;
 	default:
-		nv_fatal(device, "unknown Curie chipset\n");
 		return -EINVAL;
 	}
 

drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c

@@ -470,7 +470,6 @@ nv50_identify(struct nvkm_device *device)
 		device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
 		break;
 	default:
-		nv_fatal(device, "unknown Tesla chipset\n");
 		return -EINVAL;
 	}