提交 e0ee1a75 编写于 作者: V Victor(Weiguo) Pan 提交者: Thierry Reding

pwm: tegra: Allow 100 % duty cycle

To get 100 % duty cycle (always high), pulse width needs to be set to
256.
Signed-off-by: NVictor(Weiguo) Pan <wpan@nvidia.com>
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NThierry Reding <thierry.reding@gmail.com>
上级 5dfbd2bd
......@@ -77,7 +77,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
* nearest integer during division.
*/
c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2;
do_div(c, period_ns);
val = (u32)c << PWM_DUTY_SHIFT;
......
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