提交 d70ccd4a 编写于 作者: Y Yongqiang Sun 提交者: Alex Deucher

drm/amd/display: Keep blank until set visibility to true after mode switch

Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 e75504b1
......@@ -1609,12 +1609,10 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (!pipe_ctx->surface || pipe_ctx->top_pipe)
continue;
if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
core_dc->hwss.pipe_control_lock(
core_dc,
pipe_ctx,
true);
}
core_dc->hwss.pipe_control_lock(
core_dc,
pipe_ctx,
true);
}
if (update_type == UPDATE_TYPE_FULL)
break;
......@@ -1697,12 +1695,11 @@ void dc_update_surfaces_and_stream(struct dc *dc,
if (!pipe_ctx->surface || pipe_ctx->top_pipe)
continue;
if (!pipe_ctx->tg->funcs->is_blanked(pipe_ctx->tg)) {
core_dc->hwss.pipe_control_lock(
core_dc,
pipe_ctx,
false);
}
core_dc->hwss.pipe_control_lock(
core_dc,
pipe_ctx,
false);
break;
}
}
......
......@@ -52,6 +52,10 @@ void dce_pipe_control_lock(struct core_dc *dc,
uint32_t dcp_grph, scl, blnd, update_lock_mode, val;
struct dce_hwseq *hws = dc->hwseq;
/* Not lock pipe when blank */
if (lock && pipe->tg->funcs->is_blanked(pipe->tg))
return;
val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->pipe_idx],
BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
BLND_SCL_V_UPDATE_LOCK, &scl,
......
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