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raspberrypi-kernel
提交 d16067b2 编写于 作者: B Ben Dooks
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ARM: Merge for-2635/s5p6440-clock 

Merge branch 'for-2635/s5p6440-clock' into for-linus/samsung2
上级 2abbfb26 b3b84d65
隐藏空白更改
内联 并排
Showing with 249 addition and 101 deletion
arch/arm/mach-s5p6440/clock.c
浏览文件 @ d16067b2
...@@ -134,24 +134,6 @@ static struct clksrc_clk clk_mout_mpll = { ...@@ -134,24 +134,6 @@ static struct clksrc_clk clk_mout_mpll = {
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
}; };
static struct clk clk_h_low = {
.name = "hclk_low",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.ops = &clk_ops_def_setrate,
};
static struct clk clk_p_low = {
.name = "pclk_low",
.id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
.ops = &clk_ops_def_setrate,
};
enum perf_level { enum perf_level {
L0 = 532*1000, L0 = 532*1000,
L1 = 266*1000, L1 = 266*1000,
...@@ -247,23 +229,70 @@ static struct clk_ops s5p6440_clkarm_ops = { ...@@ -247,23 +229,70 @@ static struct clk_ops s5p6440_clkarm_ops = {
.round_rate = s5p6440_armclk_round_rate, .round_rate = s5p6440_armclk_round_rate,
}; };
static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk) static struct clksrc_clk clk_armclk = {
{ .clk = {
unsigned long rate = clk_get_rate(clk->parent); .name = "armclk",
.id = 1,
.parent = &clk_mout_apll.clk,
.ops = &s5p6440_clkarm_ops,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
};
if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK) static struct clksrc_clk clk_dout_mpll = {
rate /= 2; .clk = {
.name = "dout_mpll",
.id = -1,
.parent = &clk_mout_mpll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
};
return rate; static struct clksrc_clk clk_hclk = {
} .clk = {
.name = "clk_hclk",
.id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
};
static struct clk clk_dout_mpll = { static struct clksrc_clk clk_pclk = {
.name = "dout_mpll", .clk = {
.id = -1, .name = "clk_pclk",
.parent = &clk_mout_mpll.clk, .id = -1,
.ops = &(struct clk_ops) { .parent = &clk_hclk.clk,
.get_rate = s5p6440_clk_doutmpll_get_rate,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
};
static struct clk *clkset_hclklow_list[] = {
&clk_mout_apll.clk,
&clk_mout_mpll.clk,
};
static struct clksrc_sources clkset_hclklow = {
.sources = clkset_hclklow_list,
.nr_sources = ARRAY_SIZE(clkset_hclklow_list),
};
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "hclk_low",
.id = -1,
},
.sources = &clkset_hclklow,
.reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
};
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "pclk_low",
.id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
}; };
int s5p6440_clk48m_ctrl(struct clk *clk, int enable) int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
...@@ -307,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable) ...@@ -307,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable); return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
} }
static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
}
static int s5p6440_mem_ctrl(struct clk *clk, int enable) static int s5p6440_mem_ctrl(struct clk *clk, int enable)
{ {
return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable); return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
...@@ -321,37 +355,37 @@ static struct clk init_clocks_disable[] = { ...@@ -321,37 +355,37 @@ static struct clk init_clocks_disable[] = {
{ {
.name = "nand", .name = "nand",
.id = -1, .id = -1,
.parent = &clk_h, .parent = &clk_hclk.clk,
.enable = s5p6440_mem_ctrl, .enable = s5p6440_mem_ctrl,
.ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON, .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
}, { }, {
.name = "adc", .name = "adc",
.id = -1, .id = -1,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_TSADC, .ctrlbit = S5P_CLKCON_PCLK_TSADC,
}, { }, {
.name = "i2c", .name = "i2c",
.id = -1, .id = -1,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_IIC0, .ctrlbit = S5P_CLKCON_PCLK_IIC0,
}, { }, {
.name = "i2s_v40", .name = "i2s_v40",
.id = 0, .id = 0,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_IIS2, .ctrlbit = S5P_CLKCON_PCLK_IIS2,
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .id = 0,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_SPI0, .ctrlbit = S5P_CLKCON_PCLK_SPI0,
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .id = 1,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_SPI1, .ctrlbit = S5P_CLKCON_PCLK_SPI1,
}, { }, {
...@@ -387,58 +421,124 @@ static struct clk init_clocks_disable[] = { ...@@ -387,58 +421,124 @@ static struct clk init_clocks_disable[] = {
}, { }, {
.name = "otg", .name = "otg",
.id = -1, .id = -1,
.parent = &clk_h_low, .parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl, .enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_USB .ctrlbit = S5P_CLKCON_HCLK0_USB
}, { }, {
.name = "post", .name = "post",
.id = -1, .id = -1,
.parent = &clk_h_low, .parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl, .enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_POST0 .ctrlbit = S5P_CLKCON_HCLK0_POST0
}, { }, {
.name = "lcd", .name = "lcd",
.id = -1, .id = -1,
.parent = &clk_h_low, .parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk1_ctrl, .enable = s5p6440_hclk1_ctrl,
.ctrlbit = S5P_CLKCON_HCLK1_DISPCON, .ctrlbit = S5P_CLKCON_HCLK1_DISPCON,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .id = 0,
.parent = &clk_h_low, .parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl, .enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_HSMMC0, .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1, .id = 1,
.parent = &clk_h_low, .parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl, .enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_HSMMC1, .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1,
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 2, .id = 2,
.parent = &clk_h_low, .parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl, .enable = s5p6440_hclk0_ctrl,
.ctrlbit = S5P_CLKCON_HCLK0_HSMMC2, .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2,
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1, .id = -1,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_RTC, .ctrlbit = S5P_CLKCON_PCLK_RTC,
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1, .id = -1,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_WDT, .ctrlbit = S5P_CLKCON_PCLK_WDT,
}, { }, {
.name = "timers", .name = "timers",
.id = -1, .id = -1,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_PWM, .ctrlbit = S5P_CLKCON_PCLK_PWM,
} }, {
.name = "hclk_fimgvg",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "tsi",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "pclk_fimgvg",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 31),
}, {
.name = "dmc0",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 30),
}, {
.name = "etm",
.id = -1,
.parent = &clk_pclk.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 29),
}, {
.name = "dsim",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "gps",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "pcm",
.id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "irom",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "dma",
.id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "2d",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 8),
},
}; };
/* /*
...@@ -448,34 +548,46 @@ static struct clk init_clocks[] = { ...@@ -448,34 +548,46 @@ static struct clk init_clocks[] = {
{ {
.name = "gpio", .name = "gpio",
.id = -1, .id = -1,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_GPIO, .ctrlbit = S5P_CLKCON_PCLK_GPIO,
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .id = 0,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART0, .ctrlbit = S5P_CLKCON_PCLK_UART0,
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .id = 1,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART1, .ctrlbit = S5P_CLKCON_PCLK_UART1,
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .id = 2,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART2, .ctrlbit = S5P_CLKCON_PCLK_UART2,
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .id = 3,
.parent = &clk_p_low, .parent = &clk_pclk_low.clk,
.enable = s5p6440_pclk_ctrl, .enable = s5p6440_pclk_ctrl,
.ctrlbit = S5P_CLKCON_PCLK_UART3, .ctrlbit = S5P_CLKCON_PCLK_UART3,
} }, {
.name = "mem",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "intc",
.id = -1,
.parent = &clk_hclk.clk,
.enable = s5p6440_hclk0_ctrl,
.ctrlbit = (1 << 1),
},
}; };
static struct clk clk_iis_cd_v40 = { static struct clk clk_iis_cd_v40 = {
...@@ -488,20 +600,20 @@ static struct clk clk_pcm_cd = { ...@@ -488,20 +600,20 @@ static struct clk clk_pcm_cd = {
.id = -1, .id = -1,
}; };
static struct clk *clkset_spi_mmc_list[] = { static struct clk *clkset_group1_list[] = {
&clk_mout_epll.clk, &clk_mout_epll.clk,
&clk_dout_mpll, &clk_dout_mpll.clk,
&clk_fin_epll, &clk_fin_epll,
}; };
static struct clksrc_sources clkset_spi_mmc = { static struct clksrc_sources clkset_group1 = {
.sources = clkset_spi_mmc_list, .sources = clkset_group1_list,
.nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), .nr_sources = ARRAY_SIZE(clkset_group1_list),
}; };
static struct clk *clkset_uart_list[] = { static struct clk *clkset_uart_list[] = {
&clk_mout_epll.clk, &clk_mout_epll.clk,
&clk_dout_mpll &clk_dout_mpll.clk,
}; };
static struct clksrc_sources clkset_uart = { static struct clksrc_sources clkset_uart = {
...@@ -509,6 +621,19 @@ static struct clksrc_sources clkset_uart = { ...@@ -509,6 +621,19 @@ static struct clksrc_sources clkset_uart = {
.nr_sources = ARRAY_SIZE(clkset_uart_list), .nr_sources = ARRAY_SIZE(clkset_uart_list),
}; };
static struct clk *clkset_audio_list[] = {
&clk_mout_epll.clk,
&clk_dout_mpll.clk,
&clk_fin_epll,
&clk_iis_cd_v40,
&clk_pcm_cd,
};
static struct clksrc_sources clkset_audio = {
.sources = clkset_audio_list,
.nr_sources = ARRAY_SIZE(clkset_audio_list),
};
static struct clksrc_clk clksrcs[] = { static struct clksrc_clk clksrcs[] = {
{ {
.clk = { .clk = {
...@@ -517,7 +642,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -517,7 +642,7 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S5P_CLKCON_SCLK0_MMC0, .ctrlbit = S5P_CLKCON_SCLK0_MMC0,
.enable = s5p6440_sclk_ctrl, .enable = s5p6440_sclk_ctrl,
}, },
.sources = &clkset_spi_mmc, .sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
}, { }, {
...@@ -527,7 +652,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -527,7 +652,7 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S5P_CLKCON_SCLK0_MMC1, .ctrlbit = S5P_CLKCON_SCLK0_MMC1,
.enable = s5p6440_sclk_ctrl, .enable = s5p6440_sclk_ctrl,
}, },
.sources = &clkset_spi_mmc, .sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
}, { }, {
...@@ -537,7 +662,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -537,7 +662,7 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S5P_CLKCON_SCLK0_MMC2, .ctrlbit = S5P_CLKCON_SCLK0_MMC2,
.enable = s5p6440_sclk_ctrl, .enable = s5p6440_sclk_ctrl,
}, },
.sources = &clkset_spi_mmc, .sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
}, { }, {
...@@ -557,7 +682,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -557,7 +682,7 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S5P_CLKCON_SCLK0_SPI0, .ctrlbit = S5P_CLKCON_SCLK0_SPI0,
.enable = s5p6440_sclk_ctrl, .enable = s5p6440_sclk_ctrl,
}, },
.sources = &clkset_spi_mmc, .sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
}, { }, {
...@@ -567,17 +692,63 @@ static struct clksrc_clk clksrcs[] = { ...@@ -567,17 +692,63 @@ static struct clksrc_clk clksrcs[] = {
.ctrlbit = S5P_CLKCON_SCLK0_SPI1, .ctrlbit = S5P_CLKCON_SCLK0_SPI1,
.enable = s5p6440_sclk_ctrl, .enable = s5p6440_sclk_ctrl,
}, },
.sources = &clkset_spi_mmc, .sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
} }, {
.clk = {
.name = "sclk_post",
.id = -1,
.ctrlbit = (1 << 10),
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
}, {
.clk = {
.name = "sclk_dispcon",
.id = -1,
.ctrlbit = (1 << 1),
.enable = s5p6440_sclk1_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_fimgvg",
.id = -1,
.ctrlbit = (1 << 2),
.enable = s5p6440_sclk1_ctrl,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_audio2",
.id = -1,
.ctrlbit = (1 << 11),
.enable = s5p6440_sclk_ctrl,
},
.sources = &clkset_audio,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
},
}; };
/* Clock initialisation code */ /* Clock initialisation code */
static struct clksrc_clk *init_parents[] = { static struct clksrc_clk *sysclks[] = {
&clk_mout_apll, &clk_mout_apll,
&clk_mout_epll, &clk_mout_epll,
&clk_mout_mpll, &clk_mout_mpll,
&clk_dout_mpll,
&clk_armclk,
&clk_hclk,
&clk_pclk,
&clk_hclk_low,
&clk_pclk_low,
}; };
void __init_or_cpufreq s5p6440_setup_clocks(void) void __init_or_cpufreq s5p6440_setup_clocks(void)
...@@ -593,21 +764,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) ...@@ -593,21 +764,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
unsigned long apll; unsigned long apll;
unsigned long mpll; unsigned long mpll;
unsigned int ptr; unsigned int ptr;
u32 clkdiv0;
u32 clkdiv3;
/* Set S5P6440 functions for clk_fout_epll */ /* Set S5P6440 functions for clk_fout_epll */
clk_fout_epll.enable = s5p6440_epll_enable; clk_fout_epll.enable = s5p6440_epll_enable;
clk_fout_epll.ops = &s5p6440_epll_ops; clk_fout_epll.ops = &s5p6440_epll_ops;
/* Set S5P6440 functions for arm clock */
clk_arm.parent = &clk_mout_apll.clk;
clk_arm.ops = &s5p6440_clkarm_ops;
clk_48m.enable = s5p6440_clk48m_ctrl; clk_48m.enable = s5p6440_clk48m_ctrl;
clkdiv0 = __raw_readl(S5P_CLK_DIV0);
clkdiv3 = __raw_readl(S5P_CLK_DIV3);
xtal_clk = clk_get(NULL, "ext_xtal"); xtal_clk = clk_get(NULL, "ext_xtal");
BUG_ON(IS_ERR(xtal_clk)); BUG_ON(IS_ERR(xtal_clk));
...@@ -619,41 +782,28 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) ...@@ -619,41 +782,28 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502); apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
" E=%ld.%ldMHz\n", " E=%ld.%ldMHz\n",
print_mhz(apll), print_mhz(mpll), print_mhz(epll)); print_mhz(apll), print_mhz(mpll), print_mhz(epll));
fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM); fclk = clk_get_rate(&clk_armclk.clk);
hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK); hclk = clk_get_rate(&clk_hclk.clk);
pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); pclk = clk_get_rate(&clk_pclk.clk);
hclk_low = clk_get_rate(&clk_hclk_low.clk);
if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { pclk_low = clk_get_rate(&clk_pclk_low.clk);
/* Asynchronous mode */
hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
} else {
/* Synchronous mode */
hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
}
pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW);
printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
print_mhz(hclk), print_mhz(hclk_low), print_mhz(hclk), print_mhz(hclk_low),
print_mhz(pclk), print_mhz(pclk_low)); print_mhz(pclk), print_mhz(pclk_low));
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_apll.rate = apll;
clk_f.rate = fclk; clk_f.rate = fclk;
clk_h.rate = hclk; clk_h.rate = hclk;
clk_p.rate = pclk; clk_p.rate = pclk;
clk_h_low.rate = hclk_low;
clk_p_low.rate = pclk_low;
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
s3c_set_clksrc(init_parents[ptr], true);
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
s3c_set_clksrc(&clksrcs[ptr], true); s3c_set_clksrc(&clksrcs[ptr], true);
...@@ -661,13 +811,8 @@ void __init_or_cpufreq s5p6440_setup_clocks(void) ...@@ -661,13 +811,8 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
static struct clk *clks[] __initdata = { static struct clk *clks[] __initdata = {
&clk_ext, &clk_ext,
&clk_mout_epll.clk,
&clk_mout_mpll.clk,
&clk_dout_mpll,
&clk_iis_cd_v40, &clk_iis_cd_v40,
&clk_pcm_cd, &clk_pcm_cd,
&clk_p_low,
&clk_h_low,
}; };
void __init s5p6440_register_clocks(void) void __init s5p6440_register_clocks(void)
...@@ -680,6 +825,9 @@ void __init s5p6440_register_clocks(void) ...@@ -680,6 +825,9 @@ void __init s5p6440_register_clocks(void)
if (ret > 0) if (ret > 0)
printk(KERN_ERR "Failed to register %u clocks\n", ret); printk(KERN_ERR "Failed to register %u clocks\n", ret);
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
......
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