提交 cbb53b96 编写于 作者: D Denys Vlasenko 提交者: Ingo Molnar

x86/asm/decoder: Explain CALLW discrepancy between Intel and AMD

In 64-bit mode, AMD and Intel CPUs treat 0x66 prefix before
branch insns differently. For near branches, it affects decode
too since immediate offset's width is different.

See these empirical tests:

  http://marc.info/?l=linux-kernel&m=139714939728946&w=2Signed-off-by: NDenys Vlasenko <dvlasenk@redhat.com>
Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Cc: Oleg Nesterov <oleg@redhat.com>
Link: http://lkml.kernel.org/r/1423768017-31766-1-git-send-email-dvlasenk@redhat.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
上级 8a764a87
...@@ -273,6 +273,9 @@ dd: ESC ...@@ -273,6 +273,9 @@ dd: ESC
de: ESC de: ESC
df: ESC df: ESC
# 0xe0 - 0xef # 0xe0 - 0xef
# Note: "forced64" is Intel CPU behavior: they ignore 0x66 prefix
# in 64-bit mode. AMD CPUs accept 0x66 prefix, it causes RIP truncation
# to 16 bits. In 32-bit mode, 0x66 is accepted by both Intel and AMD.
e0: LOOPNE/LOOPNZ Jb (f64) e0: LOOPNE/LOOPNZ Jb (f64)
e1: LOOPE/LOOPZ Jb (f64) e1: LOOPE/LOOPZ Jb (f64)
e2: LOOP Jb (f64) e2: LOOP Jb (f64)
...@@ -281,6 +284,10 @@ e4: IN AL,Ib ...@@ -281,6 +284,10 @@ e4: IN AL,Ib
e5: IN eAX,Ib e5: IN eAX,Ib
e6: OUT Ib,AL e6: OUT Ib,AL
e7: OUT Ib,eAX e7: OUT Ib,eAX
# With 0x66 prefix in 64-bit mode, for AMD CPUs immediate offset
# in "near" jumps and calls is 16-bit. For CALL,
# push of return address is 16-bit wide, RSP is decremented by 2
# but is not truncated to 16 bits, unlike RIP.
e8: CALL Jz (f64) e8: CALL Jz (f64)
e9: JMP-near Jz (f64) e9: JMP-near Jz (f64)
ea: JMP-far Ap (i64) ea: JMP-far Ap (i64)
...@@ -456,6 +463,7 @@ AVXcode: 1 ...@@ -456,6 +463,7 @@ AVXcode: 1
7e: movd/q Ey,Pd | vmovd/q Ey,Vy (66),(v1) | vmovq Vq,Wq (F3),(v1) 7e: movd/q Ey,Pd | vmovd/q Ey,Vy (66),(v1) | vmovq Vq,Wq (F3),(v1)
7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqu Wx,Vx (F3) 7f: movq Qq,Pq | vmovdqa Wx,Vx (66) | vmovdqu Wx,Vx (F3)
# 0x0f 0x80-0x8f # 0x0f 0x80-0x8f
# Note: "forced64" is Intel CPU behavior (see comment about CALL insn).
80: JO Jz (f64) 80: JO Jz (f64)
81: JNO Jz (f64) 81: JNO Jz (f64)
82: JB/JC/JNAE Jz (f64) 82: JB/JC/JNAE Jz (f64)
...@@ -842,6 +850,7 @@ EndTable ...@@ -842,6 +850,7 @@ EndTable
GrpTable: Grp5 GrpTable: Grp5
0: INC Ev 0: INC Ev
1: DEC Ev 1: DEC Ev
# Note: "forced64" is Intel CPU behavior (see comment about CALL insn).
2: CALLN Ev (f64) 2: CALLN Ev (f64)
3: CALLF Ep 3: CALLF Ep
4: JMPN Ev (f64) 4: JMPN Ev (f64)
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册