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提交 ca61f10a 编写于 作者: J James Bottomley
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[SCSI] remove broken driver cpqfc 

Hopefully there should be a brand new replacement driver for this heap
of junk by the beginning of next year.

Acked By: Martin K. Petersen <mkp@mkp.net>
Signed-off-by: NJames Bottomley <James.Bottomley@SteelEye.com>
上级 80e23bab
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drivers/scsi/Kconfig
浏览文件 @ ca61f10a
......@@ -620,19 +620,6 @@ config SCSI_OMIT_FLASHPOINT
substantial, so users of MultiMaster Host Adapters may wish to omit
it.
#
# This is marked broken because it uses over 4kB of stack in
# just two routines:
# 2076 CpqTsProcessIMQEntry
# 2052 PeekIMQEntry
#
config SCSI_CPQFCTS
tristate "Compaq Fibre Channel 64-bit/66Mhz HBA support"
depends on PCI && SCSI && BROKEN
help
Say Y here to compile in support for the Compaq StorageWorks Fibre
Channel 64-bit/66Mhz Host Bus Adapter.
config SCSI_DMX3191D
tristate "DMX3191D SCSI support"
depends on PCI && SCSI
......
drivers/scsi/Makefile
浏览文件 @ ca61f10a
......@@ -120,7 +120,6 @@ obj-$(CONFIG_JAZZ_ESP) += NCR53C9x.o jazz_esp.o
obj-$(CONFIG_SUN3X_ESP) += NCR53C9x.o sun3x_esp.o
obj-$(CONFIG_SCSI_DEBUG) += scsi_debug.o
obj-$(CONFIG_SCSI_FCAL) += fcal.o
obj-$(CONFIG_SCSI_CPQFCTS) += cpqfc.o
obj-$(CONFIG_SCSI_LASI700) += 53c700.o lasi700.o
obj-$(CONFIG_SCSI_NSP32) += nsp32.o
obj-$(CONFIG_SCSI_IPR) += ipr.o
......@@ -165,8 +164,6 @@ ncr53c8xx-flags-$(CONFIG_SCSI_ZALON) \
CFLAGS_ncr53c8xx.o := $(ncr53c8xx-flags-y) $(ncr53c8xx-flags-m)
zalon7xx-objs := zalon.o ncr53c8xx.o
NCR_Q720_mod-objs := NCR_Q720.o ncr53c8xx.o
cpqfc-objs := cpqfcTSinit.o cpqfcTScontrol.o cpqfcTSi2c.o \
cpqfcTSworker.o cpqfcTStrigger.o
libata-objs := libata-core.o libata-scsi.o
# Files generated that shall be removed upon make clean
......
drivers/scsi/cpqfcTS.h 已删除 100644 → 0
浏览文件 @ 80e23bab
#ifndef CPQFCTS_H
#define CPQFCTS_H
#include "cpqfcTSstructs.h"
// These functions are required by the Linux SCSI layers
extern int cpqfcTS_detect(Scsi_Host_Template *);
extern int cpqfcTS_release(struct Scsi_Host *);
extern const char * cpqfcTS_info(struct Scsi_Host *);
extern int cpqfcTS_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
extern int cpqfcTS_queuecommand(Scsi_Cmnd *, void (* done)(Scsi_Cmnd *));
extern int cpqfcTS_abort(Scsi_Cmnd *);
extern int cpqfcTS_reset(Scsi_Cmnd *, unsigned int);
extern int cpqfcTS_eh_abort(Scsi_Cmnd *Cmnd);
extern int cpqfcTS_eh_device_reset(Scsi_Cmnd *);
extern int cpqfcTS_biosparam(struct scsi_device *, struct block_device *,
sector_t, int[]);
extern int cpqfcTS_ioctl( Scsi_Device *ScsiDev, int Cmnd, void *arg);
#endif /* CPQFCTS_H */
drivers/scsi/cpqfcTSchip.h 已删除 100644 → 0
浏览文件 @ 80e23bab
/* Copyright(c) 2000, Compaq Computer Corporation
* Fibre Channel Host Bus Adapter
* 64-bit, 66MHz PCI
* Originally developed and tested on:
* (front): [chip] Tachyon TS HPFC-5166A/1.2 L2C1090 ...
* SP# P225CXCBFIEL6T, Rev XC
* SP# 161290-001, Rev XD
* (back): Board No. 010008-001 A/W Rev X5, FAB REV X5
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
* Written by Don Zimmerman
*/
#ifndef CPQFCTSCHIP_H
#define CPQFCTSCHIP_H
#ifndef TACHYON_CHIP_INC
// FC-PH (Physical) specification levels for Login payloads
// NOTE: These are NOT strictly complied with by any FC vendors
#define FC_PH42 0x08
#define FC_PH43 0x09
#define FC_PH3 0x20
#define TACHLITE_TS_RX_SIZE 1024 // max inbound frame size
// "I" prefix is for Include
#define IVENDID 0x00 // word
#define IDEVID 0x02
#define ITLCFGCMD 0x04
#define IMEMBASE 0x18 // Tachyon
#define ITLMEMBASE 0x1C // Tachlite
#define IIOBASEL 0x10 // Tachyon I/O base address, lower 256 bytes
#define IIOBASEU 0x14 // Tachyon I/O base address, upper 256 bytes
#define ITLIOBASEL 0x14 // TachLite I/O base address, lower 256 bytes
#define ITLIOBASEU 0x18 // TachLite I/O base address, upper 256 bytes
#define ITLRAMBASE 0x20 // TL on-board RAM start
#define ISROMBASE 0x24
#define IROMBASE 0x30
#define ICFGCMD 0x04 // PCI config - PCI config access (word)
#define ICFGSTAT 0x06 // PCI status (R - word)
#define IRCTR_WCTR 0x1F2 // ROM control / pre-fetch wait counter
#define IPCIMCTR 0x1F3 // PCI master control register
#define IINTPEND 0x1FD // Interrupt pending (I/O Upper - Tachyon & TL)
#define IINTEN 0x1FE // Interrupt enable (I/O Upper - Tachyon & TL)
#define IINTSTAT 0x1FF // Interrupt status (I/O Upper - Tachyon & TL)
#define IMQ_BASE 0x80
#define IMQ_LENGTH 0x84
#define IMQ_CONSUMER_INDEX 0x88
#define IMQ_PRODUCER_INDEX 0x8C // Tach copies its INDX to bits 0-7 of value
/*
// IOBASE UPPER
#define SFSBQ_BASE 0x00 // single-frame sequences
#define SFSBQ_LENGTH 0x04
#define SFSBQ_PRODUCER_INDEX 0x08
#define SFSBQ_CONSUMER_INDEX 0x0C // (R)
#define SFS_BUFFER_LENGTH 0X10
// SCSI-FCP hardware assists
#define SEST_BASE 0x40 // SSCI Exchange State Table
#define SEST_LENGTH 0x44
#define SCSI_BUFFER_LENGTH 0x48
#define SEST_LINKED_LIST 0x4C
#define TACHYON_My_ID 0x6C
#define TACHYON_CONFIGURATION 0x84 // (R/W) reset val 2
#define TACHYON_CONTROL 0x88
#define TACHYON_STATUS 0x8C // (R)
#define TACHYON_FLUSH_SEST 0x90 // (R/W)
#define TACHYON_EE_CREDIT_TMR 0x94 // (R)
#define TACHYON_BB_CREDIT_TMR 0x98 // (R)
#define TACHYON_RCV_FRAME_ERR 0x9C // (R)
#define FRAME_MANAGER_CONFIG 0xC0 // (R/W)
#define FRAME_MANAGER_CONTROL 0xC4
#define FRAME_MANAGER_STATUS 0xC8 // (R)
#define FRAME_MANAGER_ED_TOV 0xCC
#define FRAME_MANAGER_LINK_ERR1 0xD0 // (R)
#define FRAME_MANAGER_LINK_ERR2 0xD4 // (R)
#define FRAME_MANAGER_TIMEOUT2 0xD8 // (W)
#define FRAME_MANAGER_BB_CREDIT 0xDC // (R)
#define FRAME_MANAGER_WWN_HI 0xE0 // (R/W)
#define FRAME_MANAGER_WWN_LO 0xE4 // (R/W)
#define FRAME_MANAGER_RCV_AL_PA 0xE8 // (R)
#define FRAME_MANAGER_PRIMITIVE 0xEC // {K28.5} byte1 byte2 byte3
*/
#define TL_MEM_ERQ_BASE 0x0 //ERQ Base
#define TL_IO_ERQ_BASE 0x0 //ERQ base
#define TL_MEM_ERQ_LENGTH 0x4 //ERQ Length
#define TL_IO_ERQ_LENGTH 0x4 //ERQ Length
#define TL_MEM_ERQ_PRODUCER_INDEX 0x8 //ERQ Producer Index register
#define TL_IO_ERQ_PRODUCER_INDEX 0x8 //ERQ Producer Index register
#define TL_MEM_ERQ_CONSUMER_INDEX_ADR 0xC //ERQ Consumer Index address register
#define TL_IO_ERQ_CONSUMER_INDEX_ADR 0xC //ERQ Consumer Index address register
#define TL_MEM_ERQ_CONSUMER_INDEX 0xC //ERQ Consumer Index
#define TL_IO_ERQ_CONSUMER_INDEX 0xC //ERQ Consumer Index
#define TL_MEM_SFQ_BASE 0x50 //SFQ Base
#define TL_IO_SFQ_BASE 0x50 //SFQ base
#define TL_MEM_SFQ_LENGTH 0x54 //SFQ Length
#define TL_IO_SFQ_LENGTH 0x54 //SFQ Length
#define TL_MEM_SFQ_CONSUMER_INDEX 0x58 //SFQ Consumer Index
#define TL_IO_SFQ_CONSUMER_INDEX 0x58 //SFQ Consumer Index
#define TL_MEM_IMQ_BASE 0x80 //IMQ Base
#define TL_IO_IMQ_BASE 0x80 //IMQ base
#define TL_MEM_IMQ_LENGTH 0x84 //IMQ Length
#define TL_IO_IMQ_LENGTH 0x84 //IMQ Length
#define TL_MEM_IMQ_CONSUMER_INDEX 0x88 //IMQ Consumer Index
#define TL_IO_IMQ_CONSUMER_INDEX 0x88 //IMQ Consumer Index
#define TL_MEM_IMQ_PRODUCER_INDEX_ADR 0x8C //IMQ Producer Index address register
#define TL_IO_IMQ_PRODUCER_INDEX_ADR 0x8C //IMQ Producer Index address register
#define TL_MEM_SEST_BASE 0x140 //SFQ Base
#define TL_IO_SEST_BASE 0x40 //SFQ base
#define TL_MEM_SEST_LENGTH 0x144 //SFQ Length
#define TL_IO_SEST_LENGTH 0x44 //SFQ Length
#define TL_MEM_SEST_LINKED_LIST 0x14C
#define TL_MEM_SEST_SG_PAGE 0x168 // Extended Scatter/Gather page size
#define TL_MEM_TACH_My_ID 0x16C
#define TL_IO_TACH_My_ID 0x6C //My AL_PA ID
#define TL_MEM_TACH_CONFIG 0x184 //Tachlite Configuration register
#define TL_IO_CONFIG 0x84 //Tachlite Configuration register
#define TL_MEM_TACH_CONTROL 0x188 //Tachlite Control register
#define TL_IO_CTR 0x88 //Tachlite Control register
#define TL_MEM_TACH_STATUS 0x18C //Tachlite Status register
#define TL_IO_STAT 0x8C //Tachlite Status register
#define TL_MEM_FM_CONFIG 0x1C0 //Frame Manager Configuration register
#define TL_IO_FM_CONFIG 0xC0 //Frame Manager Configuration register
#define TL_MEM_FM_CONTROL 0x1C4 //Frame Manager Control
#define TL_IO_FM_CTL 0xC4 //Frame Manager Control
#define TL_MEM_FM_STATUS 0x1C8 //Frame Manager Status
#define TL_IO_FM_STAT 0xC8 //Frame Manager Status
#define TL_MEM_FM_LINK_STAT1 0x1D0 //Frame Manager Link Status 1
#define TL_IO_FM_LINK_STAT1 0xD0 //Frame Manager Link Status 1
#define TL_MEM_FM_LINK_STAT2 0x1D4 //Frame Manager Link Status 2
#define TL_IO_FM_LINK_STAT2 0xD4 //Frame Manager Link Status 2
#define TL_MEM_FM_TIMEOUT2 0x1D8 // (W)
#define TL_MEM_FM_BB_CREDIT0 0x1DC
#define TL_MEM_FM_WWN_HI 0x1E0 //Frame Manager World Wide Name High
#define TL_IO_FM_WWN_HI 0xE0 //Frame Manager World Wide Name High
#define TL_MEM_FM_WWN_LO 0x1E4 //Frame Manager World Wide Name LOW
#define TL_IO_FM_WWN_LO 0xE4 //Frame Manager World Wide Name Low
#define TL_MEM_FM_RCV_AL_PA 0x1E8 //Frame Manager AL_PA Received register
#define TL_IO_FM_ALPA 0xE8 //Frame Manager AL_PA Received register
#define TL_MEM_FM_ED_TOV 0x1CC
#define TL_IO_ROMCTR 0xFA //TL PCI ROM Control Register
#define TL_IO_PCIMCTR 0xFB //TL PCI Master Control Register
#define TL_IO_SOFTRST 0xFC //Tachlite Configuration register
#define TL_MEM_SOFTRST 0x1FC //Tachlite Configuration register
// completion message types (bit 8 set means Interrupt generated)
// CM_Type
#define OUTBOUND_COMPLETION 0
#define ERROR_IDLE_COMPLETION 0x01
#define OUT_HI_PRI_COMPLETION 0x01
#define INBOUND_MFS_COMPLETION 0x02
#define INBOUND_000_COMPLETION 0x03
#define INBOUND_SFS_COMPLETION 0x04 // Tachyon & TachLite
#define ERQ_FROZEN_COMPLETION 0x06 // TachLite
#define INBOUND_C1_TIMEOUT 0x05
#define INBOUND_BUSIED_FRAME 0x06
#define SFS_BUF_WARN 0x07
#define FCP_FROZEN_COMPLETION 0x07 // TachLite
#define MFS_BUF_WARN 0x08
#define IMQ_BUF_WARN 0x09
#define FRAME_MGR_INTERRUPT 0x0A
#define READ_STATUS 0x0B
#define INBOUND_SCSI_DATA_COMPLETION 0x0C
#define INBOUND_FCP_XCHG_COMPLETION 0x0C // TachLite
#define INBOUND_SCSI_DATA_COMMAND 0x0D
#define BAD_SCSI_FRAME 0x0E
#define INB_SCSI_STATUS_COMPLETION 0x0F
#define BUFFER_PROCESSED_COMPLETION 0x11
// FC-AL (Tachyon) Loop Port State Machine defs
// (loop "Up" states)
#define MONITORING 0x0
#define ARBITRATING 0x1
#define ARBITRAT_WON 0x2
#define OPEN 0x3
#define OPENED 0x4
#define XMITTD_CLOSE 0x5
#define RCVD_CLOSE 0x6
#define TRANSFER 0x7
// (loop "Down" states)
#define INITIALIZING 0x8
#define O_I_INIT 0x9
#define O_I_PROTOCOL 0xa
#define O_I_LIP_RCVD 0xb
#define HOST_CONTROL 0xc
#define LOOP_FAIL 0xd
// (no 0xe)
#define OLD_PORT 0xf
#define TACHYON_CHIP_INC
#endif
#endif /* CPQFCTSCHIP_H */
drivers/scsi/cpqfcTScontrol.c 已删除 100644 → 0
浏览文件 @ 80e23bab
此差异已折叠。
drivers/scsi/cpqfcTSi2c.c 已删除 100644 → 0
浏览文件 @ 80e23bab
/* Copyright(c) 2000, Compaq Computer Corporation
* Fibre Channel Host Bus Adapter
* 64-bit, 66MHz PCI
* Originally developed and tested on:
* (front): [chip] Tachyon TS HPFC-5166A/1.2 L2C1090 ...
* SP# P225CXCBFIEL6T, Rev XC
* SP# 161290-001, Rev XD
* (back): Board No. 010008-001 A/W Rev X5, FAB REV X5
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
* later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
* Written by Don Zimmerman
*/
// These functions control the NVRAM I2C hardware on
// non-intelligent Fibre Host Adapters.
// The primary purpose is to read the HBA's NVRAM to get adapter's
// manufactured WWN to copy into Tachyon chip registers
// Orignal source author unknown
#include <linux/types.h>
enum boolean { FALSE, TRUE } ;
#ifndef UCHAR
typedef __u8 UCHAR;
#endif
#ifndef BOOLEAN
typedef __u8 BOOLEAN;
#endif
#ifndef USHORT
typedef __u16 USHORT;
#endif
#ifndef ULONG
typedef __u32 ULONG;
#endif
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <asm/io.h> // struct pt_regs for IRQ handler & Port I/O
#include "cpqfcTSchip.h"
static void tl_i2c_tx_byte( void* GPIOout, UCHAR data );
/*static BOOLEAN tl_write_i2c_page_portion( void* GPIOin, void* GPIOout,
USHORT startOffset, // e.g. 0x2f for WWN start
USHORT count,
UCHAR *buf );
*/
//
// Tachlite GPIO2, GPIO3 (I2C) DEFINES
// The NVRAM chip NM24C03 defines SCL (serial clock) and SDA (serial data)
// GPIO2 drives SDA, and GPIO3 drives SCL
//
// Since Tachlite inverts the state of the GPIO 0-3 outputs, SET writes 0
// and clear writes 1. The input lines (read in TL status) is NOT inverted
// This really helps confuse the code and debugging.
#define SET_DATA_HI 0x0
#define SET_DATA_LO 0x8
#define SET_CLOCK_HI 0x0
#define SET_CLOCK_LO 0x4
#define SENSE_DATA_HI 0x8
#define SENSE_DATA_LO 0x0
#define SENSE_CLOCK_HI 0x4
#define SENSE_CLOCK_LO 0x0
#define SLAVE_READ_ADDRESS 0xA1
#define SLAVE_WRITE_ADDRESS 0xA0
static void i2c_delay(ULONG mstime);
static void tl_i2c_clock_pulse( UCHAR , void* GPIOout);
static UCHAR tl_read_i2c_data( void* );
//-----------------------------------------------------------------------------
//
// Name: I2C_RX_ACK
//
// This routine receives an acknowledge over the I2C bus.
//
//-----------------------------------------------------------------------------
static unsigned short tl_i2c_rx_ack( void* GPIOin, void* GPIOout )
{
unsigned long value;
// do clock pulse, let data line float high
tl_i2c_clock_pulse( SET_DATA_HI, GPIOout );
// slave must drive data low for acknowledge
value = tl_read_i2c_data( GPIOin);
if (value & SENSE_DATA_HI )
return( FALSE );
return( TRUE );
}
//-----------------------------------------------------------------------------
//
// Name: READ_I2C_REG
//
// This routine reads the I2C control register using the global
// IO address stored in gpioreg.
//
//-----------------------------------------------------------------------------
static UCHAR tl_read_i2c_data( void* gpioreg )
{
return( (UCHAR)(readl( gpioreg ) & 0x08L) ); // GPIO3
}
//-----------------------------------------------------------------------------
//
// Name: WRITE_I2C_REG
//
// This routine writes the I2C control register using the global
// IO address stored in gpioreg.
// In Tachlite, we don't want to modify other bits in TL Control reg.
//
//-----------------------------------------------------------------------------
static void tl_write_i2c_reg( void* gpioregOUT, UCHAR value )
{
ULONG temp;
// First read the register and clear out the old bits
temp = readl( gpioregOUT ) & 0xfffffff3L;
// Now or in the new data and send it back out
writel( temp | value, gpioregOUT);
}
//-----------------------------------------------------------------------------
//
// Name: I2C_TX_START
//
// This routine transmits a start condition over the I2C bus.
// 1. Set SCL (clock, GPIO2) HIGH, set SDA (data, GPIO3) HIGH,
// wait 5us to stabilize.
// 2. With SCL still HIGH, drive SDA low. The low transition marks
// the start condition to NM24Cxx (the chip)
// NOTE! In TL control reg., output 1 means chip sees LOW
//
//-----------------------------------------------------------------------------
static unsigned short tl_i2c_tx_start( void* GPIOin, void* GPIOout )
{
unsigned short i;
ULONG value;
if ( !(tl_read_i2c_data(GPIOin) & SENSE_DATA_HI))
{
// start with clock high, let data float high
tl_write_i2c_reg( GPIOout, SET_DATA_HI | SET_CLOCK_HI );
// keep sending clock pulses if slave is driving data line
for (i = 0; i < 10; i++)
{
tl_i2c_clock_pulse( SET_DATA_HI, GPIOout );
if ( tl_read_i2c_data(GPIOin) & SENSE_DATA_HI )
break;
}
// if he's still driving data low after 10 clocks, abort
value = tl_read_i2c_data( GPIOin ); // read status
if (!(value & 0x08) )
return( FALSE );
}
// To START, bring data low while clock high
tl_write_i2c_reg( GPIOout, SET_CLOCK_HI | SET_DATA_LO );
i2c_delay(0);
return( TRUE ); // TX start successful
}
//-----------------------------------------------------------------------------
//
// Name: I2C_TX_STOP
//
// This routine transmits a stop condition over the I2C bus.
//
//-----------------------------------------------------------------------------
static unsigned short tl_i2c_tx_stop( void* GPIOin, void* GPIOout )
{
int i;
for (i = 0; i < 10; i++)
{
// Send clock pulse, drive data line low
tl_i2c_clock_pulse( SET_DATA_LO, GPIOout );
// To STOP, bring data high while clock high
tl_write_i2c_reg( GPIOout, SET_DATA_HI | SET_CLOCK_HI );
// Give the data line time to float high
i2c_delay(0);
// If slave is driving data line low, there's a problem; retry
if ( tl_read_i2c_data(GPIOin) & SENSE_DATA_HI )
return( TRUE ); // TX STOP successful!
}
return( FALSE ); // error
}
//-----------------------------------------------------------------------------
//
// Name: I2C_TX_uchar
//
// This routine transmits a byte across the I2C bus.
//
//-----------------------------------------------------------------------------
static void tl_i2c_tx_byte( void* GPIOout, UCHAR data )
{
UCHAR bit;
for (bit = 0x80; bit; bit >>= 1)
{
if( data & bit )
tl_i2c_clock_pulse( (UCHAR)SET_DATA_HI, GPIOout);
else
tl_i2c_clock_pulse( (UCHAR)SET_DATA_LO, GPIOout);
}
}
//-----------------------------------------------------------------------------
//
// Name: I2C_RX_uchar
//
// This routine receives a byte across the I2C bus.
//
//-----------------------------------------------------------------------------
static UCHAR tl_i2c_rx_byte( void* GPIOin, void* GPIOout )
{
UCHAR bit;
UCHAR data = 0;
for (bit = 0x80; bit; bit >>= 1) {
// do clock pulse, let data line float high
tl_i2c_clock_pulse( SET_DATA_HI, GPIOout );
// read data line
if ( tl_read_i2c_data( GPIOin) & 0x08 )
data |= bit;
}
return (data);
}
//*****************************************************************************
//*****************************************************************************
// Function: read_i2c_nvram
// Arguments: UCHAR count number of bytes to read
// UCHAR *buf area to store the bytes read
// Returns: 0 - failed
// 1 - success
//*****************************************************************************
//*****************************************************************************
unsigned long cpqfcTS_ReadNVRAM( void* GPIOin, void* GPIOout , USHORT count,
UCHAR *buf )
{
unsigned short i;
if( !( tl_i2c_tx_start(GPIOin, GPIOout) ))
return FALSE;
// Select the NVRAM for "dummy" write, to set the address
tl_i2c_tx_byte( GPIOout , SLAVE_WRITE_ADDRESS );
if ( !tl_i2c_rx_ack(GPIOin, GPIOout ) )
return( FALSE );
// Now send the address where we want to start reading
tl_i2c_tx_byte( GPIOout , 0 );
if ( !tl_i2c_rx_ack(GPIOin, GPIOout ) )
return( FALSE );
// Send a repeated start condition and select the
// slave for reading now.
if( tl_i2c_tx_start(GPIOin, GPIOout) )
tl_i2c_tx_byte( GPIOout, SLAVE_READ_ADDRESS );
if ( !tl_i2c_rx_ack(GPIOin, GPIOout) )
return( FALSE );
// this loop will now read out the data and store it
// in the buffer pointed to by buf
for ( i=0; i<count; i++)
{
*buf++ = tl_i2c_rx_byte(GPIOin, GPIOout);
// Send ACK by holding data line low for 1 clock
if ( i < (count-1) )
tl_i2c_clock_pulse( 0x08, GPIOout );
else {
// Don't send ack for final byte
tl_i2c_clock_pulse( SET_DATA_HI, GPIOout );
}
}
tl_i2c_tx_stop(GPIOin, GPIOout);
return( TRUE );
}
//****************************************************************
//
//
//
// routines to set and clear the data and clock bits
//
//
//
//****************************************************************
static void tl_set_clock(void* gpioreg)
{
ULONG ret_val;
ret_val = readl( gpioreg );
ret_val &= 0xffffffFBL; // clear GPIO2 (SCL)
writel( ret_val, gpioreg);
}
static void tl_clr_clock(void* gpioreg)
{
ULONG ret_val;
ret_val = readl( gpioreg );
ret_val |= SET_CLOCK_LO;
writel( ret_val, gpioreg);
}
//*****************************************************************
//
//
// This routine will advance the clock by one period
//
//
//*****************************************************************
static void tl_i2c_clock_pulse( UCHAR value, void* GPIOout )
{
ULONG ret_val;
// clear the clock bit
tl_clr_clock( GPIOout );
i2c_delay(0);
// read the port to preserve non-I2C bits
ret_val = readl( GPIOout );
// clear the data & clock bits
ret_val &= 0xFFFFFFf3;
// write the value passed in...
// data can only change while clock is LOW!
ret_val |= value; // the data
ret_val |= SET_CLOCK_LO; // the clock
writel( ret_val, GPIOout );
i2c_delay(0);
//set clock bit
tl_set_clock( GPIOout);
}
//*****************************************************************
//
//
// This routine returns the 64-bit WWN
//
//
//*****************************************************************
int cpqfcTS_GetNVRAM_data( UCHAR *wwnbuf, UCHAR *buf )
{
ULONG len;
ULONG sub_len;
ULONG ptr_inc;
ULONG i;
ULONG j;
UCHAR *data_ptr;
UCHAR z;
UCHAR name;
UCHAR sub_name;
UCHAR done;
int iReturn=0; // def. 0 offset is failure to find WWN field
data_ptr = (UCHAR *)buf;
done = FALSE;
i = 0;
while ( (i < 128) && (!done) )
{
z = data_ptr[i];\
if ( !(z & 0x80) )
{
len = 1 + (z & 0x07);
name = (z & 0x78) >> 3;
if (name == 0x0F)
done = TRUE;
}
else
{
name = z & 0x7F;
len = 3 + data_ptr[i+1] + (data_ptr[i+2] << 8);
switch (name)
{
case 0x0D:
//
j = i + 3;
//
if ( data_ptr[j] == 0x3b ) {
len = 6;
break;
}
while ( j<(i+len) ) {
sub_name = (data_ptr[j] & 0x3f);
sub_len = data_ptr[j+1] +
(data_ptr[j+2] << 8);
ptr_inc = sub_len + 3;
switch (sub_name)
{
case 0x3C:
memcpy( wwnbuf, &data_ptr[j+3], 8);
iReturn = j+3;
break;
default:
break;
}
j += ptr_inc;
}
break;
default:
break;
}
}
//
i += len;
} // end while
return iReturn;
}
// define a short 5 micro sec delay, and longer (ms) delay
static void i2c_delay(ULONG mstime)
{
ULONG i;
// NOTE: we only expect to use these delays when reading
// our adapter's NVRAM, which happens only during adapter reset.
// Delay technique from "Linux Device Drivers", A. Rubini
// (1st Ed.) pg 137.
// printk(" delay %lx ", mstime);
if( mstime ) // ms delay?
{
// delay technique
for( i=0; i < mstime; i++)
udelay(1000); // 1ms per loop
}
else // 5 micro sec delay
udelay( 5 ); // micro secs
// printk("done\n");
}
drivers/scsi/cpqfcTSinit.c 已删除 100644 → 0
浏览文件 @ 80e23bab
此差异已折叠。
drivers/scsi/cpqfcTSioctl.h 已删除 100644 → 0
浏览文件 @ 80e23bab
// for user apps, make sure data size types are defined
// with
#define CCPQFCTS_IOC_MAGIC 'Z'
typedef struct
{
__u8 bus;
__u8 dev_fn;
__u32 board_id;
} cpqfc_pci_info_struct;
typedef __u32 DriverVer_type;
/*
typedef union
{
struct // Peripheral Unit Device
{
__u8 Bus:6;
__u8 Mode:2; // b00
__u8 Dev;
} PeripDev;
struct // Volume Set Address
{
__u8 DevMSB:6;
__u8 Mode:2; // b01
__u8 DevLSB;
} LogDev;
struct // Logical Unit Device (SCSI-3, SCC-2 defined)
{
__u8 Targ:6;
__u8 Mode:2; // b10
__u8 Dev:5;
__u8 Bus:3;
} LogUnit;
} SCSI3Addr_struct;
typedef struct
{
SCSI3Addr_struct FCP_Nexus;
__u8 cdb[16];
} PassThru_Command_struct;
*/
/* this is nearly duplicated in idashare.h */
typedef struct {
int lc; /* Controller number */
int node; /* Node (box) number */
int ld; /* Logical Drive on this box, if required */
__u32 nexus; /* SCSI Nexus */
void *argp; /* Argument pointer */
} VENDOR_IOCTL_REQ;
typedef struct {
char cdb[16]; /* SCSI CDB for the pass-through */
ushort bus; /* Target bus on the box */
ushort pdrive; /* Physical drive on the box */
int len; /* Length of the data area of the CDB */
int sense_len; /* Length of the sense data */
char sense_data[40]; /* Sense data */
void *bufp; /* Data area for the CDB */
char rw_flag; /* Read CDB or Write CDB */
} cpqfc_passthru_t;
/*
** Defines for the IOCTLS.
*/
#define VENDOR_READ_OPCODE 0x26
#define VENDOR_WRITE_OPCODE 0x27
#define CPQFCTS_GETPCIINFO _IOR( CCPQFCTS_IOC_MAGIC, 1, cpqfc_pci_info_struct)
#define CPQFCTS_GETDRIVVER _IOR( CCPQFCTS_IOC_MAGIC, 9, DriverVer_type)
#define CPQFCTS_SCSI_PASSTHRU _IOWR( CCPQFCTS_IOC_MAGIC,11, VENDOR_IOCTL_REQ)
/* We would rather have equivalent generic, low-level driver agnostic
ioctls that do what CPQFC_IOCTL_FC_TARGET_ADDRESS and
CPQFC_IOCTL_FC_TDR 0x5388 do, but currently, we do not have them,
consequently applications would have to know they are talking to cpqfc. */
/* Used to get Fibre Channel WWN and port_id from device */
// #define CPQFC_IOCTL_FC_TARGET_ADDRESS 0x5387
#define CPQFC_IOCTL_FC_TARGET_ADDRESS \
_IOR( CCPQFCTS_IOC_MAGIC, 13, Scsi_FCTargAddress)
/* Used to invoke Target Defice Reset for Fibre Channel */
// #define CPQFC_IOCTL_FC_TDR 0x5388
#define CPQFC_IOCTL_FC_TDR _IO( CCPQFCTS_IOC_MAGIC, 15)
drivers/scsi/cpqfcTSstructs.h 已删除 100644 → 0
浏览文件 @ 80e23bab
此差异已折叠。
drivers/scsi/cpqfcTStrigger.c 已删除 100644 → 0
浏览文件 @ 80e23bab
// Routine to trigger Finisar GTA analyzer. Runs of GPIO2
// NOTE: DEBUG ONLY! Could interfere with FCMNGR/Miniport operation
// since it writes directly to the Tachyon board. This function
// developed for Compaq HBA Tachyon TS v1.2 (Rev X5 PCB)
#include "cpqfcTStrigger.h"
#if TRIGGERABLE_HBA
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/io.h>
void TriggerHBA( void* IOBaseUpper, int Print)
{
__u32 long value;
// get initial value in hopes of not modifying any other GPIO line
IOBaseUpper += 0x188; // TachTL/TS Control reg
value = readl( IOBaseUpper);
// set HIGH to trigger external analyzer (tested on Dolche Finisar 1Gb GTA)
// The Finisar anaylzer triggers on low-to-high TTL transition
value |= 0x01; // set bit 0
writel( value, IOBaseUpper);
if( Print)
printk( " -GPIO0 set- ");
}
#endif
drivers/scsi/cpqfcTStrigger.h 已删除 100644 → 0
浏览文件 @ 80e23bab
// don't do this unless you have the right hardware!
#define TRIGGERABLE_HBA 0
#if TRIGGERABLE_HBA
void TriggerHBA( void*, int);
#else
#define TriggerHBA(x, y)
#endif
drivers/scsi/cpqfcTSworker.c 已删除 100644 → 0
浏览文件 @ 80e23bab
此差异已折叠。
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