[ARM] 3832/1: iop3xx: coding style cleanup

Since the iop32x code isn't iop321-specific, and the iop33x code isn't
iop331-specfic, do a s/iop321/iop32x/ and s/iop331/iop33x/, and tidy up
the code to conform to the coding style guidelines somewhat better.
Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mach-iop32x/Kconfig

@@ -8,13 +8,14 @@ config ARCH_IQ80321
 	bool "Enable support for IQ80321"
 	help
 	  Say Y here if you want to run your kernel on the Intel IQ80321
-	  evaluation kit for the IOP321 chipset.
+	  evaluation kit for the IOP321 processor.
 
 config ARCH_IQ31244
-	bool "Enable support for IQ31244"
+	bool "Enable support for EP80219/IQ31244"
 	help
-	  Say Y here if you want to run your kernel on the Intel IQ31244
-	  evaluation kit for the IOP321 chipset.
+	  Say Y here if you want to run your kernel on the Intel EP80219
+	  evaluation kit for the Intel 80219 processor (a IOP321 variant)
+	  or the IQ31244 evaluation kit for the IOP321 processor.
 
 endmenu
 

arch/arm/mach-iop32x/iq31244.c

@@ -98,16 +98,16 @@ ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
 	if (slot == 0) {
 		/* CFlash */
-		irq = IRQ_IOP321_XINT1;
+		irq = IRQ_IOP32X_XINT1;
 	} else if (slot == 1) {
 		/* 82551 Pro 100 */
-		irq = IRQ_IOP321_XINT0;
+		irq = IRQ_IOP32X_XINT0;
 	} else if (slot == 2) {
 		/* PCI-X Slot */
-		irq = IRQ_IOP321_XINT3;
+		irq = IRQ_IOP32X_XINT3;
 	} else if (slot == 3) {
 		/* SATA */
-		irq = IRQ_IOP321_XINT2;
+		irq = IRQ_IOP32X_XINT2;
 	} else {
 		printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
 			"device PCI:%d:%d:%d\n", dev->bus->number,
@@ -134,18 +134,18 @@ iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
 	if (slot == 0) {
 		/* CFlash */
-		irq = IRQ_IOP321_XINT1;
+		irq = IRQ_IOP32X_XINT1;
 	} else if (slot == 1) {
 		/* SATA */
-		irq = IRQ_IOP321_XINT2;
+		irq = IRQ_IOP32X_XINT2;
 	} else if (slot == 2) {
 		/* PCI-X Slot */
-		irq = IRQ_IOP321_XINT3;
+		irq = IRQ_IOP32X_XINT3;
 	} else if (slot == 3) {
 		/* 82546 GigE */
-		irq = IRQ_IOP321_XINT0;
+		irq = IRQ_IOP32X_XINT0;
 	} else {
-		printk(KERN_ERR "iq31244_pci_map_irq() called for unknown "
+		printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
 			"device PCI:%d:%d:%d\n", dev->bus->number,
 			PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
 		irq = -1;
@@ -206,7 +206,7 @@ static struct plat_serial8250_port iq31244_serial_port[] = {
 	{
 		.mapbase	= IQ31244_UART,
 		.membase	= (char *)IQ31244_UART,
-		.irq		= IRQ_IOP321_XINT1,
+		.irq		= IRQ_IOP32X_XINT1,
 		.flags		= UPF_SKIP_TEST,
 		.iotype		= UPIO_MEM,
 		.regshift	= 0,
@@ -287,7 +287,7 @@ MACHINE_START(IQ31244, "Intel IQ31244")
 	.io_pg_offst	= ((IQ31244_UART) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
 	.map_io		= iq31244_map_io,
-	.init_irq	= iop321_init_irq,
+	.init_irq	= iop32x_init_irq,
 	.timer		= &iq31244_timer,
 	.init_machine	= iq31244_init_machine,
 MACHINE_END

arch/arm/mach-iop32x/iq80321.c

@@ -78,19 +78,19 @@ iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
 	if ((slot == 2 || slot == 6) && pin == 1) {
 		/* PCI-X Slot INTA */
-		irq = IRQ_IOP321_XINT2;
+		irq = IRQ_IOP32X_XINT2;
 	} else if ((slot == 2 || slot == 6) && pin == 2) {
 		/* PCI-X Slot INTA */
-		irq = IRQ_IOP321_XINT3;
+		irq = IRQ_IOP32X_XINT3;
 	} else if ((slot == 2 || slot == 6) && pin == 3) {
 		/* PCI-X Slot INTA */
-		irq = IRQ_IOP321_XINT0;
+		irq = IRQ_IOP32X_XINT0;
 	} else if ((slot == 2 || slot == 6) && pin == 4) {
 		/* PCI-X Slot INTA */
-		irq = IRQ_IOP321_XINT1;
+		irq = IRQ_IOP32X_XINT1;
 	} else if (slot == 4 || slot == 8) {
 		/* Gig-E */
-		irq = IRQ_IOP321_XINT0;
+		irq = IRQ_IOP32X_XINT0;
 	} else {
 		printk(KERN_ERR "iq80321_pci_map_irq() called for unknown "
 			"device PCI:%d:%d:%d\n", dev->bus->number,
@@ -148,7 +148,7 @@ static struct plat_serial8250_port iq80321_serial_port[] = {
 	{
 		.mapbase	= IQ80321_UART,
 		.membase	= (char *)IQ80321_UART,
-		.irq		= IRQ_IOP321_XINT1,
+		.irq		= IRQ_IOP32X_XINT1,
 		.flags		= UPF_SKIP_TEST,
 		.iotype		= UPIO_MEM,
 		.regshift	= 0,
@@ -187,7 +187,7 @@ MACHINE_START(IQ80321, "Intel IQ80321")
 	.io_pg_offst	= ((IQ80321_UART) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
 	.map_io		= iq80321_map_io,
-	.init_irq	= iop321_init_irq,
+	.init_irq	= iop32x_init_irq,
 	.timer		= &iq80321_timer,
 	.init_machine	= iq80321_init_machine,
 MACHINE_END

arch/arm/mach-iop32x/irq.c

 /*
- * linux/arch/arm/mach-iop32x/irq.c
+ * arch/arm/mach-iop32x/irq.c
  *
  * Generic IOP32X IRQ handling functionality
  *
@@ -9,76 +9,66 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- * Added IOP3XX chipset and IQ80321 board masking code.
- *
  */
+
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
-
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
 #include <asm/hardware.h>
-
 #include <asm/mach-types.h>
 
-static u32 iop321_mask /* = 0 */;
+static u32 iop32x_mask;
 
 static inline void intctl_write(u32 val)
 {
 	iop3xx_cp6_enable();
-	asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
+	asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
 	iop3xx_cp6_disable();
 }
 
 static inline void intstr_write(u32 val)
 {
 	iop3xx_cp6_enable();
-	asm volatile("mcr p6,0,%0,c4,c0,0"::"r" (val));
+	asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
 	iop3xx_cp6_disable();
 }
 
 static void
-iop321_irq_mask (unsigned int irq)
+iop32x_irq_mask(unsigned int irq)
 {
-
-	iop321_mask &= ~(1 << irq);
-
-	intctl_write(iop321_mask);
+	iop32x_mask &= ~(1 << irq);
+	intctl_write(iop32x_mask);
 }
 
 static void
-iop321_irq_unmask (unsigned int irq)
+iop32x_irq_unmask(unsigned int irq)
 {
-	iop321_mask |= (1 << irq);
-
-	intctl_write(iop321_mask);
+	iop32x_mask |= 1 << irq;
+	intctl_write(iop32x_mask);
 }
 
 struct irq_chip ext_chip = {
-	.name	= "IOP",
-	.ack    = iop321_irq_mask,
-	.mask   = iop321_irq_mask,
-	.unmask = iop321_irq_unmask,
+	.name	= "IOP32x",
+	.ack	= iop32x_irq_mask,
+	.mask	= iop32x_irq_mask,
+	.unmask	= iop32x_irq_unmask,
 };
 
-void __init iop321_init_irq(void)
+void __init iop32x_init_irq(void)
 {
-	unsigned int i;
+	int i;
 
-	intctl_write(0);		// disable all interrupts
-	intstr_write(0);		// treat all as IRQ
-	if(machine_is_iq80321() ||
-	   machine_is_iq31244()) 	// all interrupts are inputs to chip
+	intctl_write(0);
+	intstr_write(0);
+	if (machine_is_iq80321() ||
+	    machine_is_iq31244())
 		*IOP3XX_PCIIRSR = 0x0f;
 
-	for(i = 0; i < NR_IRQS; i++)
-	{
+	for (i = 0; i < NR_IRQS; i++) {
 		set_irq_chip(i, &ext_chip);
 		set_irq_handler(i, do_level_IRQ);
 		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-
 	}
 }
-

arch/arm/mach-iop33x/iq80331.c

@@ -61,19 +61,19 @@ iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
 	if (slot == 1 && pin == 1) {
 		/* PCI-X Slot INTA */
-		irq = IRQ_IOP331_XINT1;
+		irq = IRQ_IOP33X_XINT1;
 	} else if (slot == 1 && pin == 2) {
 		/* PCI-X Slot INTB */
-		irq = IRQ_IOP331_XINT2;
+		irq = IRQ_IOP33X_XINT2;
 	} else if (slot == 1 && pin == 3) {
 		/* PCI-X Slot INTC */
-		irq = IRQ_IOP331_XINT3;
+		irq = IRQ_IOP33X_XINT3;
 	} else if (slot == 1 && pin == 4) {
 		/* PCI-X Slot INTD */
-		irq = IRQ_IOP331_XINT0;
+		irq = IRQ_IOP33X_XINT0;
 	} else if (slot == 2) {
 		/* GigE */
-		irq = IRQ_IOP331_XINT2;
+		irq = IRQ_IOP33X_XINT2;
 	} else {
 		printk(KERN_ERR "iq80331_pci_map_irq() called for unknown "
 			"device PCI:%d:%d:%d\n", dev->bus->number,
@@ -142,7 +142,7 @@ MACHINE_START(IQ80331, "Intel IQ80331")
 	.io_pg_offst	= ((0xfffff000) >> 18) & 0xfffc,
 	.boot_params	= 0x00000100,
 	.map_io		= iop3xx_map_io,
-	.init_irq	= iop331_init_irq,
+	.init_irq	= iop33x_init_irq,
 	.timer		= &iq80331_timer,
 	.init_machine	= iq80331_init_machine,
 MACHINE_END

arch/arm/mach-iop33x/iq80332.c

@@ -61,19 +61,19 @@ iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 
 	if (slot == 4 && pin == 1) {
 		/* PCI-X Slot INTA */
-		irq = IRQ_IOP331_XINT0;
+		irq = IRQ_IOP33X_XINT0;
 	} else if (slot == 4 && pin == 2) {
 		/* PCI-X Slot INTB */
-		irq = IRQ_IOP331_XINT1;
+		irq = IRQ_IOP33X_XINT1;
 	} else if (slot == 4 && pin == 3) {
 		/* PCI-X Slot INTC */
-		irq = IRQ_IOP331_XINT2;
+		irq = IRQ_IOP33X_XINT2;
 	} else if (slot == 4 && pin == 4) {
 		/* PCI-X Slot INTD */
-		irq = IRQ_IOP331_XINT3;
+		irq = IRQ_IOP33X_XINT3;
 	} else if (slot == 6) {
 		/* GigE */
-		irq = IRQ_IOP331_XINT2;
+		irq = IRQ_IOP33X_XINT2;
 	} else {
 		printk(KERN_ERR "iq80332_pci_map_irq() called for unknown "
 			"device PCI:%d:%d:%d\n", dev->bus->number,
@@ -142,7 +142,7 @@ MACHINE_START(IQ80332, "Intel IQ80332")
 	.io_pg_offst	= ((0xfffff000) >> 18) & 0xfffc,
 	.boot_params	= 0x00000100,
 	.map_io		= iop3xx_map_io,
-	.init_irq	= iop331_init_irq,
+	.init_irq	= iop33x_init_irq,
 	.timer		= &iq80332_timer,
 	.init_machine	= iq80332_init_machine,
 MACHINE_END

arch/arm/mach-iop33x/irq.c

 /*
- * linux/arch/arm/mach-iop33x/irq.c
+ * arch/arm/mach-iop33x/irq.c
  *
  * Generic IOP331 IRQ handling functionality
  *
@@ -9,51 +9,44 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- *
  */
+
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/list.h>
-
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
 #include <asm/hardware.h>
-
 #include <asm/mach-types.h>
 
-static u32 iop331_mask0 = 0;
-static u32 iop331_mask1 = 0;
+static u32 iop33x_mask0;
+static u32 iop33x_mask1;
 
-static inline void intctl_write0(u32 val)
+static inline void intctl0_write(u32 val)
 {
-    // INTCTL0
 	iop3xx_cp6_enable();
-	asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
+	asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
 	iop3xx_cp6_disable();
 }
 
-static inline void intctl_write1(u32 val)
+static inline void intctl1_write(u32 val)
 {
-    // INTCTL1
 	iop3xx_cp6_enable();
-    asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
+	asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
 	iop3xx_cp6_disable();
 }
 
-static inline void intstr_write0(u32 val)
+static inline void intstr0_write(u32 val)
 {
-    // INTSTR0
 	iop3xx_cp6_enable();
-	asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
+	asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
 	iop3xx_cp6_disable();
 }
 
-static inline void intstr_write1(u32 val)
+static inline void intstr1_write(u32 val)
 {
-    // INTSTR1
 	iop3xx_cp6_enable();
-	asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
+	asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
 	iop3xx_cp6_disable();
 }
 
@@ -72,65 +65,63 @@ static inline void intsize_write(u32 val)
 }
 
 static void
-iop331_irq_mask1 (unsigned int irq)
+iop33x_irq_mask1 (unsigned int irq)
 {
-        iop331_mask0 &= ~(1 << irq);
-        intctl_write0(iop331_mask0);
+	iop33x_mask0 &= ~(1 << irq);
+	intctl0_write(iop33x_mask0);
 }
 
 static void
-iop331_irq_mask2 (unsigned int irq)
+iop33x_irq_mask2 (unsigned int irq)
 {
-        iop331_mask1 &= ~(1 << (irq - 32));
-        intctl_write1(iop331_mask1);
+	iop33x_mask1 &= ~(1 << (irq - 32));
+	intctl1_write(iop33x_mask1);
 }
 
 static void
-iop331_irq_unmask1(unsigned int irq)
+iop33x_irq_unmask1(unsigned int irq)
 {
-        iop331_mask0 |= (1 << irq);
-        intctl_write0(iop331_mask0);
+	iop33x_mask0 |= 1 << irq;
+	intctl0_write(iop33x_mask0);
 }
 
 static void
-iop331_irq_unmask2(unsigned int irq)
+iop33x_irq_unmask2(unsigned int irq)
 {
-        iop331_mask1 |= (1 << (irq - 32));
-        intctl_write1(iop331_mask1);
+	iop33x_mask1 |= (1 << (irq - 32));
+	intctl1_write(iop33x_mask1);
 }
 
-struct irq_chip iop331_irqchip1 = {
-	.name	= "IOP-1",
-	.ack    = iop331_irq_mask1,
-	.mask   = iop331_irq_mask1,
-	.unmask = iop331_irq_unmask1,
+struct irq_chip iop33x_irqchip1 = {
+	.name	= "IOP33x-1",
+	.ack	= iop33x_irq_mask1,
+	.mask	= iop33x_irq_mask1,
+	.unmask	= iop33x_irq_unmask1,
 };
 
-struct irq_chip iop331_irqchip2 = {
-	.name	= "IOP-2",
-	.ack    = iop331_irq_mask2,
-	.mask   = iop331_irq_mask2,
-	.unmask = iop331_irq_unmask2,
+struct irq_chip iop33x_irqchip2 = {
+	.name	= "IOP33x-2",
+	.ack	= iop33x_irq_mask2,
+	.mask	= iop33x_irq_mask2,
+	.unmask	= iop33x_irq_unmask2,
 };
 
-void __init iop331_init_irq(void)
+void __init iop33x_init_irq(void)
 {
-	unsigned int i;
+	int i;
 
-	intctl_write0(0);		// disable all interrupts
-    	intctl_write1(0);
-	intstr_write0(0);		// treat all as IRQ
-    	intstr_write1(0);
+	intctl0_write(0);
+	intctl1_write(0);
+	intstr0_write(0);
+	intstr1_write(0);
 	intbase_write(0);
 	intsize_write(1);
-	if(machine_is_iq80331()) 	// all interrupts are inputs to chip
+	if (machine_is_iq80331())
 		*IOP3XX_PCIIRSR = 0x0f;
 
-	for(i = 0; i < NR_IRQS; i++)
-	{
-		set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
+	for (i = 0; i < NR_IRQS; i++) {
+		set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
 		set_irq_handler(i, do_level_IRQ);
 		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 	}
 }
-

arch/arm/mach-iop33x/uart.c

 /*
- * linux/arch/arm/mach-iop33x/uart.c
+ * arch/arm/mach-iop33x/uart.c
  *
  * Author: Dave Jiang (dave.jiang@intel.com)
  * Copyright (C) 2004 Intel Corporation.
@@ -17,7 +17,6 @@
 #include <linux/serial.h>
 #include <linux/tty.h>
 #include <linux/serial_8250.h>
-
 #include <asm/io.h>
 #include <asm/pgtable.h>
 #include <asm/page.h>
@@ -30,14 +29,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#define IOP331_UART_XTAL 33334000
+#define IOP33X_UART_XTAL 33334000
 
 static struct plat_serial8250_port iop33x_uart0_data[] = {
 	{
-		.membase	= (char *)IOP331_UART0_VIRT,
-		.mapbase	= IOP331_UART0_PHYS,
-		.irq		= IRQ_IOP331_UART0,
-		.uartclk	= IOP331_UART_XTAL,
+		.membase	= (char *)IOP33X_UART0_VIRT,
+		.mapbase	= IOP33X_UART0_PHYS,
+		.irq		= IRQ_IOP33X_UART0,
+		.uartclk	= IOP33X_UART_XTAL,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM,
 		.flags		= UPF_SKIP_TEST,
@@ -47,13 +46,13 @@ static struct plat_serial8250_port iop33x_uart0_data[] = {
 
 static struct resource iop33x_uart0_resources[] = {
 	[0] = {
-		.start	= IOP331_UART0_PHYS,
-		.end	= IOP331_UART0_PHYS + 0x3f,
+		.start	= IOP33X_UART0_PHYS,
+		.end	= IOP33X_UART0_PHYS + 0x3f,
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= IRQ_IOP331_UART0,
-		.end	= IRQ_IOP331_UART0,
+		.start	= IRQ_IOP33X_UART0,
+		.end	= IRQ_IOP33X_UART0,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
@@ -71,23 +70,23 @@ struct platform_device iop33x_uart0_device = {
 
 static struct resource iop33x_uart1_resources[] = {
 	[0] = {
-		.start	= IOP331_UART1_PHYS,
-		.end	= IOP331_UART1_PHYS + 0x3f,
+		.start	= IOP33X_UART1_PHYS,
+		.end	= IOP33X_UART1_PHYS + 0x3f,
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= IRQ_IOP331_UART1,
-		.end	= IRQ_IOP331_UART1,
+		.start	= IRQ_IOP33X_UART1,
+		.end	= IRQ_IOP33X_UART1,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 
 static struct plat_serial8250_port iop33x_uart1_data[] = {
 	{
-		.membase	= (char *)IOP331_UART1_VIRT,
-		.mapbase	= IOP331_UART1_PHYS,
-		.irq		= IRQ_IOP331_UART1,
-		.uartclk	= IOP331_UART_XTAL,
+		.membase	= (char *)IOP33X_UART1_VIRT,
+		.mapbase	= IOP33X_UART1_PHYS,
+		.irq		= IRQ_IOP33X_UART1,
+		.uartclk	= IOP33X_UART_XTAL,
 		.regshift	= 2,
 		.iotype		= UPIO_MEM,
 		.flags		= UPF_SKIP_TEST,

arch/arm/oprofile/op_model_xscale.c

@@ -37,10 +37,10 @@
 #define XSCALE_PMU_IRQ  IRQ_XS80200_PMU
 #endif
 #ifdef CONFIG_ARCH_IOP32X
-#define XSCALE_PMU_IRQ  IRQ_IOP321_CORE_PMU
+#define XSCALE_PMU_IRQ  IRQ_IOP32X_CORE_PMU
 #endif
 #ifdef CONFIG_ARCH_IOP33X
-#define XSCALE_PMU_IRQ  IRQ_IOP331_CORE_PMU
+#define XSCALE_PMU_IRQ  IRQ_IOP33X_CORE_PMU
 #endif
 #ifdef CONFIG_ARCH_PXA
 #define XSCALE_PMU_IRQ  IRQ_PMU
@@ -88,7 +88,7 @@ static struct pmu_counter results[MAX_COUNTERS];
 /*
  * There are two versions of the PMU in current XScale processors
  * with differing register layouts and number of performance counters.
- * e.g. IOP321 is xsc1 whilst IOP331 is xsc2.
+ * e.g. IOP32x is xsc1 whilst IOP33x is xsc2.
  * We detect which register layout to use in xscale_detect_pmu()
  */
 enum { PMU_XSC1, PMU_XSC2 };

arch/arm/plat-iop/i2c.c

@@ -31,12 +31,12 @@
 #include <asm/mach/arch.h>
 
 #ifdef CONFIG_ARCH_IOP32X
-#define IRQ_IOP3XX_I2C_0	IRQ_IOP321_I2C_0
-#define IRQ_IOP3XX_I2C_1	IRQ_IOP321_I2C_1
+#define IRQ_IOP3XX_I2C_0	IRQ_IOP32X_I2C_0
+#define IRQ_IOP3XX_I2C_1	IRQ_IOP32X_I2C_1
 #endif
 #ifdef CONFIG_ARCH_IOP33X
-#define IRQ_IOP3XX_I2C_0	IRQ_IOP331_I2C_0
-#define IRQ_IOP3XX_I2C_1	IRQ_IOP331_I2C_1
+#define IRQ_IOP3XX_I2C_0	IRQ_IOP33X_I2C_0
+#define IRQ_IOP3XX_I2C_1	IRQ_IOP33X_I2C_1
 #endif
 
 static struct resource iop3xx_i2c0_resources[] = {

arch/arm/plat-iop/time.c

@@ -26,10 +26,10 @@
 #include <asm/mach/time.h>
 
 #ifdef CONFIG_ARCH_IOP32X
-#define IRQ_IOP3XX_TIMER0	IRQ_IOP321_TIMER0
+#define IRQ_IOP3XX_TIMER0	IRQ_IOP32X_TIMER0
 #else
 #ifdef CONFIG_ARCH_IOP33X
-#define IRQ_IOP3XX_TIMER0	IRQ_IOP331_TIMER0
+#define IRQ_IOP3XX_TIMER0	IRQ_IOP33X_TIMER0
 #endif
 #endif
 

include/asm-arm/arch-iop32x/debug-macro.S

-/* linux/include/asm-arm/arch-iop32x/debug-macro.S
+/*
+ * include/asm-arm/arch-iop32x/debug-macro.S
  *
  * Debugging macro include header
  *
@@ -8,11 +9,10 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
-*/
+ */
 
-		.macro	addruart,rx
-		mov	\rx, #0xfe000000	@ physical
+		.macro	addruart, rx
+		mov	\rx, #0xfe000000	@ physical as well as virtual
 		orr	\rx, \rx, #0x00800000	@ location of the UART
 		.endm
 

include/asm-arm/arch-iop32x/dma.h

 /*
- * linux/include/asm-arm/arch-iop32x/dma.h
+ * include/asm-arm/arch-iop32x/dma.h
  *
  * Copyright (C) 2004 Intel Corp.
  *

include/asm-arm/arch-iop32x/entry-macro.S

@@ -7,14 +7,11 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <asm/arch/irqs.h>
+#include <asm/arch/iop32x.h>
 
 		.macro	disable_fiq
 		.endm
 
-		/*
-		 * Note: only deal with normal interrupts, not FIQ
-		 */
 		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 		ldr	\base, =IOP3XX_REG_ADDR(0x07D8)
 		ldr	\irqstat, [\base]		@ Read IINTSRC

include/asm-arm/arch-iop32x/hardware.h

 /*
- * linux/include/asm-arm/arch-iop32x/hardware.h
+ * include/asm-arm/arch-iop32x/hardware.h
  */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __HARDWARE_H
+#define __HARDWARE_H
 
 #include <asm/types.h>
 
@@ -15,19 +16,21 @@
  * The PCI IO space is located at virtual 0xfe000000 from physical
  * 0x90000000. The PCI BARs must be programmed with physical addresses,
  * but when we read them, we convert them to virtual addresses. See
- * arch/arm/mach-iop3xx/iop3xx-pci.c
+ * arch/arm/plat-iop/pci.c.
  */
-
 #define pcibios_assign_all_busses() 1
 #define PCIBIOS_MIN_IO		0x00000000
 #define PCIBIOS_MIN_MEM		0x00000000
 
+#ifndef __ASSEMBLY__
+void iop32x_init_irq(void);
+#endif
+
 
 /*
  * Generic chipset bits
- *
  */
-#include "iop321.h"
+#include "iop32x.h"
 
 /*
  * Board specific bits
@@ -35,4 +38,5 @@
 #include "iq80321.h"
 #include "iq31244.h"
 
-#endif  /* _ASM_ARCH_HARDWARE_H */
+
+#endif

include/asm-arm/arch-iop32x/io.h

 /*
- * linux/include/asm-arm/arch-iop32x/io.h
+ * include/asm-arm/arch-iop32x/io.h
  *
  * Copyright (C) 2001 MontaVista Software, Inc.
  *
@@ -8,8 +8,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
+#ifndef __IO_H
+#define __IO_H
 
 #include <asm/hardware.h>
 
@@ -18,4 +18,5 @@
 #define __io(p)			((void __iomem *)(p))
 #define __mem_pci(a)		(a)
 
+
 #endif

include/asm-arm/arch-iop32x/iop321.h

-/*
- * linux/include/asm/arch-iop32x/iop321.h
- *
- * Intel IOP321 Chip definitions
- *
- * Author: Rory Bolt <rorybolt@pacbell.net>
- * Copyright (C) 2002 Rory Bolt
- * Copyright (C) 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _IOP321_HW_H_
-#define _IOP321_HW_H_
-
-
-/*
- * This is needed for mixed drivers that need to work on all
- * IOP3xx variants but behave slightly differently on each.
- */
-#ifndef __ASSEMBLY__
-#define iop_is_321()		1
-#endif
-
-/*
- * IOP321 chipset registers
- */
-#define IOP321_VIRT_MEM_BASE 0xfeffe000  /* chip virtual mem address*/
-#define IOP321_PHYS_MEM_BASE 0xffffe000  /* chip physical memory address */
-#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
-
-/* Reserved 0x00000000 through 0x000000FF */
-
-/* Address Translation Unit 0x00000100 through 0x000001FF */
-
-/* Messaging Unit 0x00000300 through 0x000003FF */
-
-/* DMA Controller 0x00000400 through 0x000004FF */
-
-/* Memory controller 0x00000500 through 0x0005FF */
-
-/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
-
-/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
-
-/* Internal arbitration unit 0x00000780 through 0x0007BF */
-#define IOP321_IACR	(volatile u32 *)IOP321_REG_ADDR(0x00000780)
-#define IOP321_MTTR1	(volatile u32 *)IOP321_REG_ADDR(0x00000784)
-#define IOP321_MTTR2	(volatile u32 *)IOP321_REG_ADDR(0x00000788)
-
-/* General Purpose I/O Registers */
-#define IOP321_GPOE       (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
-#define IOP321_GPID       (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
-#define IOP321_GPOD       (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
-
-/* Interrupt Controller */
-#define IOP321_INTCTL     (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
-#define IOP321_INTSTR     (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
-#define IOP321_IINTSRC    (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
-#define IOP321_FINTSRC    (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
-
-/* Application accelerator unit 0x00000800 - 0x000008FF */
-
-/* SSP serial port unit 0x00001600 - 0x0000167F */
-/* I2C bus interface unit 0x00001680 - 0x000016FF */
-
-/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
-
-/*
- * Peripherals that are shared between the iop32x and iop33x but
- * located at different addresses.
- */
-#define IOP3XX_GPIO_REG(reg)   (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg))
-#define IOP3XX_TIMER_REG(reg)  (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
-
-#include <asm/hardware/iop3xx.h>
-
-
-#ifndef __ASSEMBLY__
-extern void iop321_init_irq(void);
-extern void iop321_time_init(void);
-#endif
-
-#endif // _IOP321_HW_H_

include/asm-arm/arch-iop32x/iop32x.h

+/*
+ * include/asm-arm/arch-iop32x/iop32x.h
+ *
+ * Intel IOP32X Chip definitions
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IOP32X_H
+#define __IOP32X_H
+
+/*
+ * Peripherals that are shared between the iop32x and iop33x but
+ * located at different addresses.
+ */
+#define IOP3XX_GPIO_REG(reg)	(IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg))
+#define IOP3XX_TIMER_REG(reg)	(IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
+
+#include <asm/hardware/iop3xx.h>
+
+
+#endif

include/asm-arm/arch-iop32x/iq31244.h

 /*
- * linux/include/asm/arch-iop32x/iq31244.h
+ * include/asm-arm/arch-iop32x/iq31244.h
  *
  * Intel IQ31244 evaluation board registers
  */
 
-#ifndef _IQ31244_H_
-#define _IQ31244_H_
+#ifndef __IQ31244_H
+#define __IQ31244_H
 
 #define IQ31244_UART		0xfe800000	/* UART #1 */
 #define IQ31244_7SEG_1		0xfe840000	/* 7-Segment MSB */
@@ -14,4 +14,4 @@
 #define IQ31244_BATT_STAT	0xfe8f0000	/* Battery Status */
 
 
-#endif	// _IQ31244_H_
+#endif

include/asm-arm/arch-iop32x/iq80321.h

 /*
- * linux/include/asm/arch-iop32x/iq80321.h
+ * include/asm-arm/arch-iop32x/iq80321.h
  *
  * Intel IQ80321 evaluation board registers
  */
 
-#ifndef _IQ80321_H_
-#define _IQ80321_H_
+#ifndef __IQ80321_H
+#define __IQ80321_H
 
 #define IQ80321_UART		0xfe800000	/* UART #1 */
 #define IQ80321_7SEG_1		0xfe840000	/* 7-Segment MSB */
@@ -14,4 +14,4 @@
 #define IQ80321_BATT_STAT	0xfe8f0000	/* Battery Status */
 
 
-#endif	// _IQ80321_H_
+#endif

include/asm-arm/arch-iop32x/irqs.h

 /*
- * linux/include/asm-arm/arch-iop32x/irqs.h
+ * include/asm-arm/arch-iop32x/irqs.h
  *
  * Author:	Rory Bolt <rorybolt@pacbell.net>
  * Copyright:	(C) 2002 Rory Bolt
@@ -7,44 +7,44 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
  */
-#ifndef _IRQS_H_
-#define _IRQS_H_
+
+#ifndef __IRQS_H
+#define __IRQS_H
 
 /*
  * IOP80321 chipset interrupts
  */
-#define IRQ_IOP321_DMA0_EOT	0
-#define IRQ_IOP321_DMA0_EOC	1
-#define IRQ_IOP321_DMA1_EOT	2
-#define IRQ_IOP321_DMA1_EOC	3
-#define IRQ_IOP321_AA_EOT	6
-#define IRQ_IOP321_AA_EOC	7
-#define IRQ_IOP321_CORE_PMON	8
-#define IRQ_IOP321_TIMER0	9
-#define IRQ_IOP321_TIMER1	10
-#define IRQ_IOP321_I2C_0	11
-#define IRQ_IOP321_I2C_1	12
-#define IRQ_IOP321_MESSAGING	13
-#define IRQ_IOP321_ATU_BIST	14
-#define IRQ_IOP321_PERFMON	15
-#define IRQ_IOP321_CORE_PMU	16
-#define IRQ_IOP321_BIU_ERR	17
-#define IRQ_IOP321_ATU_ERR	18
-#define IRQ_IOP321_MCU_ERR	19
-#define IRQ_IOP321_DMA0_ERR	20
-#define IRQ_IOP321_DMA1_ERR	21
-#define IRQ_IOP321_AA_ERR	23
-#define IRQ_IOP321_MSG_ERR	24
-#define IRQ_IOP321_SSP		25
-#define IRQ_IOP321_XINT0	27
-#define IRQ_IOP321_XINT1	28
-#define IRQ_IOP321_XINT2	29
-#define IRQ_IOP321_XINT3	30
-#define IRQ_IOP321_HPI		31
+#define IRQ_IOP32X_DMA0_EOT	0
+#define IRQ_IOP32X_DMA0_EOC	1
+#define IRQ_IOP32X_DMA1_EOT	2
+#define IRQ_IOP32X_DMA1_EOC	3
+#define IRQ_IOP32X_AA_EOT	6
+#define IRQ_IOP32X_AA_EOC	7
+#define IRQ_IOP32X_CORE_PMON	8
+#define IRQ_IOP32X_TIMER0	9
+#define IRQ_IOP32X_TIMER1	10
+#define IRQ_IOP32X_I2C_0	11
+#define IRQ_IOP32X_I2C_1	12
+#define IRQ_IOP32X_MESSAGING	13
+#define IRQ_IOP32X_ATU_BIST	14
+#define IRQ_IOP32X_PERFMON	15
+#define IRQ_IOP32X_CORE_PMU	16
+#define IRQ_IOP32X_BIU_ERR	17
+#define IRQ_IOP32X_ATU_ERR	18
+#define IRQ_IOP32X_MCU_ERR	19
+#define IRQ_IOP32X_DMA0_ERR	20
+#define IRQ_IOP32X_DMA1_ERR	21
+#define IRQ_IOP32X_AA_ERR	23
+#define IRQ_IOP32X_MSG_ERR	24
+#define IRQ_IOP32X_SSP		25
+#define IRQ_IOP32X_XINT0	27
+#define IRQ_IOP32X_XINT1	28
+#define IRQ_IOP32X_XINT2	29
+#define IRQ_IOP32X_XINT3	30
+#define IRQ_IOP32X_HPI		31
 
 #define NR_IRQS			32
 
 
-#endif // _IRQ_H_
+#endif

include/asm-arm/arch-iop32x/memory.h

 /*
- * linux/include/asm-arm/arch-iop32x/memory.h
+ * include/asm-arm/arch-iop32x/memory.h
  */
 
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
+#ifndef __MEMORY_H
+#define __MEMORY_H
 
 #include <asm/hardware.h>
 
@@ -19,7 +19,6 @@
  * bus_to_virt: Used to convert an address for DMA operations
  *		to an address that the kernel can use.
  */
-
 #define __virt_to_bus(x)	(((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
 #define __bus_to_virt(x)	(__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
 

include/asm-arm/arch-iop32x/system.h

 /*
- * linux/include/asm-arm/arch-iop32x/system.h
+ * include/asm-arm/arch-iop32x/system.h
  *
  * Copyright (C) 2001 MontaVista Software, Inc.
  *
@@ -13,17 +13,10 @@ static inline void arch_idle(void)
 	cpu_do_idle();
 }
 
-
 static inline void arch_reset(char mode)
 {
 	*IOP3XX_PCSR = 0x30;
 
-	if ( 1 && mode == 's') {
 	/* Jump into ROM at address 0 */
 	cpu_reset(0);
-	} else {
-		/* No on-chip reset capability */
-		cpu_reset(0);
-	}
 }
-

include/asm-arm/arch-iop32x/timex.h

 /*
- * linux/include/asm-arm/arch-iop32x/timex.h
+ * include/asm-arm/arch-iop32x/timex.h
  *
- * IOP3xx architecture timex specifications
+ * IOP32x architecture timex specifications
  */
+
 #include <asm/hardware.h>
 
 #define CLOCK_TICK_RATE		(100 * HZ)

include/asm-arm/arch-iop32x/uncompress.h

 /*
- *  linux/include/asm-arm/arch-iop32x/uncompress.h
+ * include/asm-arm/arch-iop32x/uncompress.h
  */
+
 #include <asm/types.h>
 #include <asm/mach-types.h>
 #include <linux/serial_reg.h>
@@ -8,13 +9,13 @@
 
 static volatile u8 *uart_base;
 
-#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
+#define TX_DONE		(UART_LSR_TEMT | UART_LSR_THRE)
 
 static inline void putc(char c)
 {
 	while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
 		barrier();
-	*uart_base = c;
+	uart_base[UART_TX] = c;
 }
 
 static inline void flush(void)

include/asm-arm/arch-iop32x/vmalloc.h

 /*
- * linux/include/asm-arm/arch-iop32x/vmalloc.h
+ * include/asm-arm/arch-iop32x/vmalloc.h
  */
 
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-//#define VMALLOC_END       (0xe8000000)
-/* increase usable physical RAM to ~992M per RMK */
-#define VMALLOC_END       (0xfe000000)
-
+#define VMALLOC_END	0xfe000000

include/asm-arm/arch-iop33x/debug-macro.S

-/* linux/include/asm-arm/arch-iop33x/debug-macro.S
+/*
+ * include/asm-arm/arch-iop33x/debug-macro.S
  *
  * Debugging macro include header
  *
@@ -8,10 +9,9 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
-*/
+ */
 
-		.macro	addruart,rx
+		.macro	addruart, rx
 		mrc	p15, 0, \rx, c1, c0
 		tst	\rx, #1			@ mmu enabled?
 		moveq	\rx, #0xff000000	@ physical

include/asm-arm/arch-iop33x/dma.h

 /*
- * linux/include/asm-arm/arch-iop33x/dma.h
+ * include/asm-arm/arch-iop33x/dma.h
  *
  * Copyright (C) 2004 Intel Corp.
  *

include/asm-arm/arch-iop33x/entry-macro.S

@@ -7,7 +7,7 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <asm/arch/irqs.h>
+#include <asm/arch/iop33x.h>
 
 		.macro	disable_fiq
 		.endm

include/asm-arm/arch-iop33x/hardware.h

 /*
- * linux/include/asm-arm/arch-iop33x/hardware.h
+ * include/asm-arm/arch-iop33x/hardware.h
  */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __HARDWARE_H
+#define __HARDWARE_H
 
 #include <asm/types.h>
 
@@ -15,14 +16,15 @@
  * The PCI IO space is located at virtual 0xfe000000 from physical
  * 0x90000000.  The PCI BARs must be programmed with physical addresses,
  * but when we read them, we convert them to virtual addresses.  See
- * arch/arm/mach-iop33x/pci.c
+ * arch/arm/mach-iop3xx/iop3xx-pci.c
  */
-
 #define pcibios_assign_all_busses()	1
 #define PCIBIOS_MIN_IO		0x00000000
 #define PCIBIOS_MIN_MEM		0x00000000
 
 #ifndef __ASSEMBLY__
+void iop33x_init_irq(void);
+
 extern struct platform_device iop33x_uart0_device;
 extern struct platform_device iop33x_uart1_device;
 #endif
@@ -32,7 +34,7 @@ extern struct platform_device iop33x_uart1_device;
  * Generic chipset bits
  *
  */
-#include "iop331.h"
+#include "iop33x.h"
 
 /*
  * Board specific bits
@@ -40,4 +42,5 @@ extern struct platform_device iop33x_uart1_device;
 #include "iq80331.h"
 #include "iq80332.h"
 
-#endif  /* _ASM_ARCH_HARDWARE_H */
+
+#endif

include/asm-arm/arch-iop33x/io.h

 /*
- * linux/include/asm-arm/arch-iop33x/io.h
+ * include/asm-arm/arch-iop33x/io.h
  *
  * Copyright (C) 2001  MontaVista Software, Inc.
  *
@@ -8,14 +8,14 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
+#ifndef __IO_H
+#define __IO_H
 
 #include <asm/hardware.h>
 
 #define IO_SPACE_LIMIT		0xffffffff
-
 #define __io(p)			((void __iomem *)(p))
 #define __mem_pci(a)		(a)
 
+
 #endif

include/asm-arm/arch-iop33x/iop331.h

-/*
- * linux/include/asm/arch-iop33x/iop331.h
- *
- * Intel IOP331 Chip definitions
- *
- * Author: Dave Jiang (dave.jiang@intel.com)
- * Copyright (C) 2003, 2004 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _IOP331_HW_H_
-#define _IOP331_HW_H_
-
-
-/*
- * This is needed for mixed drivers that need to work on all
- * IOP3xx variants but behave slightly differently on each.
- */
-#ifndef __ASSEMBLY__
-#define	iop_is_331()		1
-#endif
-
-/*
- * IOP331 chipset registers
- */
-#define IOP331_VIRT_MEM_BASE  0xfeffe000  /* chip virtual mem address*/
-#define IOP331_PHYS_MEM_BASE  0xffffe000  /* chip physical memory address */
-#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
-
-/* Reserved 0x00000000 through 0x000000FF */
-
-/* Address Translation Unit 0x00000100 through 0x000001FF */
-
-/* Messaging Unit 0x00000300 through 0x000003FF */
-
-/* DMA Controller 0x00000400 through 0x000004FF */
-
-/* Memory controller 0x00000500 through 0x0005FF */
-
-/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
-
-/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
-/* Internal arbitration unit 0x00000780 through 0x0007BF */
-
-/* Interrupt Controller */
-#define IOP331_INTCTL0    (volatile u32 *)IOP331_REG_ADDR(0x00000790)
-#define IOP331_INTCTL1    (volatile u32 *)IOP331_REG_ADDR(0x00000794)
-#define IOP331_INTSTR0    (volatile u32 *)IOP331_REG_ADDR(0x00000798)
-#define IOP331_INTSTR1    (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
-#define IOP331_IINTSRC0   (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
-#define IOP331_IINTSRC1   (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
-#define IOP331_FINTSRC0   (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
-#define IOP331_FINTSRC1   (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
-#define IOP331_IPR0       (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
-#define IOP331_IPR1       (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
-#define IOP331_IPR2       (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
-#define IOP331_IPR3       (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
-#define IOP331_INTBASE    (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
-#define IOP331_INTSIZE    (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
-#define IOP331_IINTVEC    (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
-#define IOP331_FINTVEC    (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
-
-
-/* Application accelerator unit 0x00000800 - 0x000008FF */
-
-#define IOP331_SPDSCR	  (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
-#define IOP331_PPDSCR	  (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
-/* SSP serial port unit 0x00001600 - 0x0000167F */
-
-/* I2C bus interface unit 0x00001680 - 0x000016FF */
-
-/* 0x00001700 through 0x0000172C  UART 0 */
-
-/* Reserved 0x00001730 through 0x0000173F */
-
-/* 0x00001740 through 0x0000176C UART 1 */
-
-#define IOP331_UART0_PHYS  (IOP331_PHYS_MEM_BASE | 0x00001700)	/* UART #1 physical */
-#define IOP331_UART1_PHYS  (IOP331_PHYS_MEM_BASE | 0x00001740)	/* UART #2 physical */
-#define IOP331_UART0_VIRT  (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
-#define IOP331_UART1_VIRT  (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
-
-/* Reserved 0x00001770 through 0x0000177F */
-
-/* General Purpose I/O Registers */
-#define IOP331_GPOE       (volatile u32 *)IOP331_REG_ADDR(0x00001780)
-#define IOP331_GPID       (volatile u32 *)IOP331_REG_ADDR(0x00001784)
-#define IOP331_GPOD       (volatile u32 *)IOP331_REG_ADDR(0x00001788)
-
-/* Reserved 0x0000178c through 0x000019ff */
-
-/*
- * Peripherals that are shared between the iop32x and iop33x but
- * located at different addresses.
- */
-#define IOP3XX_GPIO_REG(reg)   (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
-#define IOP3XX_TIMER_REG(reg)  (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
-
-#include <asm/hardware/iop3xx.h>
-
-
-#ifndef __ASSEMBLY__
-extern void iop331_init_irq(void);
-extern void iop331_time_init(void);
-#endif
-
-#endif // _IOP331_HW_H_

include/asm-arm/arch-iop33x/iop33x.h

+/*
+ * include/asm-arm/arch-iop33x/iop33x.h
+ *
+ * Intel IOP33X Chip definitions
+ *
+ * Author: Dave Jiang (dave.jiang@intel.com)
+ * Copyright (C) 2003, 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __IOP33X_H
+#define __IOP33X_H
+
+/*
+ * Peripherals that are shared between the iop32x and iop33x but
+ * located at different addresses.
+ */
+#define IOP3XX_GPIO_REG(reg)	(IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
+#define IOP3XX_TIMER_REG(reg)	(IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
+
+#include <asm/hardware/iop3xx.h>
+
+/* UARTs  */
+#define IOP33X_UART0_PHYS	(IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
+#define IOP33X_UART0_VIRT	(IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
+#define IOP33X_UART1_PHYS	(IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
+#define IOP33X_UART1_VIRT	(IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
+
+
+#endif

include/asm-arm/arch-iop33x/iq80331.h

 /*
- * linux/include/asm/arch-iop33x/iq80331.h
+ * include/asm-arm/arch-iop33x/iq80331.h
  *
  * Intel IQ80331 evaluation board registers
  */
 
-#ifndef _IQ80331_H_
-#define _IQ80331_H_
+#ifndef __IQ80331_H
+#define __IQ80331_H
 
 #define IQ80331_7SEG_1		0xce840000	/* 7-Segment MSB */
 #define IQ80331_7SEG_0		0xce850000	/* 7-Segment LSB (WO) */
@@ -13,4 +13,4 @@
 #define IQ80331_BATT_STAT	0xce8f0000	/* Battery Status */
 
 
-#endif	// _IQ80331_H_
+#endif

include/asm-arm/arch-iop33x/iq80332.h

 /*
- * linux/include/asm/arch-iop33x/iq80332.h
+ * include/asm-arm/arch-iop33x/iq80332.h
  *
  * Intel IQ80332 evaluation board registers
  */
 
-#ifndef _IQ80332_H_
-#define _IQ80332_H_
+#ifndef __IQ80332_H
+#define __IQ80332_H
 
 #define IQ80332_7SEG_1		0xce840000	/* 7-Segment MSB */
 #define IQ80332_7SEG_0		0xce850000	/* 7-Segment LSB (WO) */
@@ -13,4 +13,4 @@
 #define IQ80332_BATT_STAT	0xce8f0000	/* Battery Status */
 
 
-#endif	// _IQ80332_H_
+#endif

include/asm-arm/arch-iop33x/irqs.h

 /*
- * linux/include/asm-arm/arch-iop33x/irqs.h
+ * include/asm-arm/arch-iop33x/irqs.h
  *
  * Author:	Dave Jiang (dave.jiang@intel.com)
  * Copyright:	(C) 2003 Intel Corp.
@@ -7,54 +7,54 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
  */
-#ifndef _IRQS_H_
-#define _IRQS_H_
+
+#ifndef __IRQS_H
+#define __IRQS_H
 
 /*
  * IOP80331 chipset interrupts
  */
-#define IRQ_IOP331_DMA0_EOT	0
-#define IRQ_IOP331_DMA0_EOC	1
-#define IRQ_IOP331_DMA1_EOT	2
-#define IRQ_IOP331_DMA1_EOC	3
-#define IRQ_IOP331_AA_EOT	6
-#define IRQ_IOP331_AA_EOC	7
-#define IRQ_IOP331_TIMER0	8
-#define IRQ_IOP331_TIMER1	9
-#define IRQ_IOP331_I2C_0	10
-#define IRQ_IOP331_I2C_1	11
-#define IRQ_IOP331_MSG		12
-#define IRQ_IOP331_MSGIBQ	13
-#define IRQ_IOP331_ATU_BIST	14
-#define IRQ_IOP331_PERFMON	15
-#define IRQ_IOP331_CORE_PMU	16
-#define IRQ_IOP331_XINT0	24
-#define IRQ_IOP331_XINT1	25
-#define IRQ_IOP331_XINT2	26
-#define IRQ_IOP331_XINT3	27
-#define IRQ_IOP331_XINT8	32
-#define IRQ_IOP331_XINT9	33
-#define IRQ_IOP331_XINT10	34
-#define IRQ_IOP331_XINT11	35
-#define IRQ_IOP331_XINT12	36
-#define IRQ_IOP331_XINT13	37
-#define IRQ_IOP331_XINT14	38
-#define IRQ_IOP331_XINT15	39
-#define IRQ_IOP331_UART0	51
-#define IRQ_IOP331_UART1	52
-#define IRQ_IOP331_PBIE		53
-#define IRQ_IOP331_ATU_CRW	54
-#define IRQ_IOP331_ATU_ERR	55
-#define IRQ_IOP331_MCU_ERR	56
-#define IRQ_IOP331_DMA0_ERR	57
-#define IRQ_IOP331_DMA1_ERR	58
-#define IRQ_IOP331_AA_ERR	60
-#define IRQ_IOP331_MSG_ERR	62
-#define IRQ_IOP331_HPI		63
+#define IRQ_IOP33X_DMA0_EOT	0
+#define IRQ_IOP33X_DMA0_EOC	1
+#define IRQ_IOP33X_DMA1_EOT	2
+#define IRQ_IOP33X_DMA1_EOC	3
+#define IRQ_IOP33X_AA_EOT	6
+#define IRQ_IOP33X_AA_EOC	7
+#define IRQ_IOP33X_TIMER0	8
+#define IRQ_IOP33X_TIMER1	9
+#define IRQ_IOP33X_I2C_0	10
+#define IRQ_IOP33X_I2C_1	11
+#define IRQ_IOP33X_MSG		12
+#define IRQ_IOP33X_MSGIBQ	13
+#define IRQ_IOP33X_ATU_BIST	14
+#define IRQ_IOP33X_PERFMON	15
+#define IRQ_IOP33X_CORE_PMU	16
+#define IRQ_IOP33X_XINT0	24
+#define IRQ_IOP33X_XINT1	25
+#define IRQ_IOP33X_XINT2	26
+#define IRQ_IOP33X_XINT3	27
+#define IRQ_IOP33X_XINT8	32
+#define IRQ_IOP33X_XINT9	33
+#define IRQ_IOP33X_XINT10	34
+#define IRQ_IOP33X_XINT11	35
+#define IRQ_IOP33X_XINT12	36
+#define IRQ_IOP33X_XINT13	37
+#define IRQ_IOP33X_XINT14	38
+#define IRQ_IOP33X_XINT15	39
+#define IRQ_IOP33X_UART0	51
+#define IRQ_IOP33X_UART1	52
+#define IRQ_IOP33X_PBIE		53
+#define IRQ_IOP33X_ATU_CRW	54
+#define IRQ_IOP33X_ATU_ERR	55
+#define IRQ_IOP33X_MCU_ERR	56
+#define IRQ_IOP33X_DMA0_ERR	57
+#define IRQ_IOP33X_DMA1_ERR	58
+#define IRQ_IOP33X_AA_ERR	60
+#define IRQ_IOP33X_MSG_ERR	62
+#define IRQ_IOP33X_HPI		63
 
 #define NR_IRQS			64
 
 
-#endif // _IRQ_H_
+#endif

include/asm-arm/arch-iop33x/memory.h

 /*
- * linux/include/asm-arm/arch-iop33x/memory.h
+ * include/asm-arm/arch-iop33x/memory.h
  */
 
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
+#ifndef __MEMORY_H
+#define __MEMORY_H
 
 #include <asm/hardware.h>
 

include/asm-arm/arch-iop33x/system.h

 /*
- * linux/include/asm-arm/arch-iop33x/system.h
+ * include/asm-arm/arch-iop33x/system.h
  *
  * Copyright (C) 2001 MontaVista Software, Inc.
  *
@@ -13,17 +13,10 @@ static inline void arch_idle(void)
 	cpu_do_idle();
 }
 
-
 static inline void arch_reset(char mode)
 {
 	*IOP3XX_PCSR = 0x30;
 
-	if ( 1 && mode == 's') {
 	/* Jump into ROM at address 0 */
 	cpu_reset(0);
-	} else {
-		/* No on-chip reset capability */
-		cpu_reset(0);
-	}
 }
-

include/asm-arm/arch-iop33x/timex.h

 /*
- * linux/include/asm-arm/arch-iop33x/timex.h
+ * include/asm-arm/arch-iop33x/timex.h
  *
  * IOP3xx architecture timex specifications
  */
+
 #include <asm/hardware.h>
 
 #define CLOCK_TICK_RATE		(100 * HZ)

include/asm-arm/arch-iop33x/uncompress.h

 /*
- *  linux/include/asm-arm/arch-iop33x/uncompress.h
+ * include/asm-arm/arch-iop33x/uncompress.h
  */
+
 #include <asm/types.h>
 #include <asm/mach-types.h>
 #include <linux/serial_reg.h>
@@ -8,13 +9,13 @@
 
 static volatile u32 *uart_base;
 
-#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
+#define TX_DONE		(UART_LSR_TEMT | UART_LSR_THRE)
 
 static inline void putc(char c)
 {
 	while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
 		barrier();
-	*uart_base = c;
+	uart_base[UART_TX] = c;
 }
 
 static inline void flush(void)
@@ -24,7 +25,7 @@ static inline void flush(void)
 static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 {
 	if (machine_is_iq80331() || machine_is_iq80332())
-		uart_base = (volatile u32 *)IOP331_UART0_PHYS;
+		uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
 	else
 		uart_base = (volatile u32 *)0xfe800000;
 }

include/asm-arm/arch-iop33x/vmalloc.h

 /*
- * linux/include/asm-arm/arch-iop33x/vmalloc.h
+ * include/asm-arm/arch-iop33x/vmalloc.h
  */
 
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-//#define VMALLOC_END       (0xe8000000)
-/* increase usable physical RAM to ~992M per RMK */
-#define VMALLOC_END       (0xfe000000)
-
+#define VMALLOC_END	0xfe000000