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提交 b2a9dd46 编写于 作者: T Thomas Abraham 提交者： Kukjin Kim
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ARM: S5PV210: Add clkdev support 

Signed-off-by: NThomas Abraham <thomas.ab@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
上级 29e8eb0f
隐藏空白更改
内联 并排
Showing with 41 addition and 90 deletion
arch/arm/Kconfig
浏览文件 @ b2a9dd46
...@@ -755,6 +755,7 @@ config ARCH_S5PV210 ...@@ -755,6 +755,7 @@ config ARCH_S5PV210
select ARCH_SPARSEMEM_ENABLE select ARCH_SPARSEMEM_ENABLE
select GENERIC_GPIO select GENERIC_GPIO
select HAVE_CLK select HAVE_CLK
select CLKDEV_LOOKUP
select ARM_L1_CACHE_SHIFT_6 select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS select GENERIC_CLOCKEVENTS
......
arch/arm/mach-s5pv210/clock.c
浏览文件 @ b2a9dd46
...@@ -36,7 +36,6 @@ static unsigned long xtal; ...@@ -36,7 +36,6 @@ static unsigned long xtal;
static struct clksrc_clk clk_mout_apll = { static struct clksrc_clk clk_mout_apll = {
.clk = { .clk = {
.name = "mout_apll", .name = "mout_apll",
.id = -1,
}, },
.sources = &clk_src_apll, .sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
...@@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = { ...@@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_mout_epll = { static struct clksrc_clk clk_mout_epll = {
.clk = { .clk = {
.name = "mout_epll", .name = "mout_epll",
.id = -1,
}, },
.sources = &clk_src_epll, .sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
...@@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = { ...@@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = {
static struct clksrc_clk clk_mout_mpll = { static struct clksrc_clk clk_mout_mpll = {
.clk = { .clk = {
.name = "mout_mpll", .name = "mout_mpll",
.id = -1,
}, },
.sources = &clk_src_mpll, .sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
...@@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = { ...@@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = {
static struct clksrc_clk clk_armclk = { static struct clksrc_clk clk_armclk = {
.clk = { .clk = {
.name = "armclk", .name = "armclk",
.id = -1,
}, },
.sources = &clkset_armclk, .sources = &clkset_armclk,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
...@@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = { ...@@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = {
static struct clksrc_clk clk_hclk_msys = { static struct clksrc_clk clk_hclk_msys = {
.clk = { .clk = {
.name = "hclk_msys", .name = "hclk_msys",
.id = -1,
.parent = &clk_armclk.clk, .parent = &clk_armclk.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
...@@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = { ...@@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = {
static struct clksrc_clk clk_pclk_msys = { static struct clksrc_clk clk_pclk_msys = {
.clk = { .clk = {
.name = "pclk_msys", .name = "pclk_msys",
.id = -1,
.parent = &clk_hclk_msys.clk, .parent = &clk_hclk_msys.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
...@@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = { ...@@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = {
static struct clksrc_clk clk_sclk_a2m = { static struct clksrc_clk clk_sclk_a2m = {
.clk = { .clk = {
.name = "sclk_a2m", .name = "sclk_a2m",
.id = -1,
.parent = &clk_mout_apll.clk, .parent = &clk_mout_apll.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
...@@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = { ...@@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = {
static struct clksrc_clk clk_hclk_dsys = { static struct clksrc_clk clk_hclk_dsys = {
.clk = { .clk = {
.name = "hclk_dsys", .name = "hclk_dsys",
.id = -1,
}, },
.sources = &clkset_hclk_sys, .sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
...@@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = { ...@@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = {
static struct clksrc_clk clk_pclk_dsys = { static struct clksrc_clk clk_pclk_dsys = {
.clk = { .clk = {
.name = "pclk_dsys", .name = "pclk_dsys",
.id = -1,
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
...@@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = { ...@@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = {
static struct clksrc_clk clk_hclk_psys = { static struct clksrc_clk clk_hclk_psys = {
.clk = { .clk = {
.name = "hclk_psys", .name = "hclk_psys",
.id = -1,
}, },
.sources = &clkset_hclk_sys, .sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
...@@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = { ...@@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = {
static struct clksrc_clk clk_pclk_psys = { static struct clksrc_clk clk_pclk_psys = {
.clk = { .clk = {
.name = "pclk_psys", .name = "pclk_psys",
.id = -1,
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 }, .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
...@@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) ...@@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
static struct clk clk_sclk_hdmi27m = { static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m", .name = "sclk_hdmi27m",
.id = -1,
.rate = 27000000, .rate = 27000000,
}; };
static struct clk clk_sclk_hdmiphy = { static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy", .name = "sclk_hdmiphy",
.id = -1,
}; };
static struct clk clk_sclk_usbphy0 = { static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0", .name = "sclk_usbphy0",
.id = -1,
}; };
static struct clk clk_sclk_usbphy1 = { static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1", .name = "sclk_usbphy1",
.id = -1,
}; };
static struct clk clk_pcmcdclk0 = { static struct clk clk_pcmcdclk0 = {
.name = "pcmcdclk", .name = "pcmcdclk",
.id = -1,
}; };
static struct clk clk_pcmcdclk1 = { static struct clk clk_pcmcdclk1 = {
.name = "pcmcdclk", .name = "pcmcdclk",
.id = -1,
}; };
static struct clk clk_pcmcdclk2 = { static struct clk clk_pcmcdclk2 = {
.name = "pcmcdclk", .name = "pcmcdclk",
.id = -1,
}; };
static struct clk *clkset_vpllsrc_list[] = { static struct clk *clkset_vpllsrc_list[] = {
...@@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = { ...@@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = {
static struct clksrc_clk clk_vpllsrc = { static struct clksrc_clk clk_vpllsrc = {
.clk = { .clk = {
.name = "vpll_src", .name = "vpll_src",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, },
...@@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = { ...@@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
static struct clksrc_clk clk_sclk_vpll = { static struct clksrc_clk clk_sclk_vpll = {
.clk = { .clk = {
.name = "sclk_vpll", .name = "sclk_vpll",
.id = -1,
}, },
.sources = &clkset_sclk_vpll, .sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
...@@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = { ...@@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = {
static struct clksrc_clk clk_mout_dmc0 = { static struct clksrc_clk clk_mout_dmc0 = {
.clk = { .clk = {
.name = "mout_dmc0", .name = "mout_dmc0",
.id = -1,
}, },
.sources = &clkset_moutdmc0src, .sources = &clkset_moutdmc0src,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
...@@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = { ...@@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = {
static struct clksrc_clk clk_sclk_dmc0 = { static struct clksrc_clk clk_sclk_dmc0 = {
.clk = { .clk = {
.name = "sclk_dmc0", .name = "sclk_dmc0",
.id = -1,
.parent = &clk_mout_dmc0.clk, .parent = &clk_mout_dmc0.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 }, .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
...@@ -312,181 +290,169 @@ static struct clk_ops clk_fout_apll_ops = { ...@@ -312,181 +290,169 @@ static struct clk_ops clk_fout_apll_ops = {
static struct clk init_clocks_off[] = { static struct clk init_clocks_off[] = {
{ {
.name = "pdma", .name = "pdma",
.id = 0, .devname = "s3c-pl330.0",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "pdma", .name = "pdma",
.id = 1, .devname = "s3c-pl330.1",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, { }, {
.name = "rot", .name = "rot",
.id = -1,
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1<<29), .ctrlbit = (1<<29),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 0, .devname = "s5pv210-fimc.0",
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 1, .devname = "s5pv210-fimc.1",
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 25), .ctrlbit = (1 << 25),
}, { }, {
.name = "fimc", .name = "fimc",
.id = 2, .devname = "s5pv210-fimc.2",
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 26), .ctrlbit = (1 << 26),
}, { }, {
.name = "otg", .name = "otg",
.id = -1,
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl, .enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<16), .ctrlbit = (1<<16),
}, { }, {
.name = "usb-host", .name = "usb-host",
.id = -1,
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl, .enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<17), .ctrlbit = (1<<17),
}, { }, {
.name = "lcd", .name = "lcd",
.id = -1,
.parent = &clk_hclk_dsys.clk, .parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip1_ctrl, .enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<0), .ctrlbit = (1<<0),
}, { }, {
.name = "cfcon", .name = "cfcon",
.id = 0,
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl, .enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<25), .ctrlbit = (1<<25),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 0, .devname = "s3c-sdhci.0",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl, .enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<16), .ctrlbit = (1<<16),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 1, .devname = "s3c-sdhci.1",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl, .enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<17), .ctrlbit = (1<<17),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 2, .devname = "s3c-sdhci.2",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl, .enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<18), .ctrlbit = (1<<18),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.id = 3, .devname = "s3c-sdhci.3",
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl, .enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<19), .ctrlbit = (1<<19),
}, { }, {
.name = "systimer", .name = "systimer",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<16), .ctrlbit = (1<<16),
}, { }, {
.name = "watchdog", .name = "watchdog",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<22), .ctrlbit = (1<<22),
}, { }, {
.name = "rtc", .name = "rtc",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<15), .ctrlbit = (1<<15),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 0, .devname = "s3c2440-i2c.0",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<7), .ctrlbit = (1<<7),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 1, .devname = "s3c2440-i2c.1",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, { }, {
.name = "i2c", .name = "i2c",
.id = 2, .devname = "s3c2440-i2c.2",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<9), .ctrlbit = (1<<9),
}, { }, {
.name = "spi", .name = "spi",
.id = 0, .devname = "s3c64xx-spi.0",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<12), .ctrlbit = (1<<12),
}, { }, {
.name = "spi", .name = "spi",
.id = 1, .devname = "s3c64xx-spi.1",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<13), .ctrlbit = (1<<13),
}, { }, {
.name = "spi", .name = "spi",
.id = 2, .devname = "s3c64xx-spi.2",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<14), .ctrlbit = (1<<14),
}, { }, {
.name = "timers", .name = "timers",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<23), .ctrlbit = (1<<23),
}, { }, {
.name = "adc", .name = "adc",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<24), .ctrlbit = (1<<24),
}, { }, {
.name = "keypad", .name = "keypad",
.id = -1,
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<21), .ctrlbit = (1<<21),
}, { }, {
.name = "iis", .name = "iis",
.id = 0, .devname = "samsung-i2s.0",
.parent = &clk_p, .parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<4), .ctrlbit = (1<<4),
}, { }, {
.name = "iis", .name = "iis",
.id = 1, .devname = "samsung-i2s.1",
.parent = &clk_p, .parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "iis", .name = "iis",
.id = 2, .devname = "samsung-i2s.2",
.parent = &clk_p, .parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "spdif", .name = "spdif",
.id = -1,
.parent = &clk_p, .parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
...@@ -496,38 +462,36 @@ static struct clk init_clocks_off[] = { ...@@ -496,38 +462,36 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = { static struct clk init_clocks[] = {
{ {
.name = "hclk_imem", .name = "hclk_imem",
.id = -1,
.parent = &clk_hclk_msys.clk, .parent = &clk_hclk_msys.clk,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ops = &clk_hclk_imem_ops, .ops = &clk_hclk_imem_ops,
}, { }, {
.name = "uart", .name = "uart",
.id = 0, .devname = "s5pv210-uart.0",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
}, { }, {
.name = "uart", .name = "uart",
.id = 1, .devname = "s5pv210-uart.1",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 18), .ctrlbit = (1 << 18),
}, { }, {
.name = "uart", .name = "uart",
.id = 2, .devname = "s5pv210-uart.2",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 19), .ctrlbit = (1 << 19),
}, { }, {
.name = "uart", .name = "uart",
.id = 3, .devname = "s5pv210-uart.3",
.parent = &clk_pclk_psys.clk, .parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl, .enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
}, { }, {
.name = "sromc", .name = "sromc",
.id = -1,
.parent = &clk_hclk_psys.clk, .parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl, .enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 26), .ctrlbit = (1 << 26),
...@@ -579,7 +543,6 @@ static struct clksrc_sources clkset_sclk_dac = { ...@@ -579,7 +543,6 @@ static struct clksrc_sources clkset_sclk_dac = {
static struct clksrc_clk clk_sclk_dac = { static struct clksrc_clk clk_sclk_dac = {
.clk = { .clk = {
.name = "sclk_dac", .name = "sclk_dac",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, },
...@@ -590,7 +553,6 @@ static struct clksrc_clk clk_sclk_dac = { ...@@ -590,7 +553,6 @@ static struct clksrc_clk clk_sclk_dac = {
static struct clksrc_clk clk_sclk_pixel = { static struct clksrc_clk clk_sclk_pixel = {
.clk = { .clk = {
.name = "sclk_pixel", .name = "sclk_pixel",
.id = -1,
.parent = &clk_sclk_vpll.clk, .parent = &clk_sclk_vpll.clk,
}, },
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4}, .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
...@@ -609,7 +571,6 @@ static struct clksrc_sources clkset_sclk_hdmi = { ...@@ -609,7 +571,6 @@ static struct clksrc_sources clkset_sclk_hdmi = {
static struct clksrc_clk clk_sclk_hdmi = { static struct clksrc_clk clk_sclk_hdmi = {
.clk = { .clk = {
.name = "sclk_hdmi", .name = "sclk_hdmi",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
}, },
...@@ -647,7 +608,7 @@ static struct clksrc_sources clkset_sclk_audio0 = { ...@@ -647,7 +608,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = { static struct clksrc_clk clk_sclk_audio0 = {
.clk = { .clk = {
.name = "sclk_audio", .name = "sclk_audio",
.id = 0, .devname = "soc-audio.0",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 24), .ctrlbit = (1 << 24),
}, },
...@@ -676,7 +637,7 @@ static struct clksrc_sources clkset_sclk_audio1 = { ...@@ -676,7 +637,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
static struct clksrc_clk clk_sclk_audio1 = { static struct clksrc_clk clk_sclk_audio1 = {
.clk = { .clk = {
.name = "sclk_audio", .name = "sclk_audio",
.id = 1, .devname = "soc-audio.1",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 25), .ctrlbit = (1 << 25),
}, },
...@@ -705,7 +666,7 @@ static struct clksrc_sources clkset_sclk_audio2 = { ...@@ -705,7 +666,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
static struct clksrc_clk clk_sclk_audio2 = { static struct clksrc_clk clk_sclk_audio2 = {
.clk = { .clk = {
.name = "sclk_audio", .name = "sclk_audio",
.id = 2, .devname = "soc-audio.2",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 26), .ctrlbit = (1 << 26),
}, },
...@@ -763,7 +724,6 @@ static struct clk_ops s5pv210_sclk_spdif_ops = { ...@@ -763,7 +724,6 @@ static struct clk_ops s5pv210_sclk_spdif_ops = {
static struct clksrc_clk clk_sclk_spdif = { static struct clksrc_clk clk_sclk_spdif = {
.clk = { .clk = {
.name = "sclk_spdif", .name = "sclk_spdif",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 27), .ctrlbit = (1 << 27),
.ops = &s5pv210_sclk_spdif_ops, .ops = &s5pv210_sclk_spdif_ops,
...@@ -793,7 +753,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -793,7 +753,6 @@ static struct clksrc_clk clksrcs[] = {
{ {
.clk = { .clk = {
.name = "sclk_dmc", .name = "sclk_dmc",
.id = -1,
}, },
.sources = &clkset_group1, .sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 }, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
...@@ -801,7 +760,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -801,7 +760,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_onenand", .name = "sclk_onenand",
.id = -1,
}, },
.sources = &clkset_sclk_onenand, .sources = &clkset_sclk_onenand,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 }, .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
...@@ -809,7 +767,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -809,7 +767,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 0, .devname = "s5pv210-uart.0",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, },
...@@ -819,7 +777,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -819,7 +777,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 1, .devname = "s5pv210-uart.1",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 13), .ctrlbit = (1 << 13),
}, },
...@@ -829,7 +787,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -829,7 +787,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 2, .devname = "s5pv210-uart.2",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 14), .ctrlbit = (1 << 14),
}, },
...@@ -839,7 +797,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -839,7 +797,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "uclk1", .name = "uclk1",
.id = 3, .devname = "s5pv210-uart.3",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 15), .ctrlbit = (1 << 15),
}, },
...@@ -849,7 +807,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -849,7 +807,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mixer", .name = "sclk_mixer",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 1), .ctrlbit = (1 << 1),
}, },
...@@ -858,7 +815,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -858,7 +815,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 0, .devname = "s5pv210-fimc.0",
.enable = s5pv210_clk_mask1_ctrl, .enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 2), .ctrlbit = (1 << 2),
}, },
...@@ -868,7 +825,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -868,7 +825,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 1, .devname = "s5pv210-fimc.1",
.enable = s5pv210_clk_mask1_ctrl, .enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, },
...@@ -878,7 +835,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -878,7 +835,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimc", .name = "sclk_fimc",
.id = 2, .devname = "s5pv210-fimc.2",
.enable = s5pv210_clk_mask1_ctrl, .enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, },
...@@ -888,7 +845,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -888,7 +845,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_cam", .name = "sclk_cam",
.id = 0, .devname = "s5pv210-fimc.0",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, },
...@@ -898,7 +855,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -898,7 +855,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_cam", .name = "sclk_cam",
.id = 1, .devname = "s5pv210-fimc.1",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
}, },
...@@ -908,7 +865,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -908,7 +865,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_fimd", .name = "sclk_fimd",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, },
...@@ -918,7 +874,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -918,7 +874,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 0, .devname = "s3c-sdhci.0",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, },
...@@ -928,7 +884,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -928,7 +884,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 1, .devname = "s3c-sdhci.1",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 9), .ctrlbit = (1 << 9),
}, },
...@@ -938,7 +894,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -938,7 +894,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 2, .devname = "s3c-sdhci.2",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 10), .ctrlbit = (1 << 10),
}, },
...@@ -948,7 +904,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -948,7 +904,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.id = 3, .devname = "s3c-sdhci.3",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 11), .ctrlbit = (1 << 11),
}, },
...@@ -958,7 +914,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -958,7 +914,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_mfc", .name = "sclk_mfc",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, },
...@@ -968,7 +923,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -968,7 +923,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_g2d", .name = "sclk_g2d",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, },
...@@ -978,7 +932,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -978,7 +932,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_g3d", .name = "sclk_g3d",
.id = -1,
.enable = s5pv210_clk_ip0_ctrl, .enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
}, },
...@@ -988,7 +941,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -988,7 +941,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_csis", .name = "sclk_csis",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, },
...@@ -998,7 +950,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -998,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 0, .devname = "s3c64xx-spi.0",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 16), .ctrlbit = (1 << 16),
}, },
...@@ -1008,7 +960,7 @@ static struct clksrc_clk clksrcs[] = { ...@@ -1008,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_spi", .name = "sclk_spi",
.id = 1, .devname = "s3c64xx-spi.1",
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 17), .ctrlbit = (1 << 17),
}, },
...@@ -1018,7 +970,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -1018,7 +970,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_pwi", .name = "sclk_pwi",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 29), .ctrlbit = (1 << 29),
}, },
...@@ -1028,7 +979,6 @@ static struct clksrc_clk clksrcs[] = { ...@@ -1028,7 +979,6 @@ static struct clksrc_clk clksrcs[] = {
}, { }, {
.clk = { .clk = {
.name = "sclk_pwm", .name = "sclk_pwm",
.id = -1,
.enable = s5pv210_clk_mask0_ctrl, .enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 19), .ctrlbit = (1 << 19),
}, },
......
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