提交 af2418be 编写于 作者: F Florian Fainelli 提交者: Ralf Baechle

MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.
Reported-by: NDaniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: NFlorian Fainelli <florian@openwrt.org>
上级 a4c0201e
......@@ -138,6 +138,7 @@ config BCM63XX
select SWAP_IO_SPACE
select ARCH_REQUIRE_GPIOLIB
select HAVE_CLK
select MIPS_L1_CACHE_SHIFT_4
help
Support for BCM63XX based boards
......
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