提交 a836bdf9 编写于 作者: P Paulo Zanoni 提交者: Daniel Vetter

drm/i915: add DP support to intel_ddi_disable_port

Just a missing register. There is no problem to run this code when the
output is HDMI.
Signed-off-by: NPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: NJani Nikula <jani.nikula@intel.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
上级 247d89f6
...@@ -1138,14 +1138,23 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder) ...@@ -1138,14 +1138,23 @@ void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
struct drm_i915_private *dev_priv = encoder->dev->dev_private; struct drm_i915_private *dev_priv = encoder->dev->dev_private;
enum port port = intel_ddi_get_encoder_port(intel_encoder); enum port port = intel_ddi_get_encoder_port(intel_encoder);
uint32_t val; uint32_t val;
bool wait = false;
val = I915_READ(DDI_BUF_CTL(port)); val = I915_READ(DDI_BUF_CTL(port));
if (val & DDI_BUF_CTL_ENABLE) { if (val & DDI_BUF_CTL_ENABLE) {
val &= ~DDI_BUF_CTL_ENABLE; val &= ~DDI_BUF_CTL_ENABLE;
I915_WRITE(DDI_BUF_CTL(port), val); I915_WRITE(DDI_BUF_CTL(port), val);
intel_wait_ddi_buf_idle(dev_priv, port); wait = true;
} }
val = I915_READ(DP_TP_CTL(port));
val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
val |= DP_TP_CTL_LINK_TRAIN_PAT1;
I915_WRITE(DP_TP_CTL(port), val);
if (wait)
intel_wait_ddi_buf_idle(dev_priv, port);
I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
} }
......
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