提交 a52074ee 编写于 作者: T Tomasz Stanislawski 提交者: Mauro Carvalho Chehab

[media] v4l: s5p-tv: add drivers for HDMI on Samsung S5P platform

Add drivers for HDMI outputs on Samsung platforms from S5P family.

Drivers are using:
- v4l2 framework
- runtime PM
Signed-off-by: NTomasz Stanislawski <t.stanislaws@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: NHans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
上级 5930ab2b
......@@ -971,6 +971,8 @@ config VIDEO_S5P_MIPI_CSIS
To compile this driver as a module, choose M here: the
module will be called s5p-csis.
source "drivers/media/video/s5p-tv/Kconfig"
#
# USB Multimedia device configuration
#
......
......@@ -172,6 +172,7 @@ obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) += s5p-fimc/
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_MFC) += s5p-mfc/
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_TV) += s5p-tv/
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
......
# drivers/media/video/s5p-tv/Kconfig
#
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
# Tomasz Stanislawski <t.stanislaws@samsung.com>
#
# Licensed under GPL
config VIDEO_SAMSUNG_S5P_TV
bool "Samsung TV driver for S5P platform (experimental)"
depends on PLAT_S5P
depends on EXPERIMENTAL
default n
---help---
Say Y here to enable selecting the TV output devices for
Samsung S5P platform.
if VIDEO_SAMSUNG_S5P_TV
config VIDEO_SAMSUNG_S5P_HDMI
tristate "Samsung HDMI Driver"
depends on VIDEO_V4L2
depends on VIDEO_SAMSUNG_S5P_TV
select VIDEO_SAMSUNG_S5P_HDMIPHY
help
Say Y here if you want support for the HDMI output
interface in S5P Samsung SoC. The driver can be compiled
as module. It is an auxiliary driver, that exposes a V4L2
subdev for use by other drivers. This driver requires
hdmiphy driver to work correctly.
config VIDEO_SAMSUNG_S5P_HDMI_DEBUG
bool "Enable debug for HDMI Driver"
depends on VIDEO_SAMSUNG_S5P_HDMI
default n
help
Enables debugging for HDMI driver.
config VIDEO_SAMSUNG_S5P_HDMIPHY
tristate "Samsung HDMIPHY Driver"
depends on VIDEO_DEV && VIDEO_V4L2 && I2C
depends on VIDEO_SAMSUNG_S5P_TV
help
Say Y here if you want support for the physical HDMI
interface in S5P Samsung SoC. The driver can be compiled
as module. It is an I2C driver, that exposes a V4L2
subdev for use by other drivers.
endif # VIDEO_SAMSUNG_S5P_TV
# drivers/media/video/samsung/tvout/Makefile
#
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/
# Tomasz Stanislawski <t.stanislaws@samsung.com>
#
# Licensed under GPL
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_HDMIPHY) += s5p-hdmiphy.o
s5p-hdmiphy-y += hdmiphy_drv.o
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_HDMI) += s5p-hdmi.o
s5p-hdmi-y += hdmi_drv.o
此差异已折叠。
/*
* Samsung HDMI Physical interface driver
*
* Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
* Author: Tomasz Stanislawski <t.stanislaws@samsung.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/module.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <media/v4l2-subdev.h>
MODULE_AUTHOR("Tomasz Stanislawski <t.stanislaws@samsung.com>");
MODULE_DESCRIPTION("Samsung HDMI Physical interface driver");
MODULE_LICENSE("GPL");
struct hdmiphy_conf {
u32 preset;
const u8 *data;
};
static const u8 hdmiphy_conf27[32] = {
0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
0x6B, 0x10, 0x02, 0x51, 0xDf, 0xF2, 0x54, 0x87,
0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
0x22, 0x40, 0xe3, 0x26, 0x00, 0x00, 0x00, 0x00,
};
static const u8 hdmiphy_conf74_175[32] = {
0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
};
static const u8 hdmiphy_conf74_25[32] = {
0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xe0,
0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
};
static const u8 hdmiphy_conf148_5[32] = {
0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
};
static const struct hdmiphy_conf hdmiphy_conf[] = {
{ V4L2_DV_480P59_94, hdmiphy_conf27 },
{ V4L2_DV_1080P30, hdmiphy_conf74_175 },
{ V4L2_DV_720P59_94, hdmiphy_conf74_175 },
{ V4L2_DV_720P60, hdmiphy_conf74_25 },
{ V4L2_DV_1080P50, hdmiphy_conf148_5 },
{ V4L2_DV_1080P60, hdmiphy_conf148_5 },
};
const u8 *hdmiphy_preset2conf(u32 preset)
{
int i;
for (i = 0; i < ARRAY_SIZE(hdmiphy_conf); ++i)
if (hdmiphy_conf[i].preset == preset)
return hdmiphy_conf[i].data;
return NULL;
}
static int hdmiphy_s_power(struct v4l2_subdev *sd, int on)
{
/* to be implemented */
return 0;
}
static int hdmiphy_s_dv_preset(struct v4l2_subdev *sd,
struct v4l2_dv_preset *preset)
{
const u8 *data;
u8 buffer[32];
int ret;
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct device *dev = &client->dev;
dev_info(dev, "s_dv_preset(preset = %d)\n", preset->preset);
data = hdmiphy_preset2conf(preset->preset);
if (!data) {
dev_err(dev, "format not supported\n");
return -EINVAL;
}
/* storing configuration to the device */
memcpy(buffer, data, 32);
ret = i2c_master_send(client, buffer, 32);
if (ret != 32) {
dev_err(dev, "failed to configure HDMIPHY via I2C\n");
return -EIO;
}
return 0;
}
static int hdmiphy_s_stream(struct v4l2_subdev *sd, int enable)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
struct device *dev = &client->dev;
u8 buffer[2];
int ret;
dev_info(dev, "s_stream(%d)\n", enable);
/* going to/from configuration from/to operation mode */
buffer[0] = 0x1f;
buffer[1] = enable ? 0x80 : 0x00;
ret = i2c_master_send(client, buffer, 2);
if (ret != 2) {
dev_err(dev, "stream (%d) failed\n", enable);
return -EIO;
}
return 0;
}
static const struct v4l2_subdev_core_ops hdmiphy_core_ops = {
.s_power = hdmiphy_s_power,
};
static const struct v4l2_subdev_video_ops hdmiphy_video_ops = {
.s_dv_preset = hdmiphy_s_dv_preset,
.s_stream = hdmiphy_s_stream,
};
static const struct v4l2_subdev_ops hdmiphy_ops = {
.core = &hdmiphy_core_ops,
.video = &hdmiphy_video_ops,
};
static int __devinit hdmiphy_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
static struct v4l2_subdev sd;
v4l2_i2c_subdev_init(&sd, client, &hdmiphy_ops);
dev_info(&client->dev, "probe successful\n");
return 0;
}
static int __devexit hdmiphy_remove(struct i2c_client *client)
{
dev_info(&client->dev, "remove successful\n");
return 0;
}
static const struct i2c_device_id hdmiphy_id[] = {
{ "hdmiphy", 0 },
{ },
};
MODULE_DEVICE_TABLE(i2c, hdmiphy_id);
static struct i2c_driver hdmiphy_driver = {
.driver = {
.name = "s5p-hdmiphy",
.owner = THIS_MODULE,
},
.probe = hdmiphy_probe,
.remove = __devexit_p(hdmiphy_remove),
.id_table = hdmiphy_id,
};
static int __init hdmiphy_init(void)
{
return i2c_add_driver(&hdmiphy_driver);
}
module_init(hdmiphy_init);
static void __exit hdmiphy_exit(void)
{
i2c_del_driver(&hdmiphy_driver);
}
module_exit(hdmiphy_exit);
/* linux/arch/arm/mach-exynos4/include/mach/regs-hdmi.h
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* HDMI register header file for Samsung TVOUT driver
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef SAMSUNG_REGS_HDMI_H
#define SAMSUNG_REGS_HDMI_H
/*
* Register part
*/
#define HDMI_CTRL_BASE(x) ((x) + 0x00000000)
#define HDMI_CORE_BASE(x) ((x) + 0x00010000)
#define HDMI_TG_BASE(x) ((x) + 0x00050000)
/* Control registers */
#define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000)
#define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004)
#define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C)
#define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0014)
#define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0018)
#define HDMI_PHY_CMU HDMI_CTRL_BASE(0x001C)
#define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0020)
/* Core registers */
#define HDMI_CON_0 HDMI_CORE_BASE(0x0000)
#define HDMI_CON_1 HDMI_CORE_BASE(0x0004)
#define HDMI_CON_2 HDMI_CORE_BASE(0x0008)
#define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010)
#define HDMI_PHY_STATUS HDMI_CORE_BASE(0x0014)
#define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020)
#define HDMI_HPD HDMI_CORE_BASE(0x0030)
#define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040)
#define HDMI_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050)
#define HDMI_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054)
#define HDMI_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058)
#define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0)
#define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4)
#define HDMI_V_BLANK_0 HDMI_CORE_BASE(0x00B0)
#define HDMI_V_BLANK_1 HDMI_CORE_BASE(0x00B4)
#define HDMI_V_BLANK_2 HDMI_CORE_BASE(0x00B8)
#define HDMI_H_V_LINE_0 HDMI_CORE_BASE(0x00C0)
#define HDMI_H_V_LINE_1 HDMI_CORE_BASE(0x00C4)
#define HDMI_H_V_LINE_2 HDMI_CORE_BASE(0x00C8)
#define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4)
#define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8)
#define HDMI_V_BLANK_F_0 HDMI_CORE_BASE(0x0110)
#define HDMI_V_BLANK_F_1 HDMI_CORE_BASE(0x0114)
#define HDMI_V_BLANK_F_2 HDMI_CORE_BASE(0x0118)
#define HDMI_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120)
#define HDMI_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124)
#define HDMI_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128)
#define HDMI_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130)
#define HDMI_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134)
#define HDMI_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138)
#define HDMI_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140)
#define HDMI_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144)
#define HDMI_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148)
#define HDMI_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150)
#define HDMI_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154)
#define HDMI_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158)
#define HDMI_AVI_CON HDMI_CORE_BASE(0x0300)
#define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n))
#define HDMI_DC_CONTROL HDMI_CORE_BASE(0x05C0)
#define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4)
#define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8)
/* Timing generator registers */
#define HDMI_TG_CMD HDMI_TG_BASE(0x0000)
#define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018)
#define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C)
#define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020)
#define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024)
#define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028)
#define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C)
#define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030)
#define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034)
#define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038)
#define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C)
#define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040)
#define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044)
#define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048)
#define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C)
#define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050)
#define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054)
#define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058)
#define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C)
#define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060)
#define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064)
#define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078)
#define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C)
#define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080)
#define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084)
#define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088)
#define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C)
#define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090)
#define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094)
/*
* Bit definition part
*/
/* HDMI_INTC_CON */
#define HDMI_INTC_EN_GLOBAL (1 << 6)
#define HDMI_INTC_EN_HPD_PLUG (1 << 3)
#define HDMI_INTC_EN_HPD_UNPLUG (1 << 2)
/* HDMI_INTC_FLAG */
#define HDMI_INTC_FLAG_HPD_PLUG (1 << 3)
#define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2)
/* HDMI_PHY_RSTOUT */
#define HDMI_PHY_SW_RSTOUT (1 << 0)
/* HDMI_CORE_RSTOUT */
#define HDMI_CORE_SW_RSTOUT (1 << 0)
/* HDMI_CON_0 */
#define HDMI_BLUE_SCR_EN (1 << 5)
#define HDMI_EN (1 << 0)
/* HDMI_PHY_STATUS */
#define HDMI_PHY_STATUS_READY (1 << 0)
/* HDMI_MODE_SEL */
#define HDMI_MODE_HDMI_EN (1 << 1)
#define HDMI_MODE_DVI_EN (1 << 0)
#define HDMI_MODE_MASK (3 << 0)
/* HDMI_TG_CMD */
#define HDMI_TG_EN (1 << 0)
#endif /* SAMSUNG_REGS_HDMI_H */
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