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raspberrypi-kernel
提交 a46699c9 编写于 作者: L Linus Torvalds
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Merge master.kernel.org:/home/rmk/linux-2.6-arm

上级 7ed0175a b216c018
展开全部 隐藏空白更改
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Showing with 11839 addition and 2519 deletion
arch/arm/Kconfig
浏览文件 @ a46699c9
......@@ -239,6 +239,8 @@ source "arch/arm/plat-omap/Kconfig"
source "arch/arm/mach-omap1/Kconfig"
source "arch/arm/mach-omap2/Kconfig"
source "arch/arm/mach-s3c2410/Kconfig"
source "arch/arm/mach-lh7a40x/Kconfig"
......
arch/arm/Makefile
浏览文件 @ a46699c9
......@@ -93,6 +93,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET) := 0xc0008000
machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
machine-$(CONFIG_ARCH_IXP2000) := ixp2000
machine-$(CONFIG_ARCH_OMAP1) := omap1
machine-$(CONFIG_ARCH_OMAP2) := omap2
incdir-$(CONFIG_ARCH_OMAP) := omap
machine-$(CONFIG_ARCH_S3C2410) := s3c2410
machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
......
arch/arm/configs/omap_h2_1610_defconfig
浏览文件 @ a46699c9
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.13
# Mon Sep 5 18:07:12 2005
# Linux kernel version: 2.6.14
# Wed Nov 9 18:53:40 2005
#
CONFIG_ARM=y
CONFIG_MMU=y
......@@ -22,6 +22,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_POSIX_MQUEUE is not set
......@@ -31,6 +32,7 @@ CONFIG_SYSCTL=y
# CONFIG_HOTPLUG is not set
CONFIG_KOBJECT_UEVENT=y
# CONFIG_IKCONFIG is not set
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
......@@ -59,6 +61,23 @@ CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
# CONFIG_KMOD is not set
#
# Block layer
#
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_DEFAULT_AS=y
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# System Type
#
......@@ -81,6 +100,7 @@ CONFIG_OBSOLETE_MODPARM=y
# CONFIG_ARCH_LH7A40X is not set
CONFIG_ARCH_OMAP=y
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_AAEC2000 is not set
......@@ -112,7 +132,7 @@ CONFIG_OMAP_SERIAL_WAKE=y
# OMAP Core Type
#
# CONFIG_ARCH_OMAP730 is not set
# CONFIG_ARCH_OMAP1510 is not set
# CONFIG_ARCH_OMAP15XX is not set
CONFIG_ARCH_OMAP16XX=y
#
......@@ -177,6 +197,8 @@ CONFIG_FLATMEM_MANUAL=y
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
CONFIG_SPLIT_PTLOCK_CPUS=4096
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
......@@ -258,13 +280,18 @@ CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_TUNNEL is not set
CONFIG_IP_TCPDIAG=y
# CONFIG_IP_TCPDIAG_IPV6 is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_BIC=y
# CONFIG_IPV6 is not set
# CONFIG_NETFILTER is not set
#
# DCCP Configuration (EXPERIMENTAL)
#
# CONFIG_IP_DCCP is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
......@@ -281,6 +308,10 @@ CONFIG_TCP_CONG_BIC=y
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
# CONFIG_NET_CLS_ROUTE is not set
......@@ -291,6 +322,7 @@ CONFIG_TCP_CONG_BIC=y
# CONFIG_HAMRADIO is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_IEEE80211 is not set
#
# Device Drivers
......@@ -328,21 +360,13 @@ CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_CDROM_PKTCDVD is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_ATA_OVER_ETH=m
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
CONFIG_SCSI=y
CONFIG_SCSI_PROC_FS=y
......@@ -369,10 +393,12 @@ CONFIG_SCSI_PROC_FS=y
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
# CONFIG_SCSI_ISCSI_ATTRS is not set
# CONFIG_SCSI_SAS_ATTRS is not set
#
# SCSI low-level drivers
#
# CONFIG_ISCSI_TCP is not set
# CONFIG_SCSI_SATA is not set
# CONFIG_SCSI_DEBUG is not set
......@@ -403,6 +429,11 @@ CONFIG_NETDEVICES=y
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
#
# PHY device support
#
# CONFIG_PHYLIB is not set
#
# Ethernet (10 or 100Mbit)
#
......@@ -439,6 +470,7 @@ CONFIG_PPP=y
# CONFIG_PPP_SYNC_TTY is not set
# CONFIG_PPP_DEFLATE is not set
# CONFIG_PPP_BSDCOMP is not set
# CONFIG_PPP_MPPE is not set
# CONFIG_PPPOE is not set
CONFIG_SLIP=y
CONFIG_SLIP_COMPRESSED=y
......@@ -541,24 +573,28 @@ CONFIG_WATCHDOG_NOWAYOUT=y
#
# TPM devices
#
# CONFIG_TELCLOCK is not set
#
# I2C support
#
# CONFIG_I2C is not set
# CONFIG_I2C_SENSOR is not set
CONFIG_ISP1301_OMAP=y
#
# Hardware Monitoring support
#
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Misc devices
#
#
# Multimedia Capabilities Port drivers
#
#
# Multimedia devices
#
......@@ -576,7 +612,6 @@ CONFIG_FB=y
# CONFIG_FB_CFB_FILLRECT is not set
# CONFIG_FB_CFB_COPYAREA is not set
# CONFIG_FB_CFB_IMAGEBLIT is not set
# CONFIG_FB_SOFT_CURSOR is not set
# CONFIG_FB_MACMODES is not set
CONFIG_FB_MODE_HELPERS=y
# CONFIG_FB_TILEBLITTING is not set
......@@ -589,6 +624,7 @@ CONFIG_FB_MODE_HELPERS=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
......@@ -600,6 +636,7 @@ CONFIG_FONT_8x16=y
# CONFIG_FONT_SUN8x16 is not set
# CONFIG_FONT_SUN12x22 is not set
# CONFIG_FONT_10x18 is not set
# CONFIG_FONT_RL is not set
#
# Logo configuration
......@@ -624,10 +661,10 @@ CONFIG_SOUND=y
# Open Sound System
#
CONFIG_SOUND_PRIME=y
# CONFIG_OBSOLETE_OSS_DRIVER is not set
# CONFIG_SOUND_MSNDCLAS is not set
# CONFIG_SOUND_MSNDPIN is not set
# CONFIG_SOUND_OSS is not set
# CONFIG_SOUND_AD1980 is not set
#
# USB support
......@@ -636,23 +673,22 @@ CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB is not set
#
# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
#
#
# USB Gadget Support
#
CONFIG_USB_GADGET=y
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_SELECTED=y
# CONFIG_USB_GADGET is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_PXA2XX is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LH7A40X is not set
CONFIG_USB_GADGET_OMAP=y
CONFIG_USB_OMAP=y
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
# CONFIG_USB_GADGET_DUALSPEED is not set
# CONFIG_USB_ZERO is not set
CONFIG_USB_ETH=y
CONFIG_USB_ETH_RNDIS=y
# CONFIG_USB_ETH is not set
# CONFIG_USB_GADGETFS is not set
# CONFIG_USB_FILE_STORAGE is not set
# CONFIG_USB_G_SERIAL is not set
......@@ -673,10 +709,6 @@ CONFIG_EXT2_FS=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
#
# XFS support
#
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
CONFIG_ROMFS_FS=y
......@@ -685,6 +717,7 @@ CONFIG_INOTIFY=y
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
......@@ -706,10 +739,10 @@ CONFIG_FAT_DEFAULT_CODEPAGE=437
#
CONFIG_PROC_FS=y
CONFIG_SYSFS=y
# CONFIG_DEVPTS_FS_XATTR is not set
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
# CONFIG_RELAYFS_FS is not set
#
# Miscellaneous filesystems
......@@ -750,6 +783,7 @@ CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
# CONFIG_9P_FS is not set
#
# Partition Types
......@@ -859,6 +893,7 @@ CONFIG_CRYPTO_DES=y
# Library routines
#
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
arch/arm/lib/csumpartial.S
浏览文件 @ a46699c9
......@@ -39,6 +39,7 @@ td3 .req lr
/* we must have at least one byte. */
tst buf, #1 @ odd address?
movne sum, sum, ror #8
ldrneb td0, [buf], #1
subne len, len, #1
adcnes sum, sum, td0, put_byte_1
......@@ -103,6 +104,9 @@ ENTRY(csum_partial)
cmp len, #8 @ Ensure that we have at least
blo .less8 @ 8 bytes to copy.
tst buf, #1
movne sum, sum, ror #8
adds sum, sum, #0 @ C = 0
tst buf, #3 @ Test destination alignment
blne .not_aligned @ aligh destination, return here
......
arch/arm/mach-ixp4xx/Kconfig
浏览文件 @ a46699c9
......@@ -8,6 +8,16 @@ menu "Intel IXP4xx Implementation Options"
comment "IXP4xx Platforms"
# This entry is placed on top because otherwise it would have
# been shown as a submenu.
config MACH_NSLU2
bool
prompt "NSLU2" if !(MACH_IXDP465 || MACH_IXDPG425 || ARCH_IXDP425 || ARCH_ADI_COYOTE || ARCH_AVILA || ARCH_IXCDP1100 || ARCH_PRPMC1100 || MACH_GTWX5715)
help
Say 'Y' here if you want your kernel to support Linksys's
NSLU2 NAS device. For more information on this platform,
see http://www.nslu2-linux.org
config ARCH_AVILA
bool "Avila"
help
......
arch/arm/mach-ixp4xx/Makefile
浏览文件 @ a46699c9
......@@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o ixdp425-setup.o
obj-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o coyote-setup.o
obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o coyote-setup.o
obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o gtwx5715-setup.o
obj-$(CONFIG_MACH_NSLU2) += nslu2-pci.o nslu2-setup.o nslu2-power.o
arch/arm/mach-ixp4xx/nslu2-pci.c 0 → 100644
浏览文件 @ a46699c9
/*
* arch/arm/mach-ixp4xx/nslu2-pci.c
*
* NSLU2 board-level PCI initialization
*
* based on ixdp425-pci.c:
* Copyright (C) 2002 Intel Corporation.
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Maintainer: http://www.nslu2-linux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/config.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
void __init nslu2_pci_preinit(void)
{
set_irq_type(IRQ_NSLU2_PCI_INTA, IRQT_LOW);
set_irq_type(IRQ_NSLU2_PCI_INTB, IRQT_LOW);
set_irq_type(IRQ_NSLU2_PCI_INTC, IRQT_LOW);
gpio_line_isr_clear(NSLU2_PCI_INTA_PIN);
gpio_line_isr_clear(NSLU2_PCI_INTB_PIN);
gpio_line_isr_clear(NSLU2_PCI_INTC_PIN);
/* INTD is not configured as GPIO is used
* for the power input button.
*/
ixp4xx_pci_preinit();
}
static int __init nslu2_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[NSLU2_PCI_IRQ_LINES] = {
IRQ_NSLU2_PCI_INTA,
IRQ_NSLU2_PCI_INTB,
IRQ_NSLU2_PCI_INTC,
};
int irq = -1;
if (slot >= 1 && slot <= NSLU2_PCI_MAX_DEV &&
pin >= 1 && pin <= NSLU2_PCI_IRQ_LINES) {
irq = pci_irq_table[(slot + pin - 2) % NSLU2_PCI_IRQ_LINES];
}
return irq;
}
struct hw_pci __initdata nslu2_pci = {
.nr_controllers = 1,
.preinit = nslu2_pci_preinit,
.swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
.scan = ixp4xx_scan_bus,
.map_irq = nslu2_map_irq,
};
int __init nslu2_pci_init(void) /* monkey see, monkey do */
{
if (machine_is_nslu2())
pci_common_init(&nslu2_pci);
return 0;
}
subsys_initcall(nslu2_pci_init);
arch/arm/mach-ixp4xx/nslu2-power.c 0 → 100644
浏览文件 @ a46699c9
/*
* arch/arm/mach-ixp4xx/nslu2-power.c
*
* NSLU2 Power/Reset driver
*
* Copyright (C) 2005 Tower Technologies
*
* based on nslu2-io.c
* Copyright (C) 2004 Karen Spearel
*
* Author: Alessandro Zummo <a.zummo@towertech.it>
* Maintainers: http://www.nslu2-linux.org/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/reboot.h>
#include <linux/interrupt.h>
#include <asm/mach-types.h>
extern void ctrl_alt_del(void);
static irqreturn_t nslu2_power_handler(int irq, void *dev_id, struct pt_regs *regs)
{
/* Signal init to do the ctrlaltdel action, this will bypass init if
* it hasn't started and do a kernel_restart.
*/
ctrl_alt_del();
return IRQ_HANDLED;
}
static irqreturn_t nslu2_reset_handler(int irq, void *dev_id, struct pt_regs *regs)
{
/* This is the paper-clip reset, it shuts the machine down directly.
*/
machine_power_off();
return IRQ_HANDLED;
}
static int __init nslu2_power_init(void)
{
if (!(machine_is_nslu2()))
return 0;
*IXP4XX_GPIO_GPISR = 0x20400000; /* read the 2 irqs to clr */
set_irq_type(NSLU2_RB_IRQ, IRQT_LOW);
set_irq_type(NSLU2_PB_IRQ, IRQT_HIGH);
gpio_line_isr_clear(NSLU2_RB_GPIO);
gpio_line_isr_clear(NSLU2_PB_GPIO);
if (request_irq(NSLU2_RB_IRQ, &nslu2_reset_handler,
SA_INTERRUPT, "NSLU2 reset button", NULL) < 0) {
printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
NSLU2_RB_IRQ);
return -EIO;
}
if (request_irq(NSLU2_PB_IRQ, &nslu2_power_handler,
SA_INTERRUPT, "NSLU2 power button", NULL) < 0) {
printk(KERN_DEBUG "Power Button IRQ %d not available\n",
NSLU2_PB_IRQ);
return -EIO;
}
return 0;
}
static void __exit nslu2_power_exit(void)
{
free_irq(NSLU2_RB_IRQ, NULL);
free_irq(NSLU2_PB_IRQ, NULL);
}
module_init(nslu2_power_init);
module_exit(nslu2_power_exit);
MODULE_AUTHOR("Alessandro Zummo <a.zummo@towertech.it>");
MODULE_DESCRIPTION("NSLU2 Power/Reset driver");
MODULE_LICENSE("GPL");
arch/arm/mach-ixp4xx/nslu2-setup.c 0 → 100644
浏览文件 @ a46699c9
/*
* arch/arm/mach-ixp4xx/nslu2-setup.c
*
* NSLU2 board-setup
*
* based ixdp425-setup.c:
* Copyright (C) 2003-2004 MontaVista Software, Inc.
*
* Author: Mark Rakes <mrakes at mac.com>
* Maintainers: http://www.nslu2-linux.org/
*
* Fixed missing init_time in MACHINE_START kas11 10/22/04
* Changed to conform to new style __init ixdp425 kas11 10/22/04
*/
#include <linux/kernel.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
static struct flash_platform_data nslu2_flash_data = {
.map_name = "cfi_probe",
.width = 2,
};
static struct resource nslu2_flash_resource = {
.start = NSLU2_FLASH_BASE,
.end = NSLU2_FLASH_BASE + NSLU2_FLASH_SIZE,
.flags = IORESOURCE_MEM,
};
static struct platform_device nslu2_flash = {
.name = "IXP4XX-Flash",
.id = 0,
.dev.platform_data = &nslu2_flash_data,
.num_resources = 1,
.resource = &nslu2_flash_resource,
};
static struct ixp4xx_i2c_pins nslu2_i2c_gpio_pins = {
.sda_pin = NSLU2_SDA_PIN,
.scl_pin = NSLU2_SCL_PIN,
};
static struct platform_device nslu2_i2c_controller = {
.name = "IXP4XX-I2C",
.id = 0,
.dev.platform_data = &nslu2_i2c_gpio_pins,
.num_resources = 0,
};
static struct resource nslu2_uart_resources[] = {
{
.start = IXP4XX_UART1_BASE_PHYS,
.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
},
{
.start = IXP4XX_UART2_BASE_PHYS,
.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
.flags = IORESOURCE_MEM,
}
};
static struct plat_serial8250_port nslu2_uart_data[] = {
{
.mapbase = IXP4XX_UART1_BASE_PHYS,
.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART1,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{
.mapbase = IXP4XX_UART2_BASE_PHYS,
.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
.irq = IRQ_IXP4XX_UART2,
.flags = UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.regshift = 2,
.uartclk = IXP4XX_UART_XTAL,
},
{ }
};
static struct platform_device nslu2_uart = {
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev.platform_data = nslu2_uart_data,
.num_resources = 2,
.resource = nslu2_uart_resources,
};
static struct platform_device *nslu2_devices[] __initdata = {
&nslu2_i2c_controller,
&nslu2_flash,
&nslu2_uart,
};
static void nslu2_power_off(void)
{
/* This causes the box to drop the power and go dead. */
/* enable the pwr cntl gpio */
gpio_line_config(NSLU2_PO_GPIO, IXP4XX_GPIO_OUT);
/* do the deed */
gpio_line_set(NSLU2_PO_GPIO, IXP4XX_GPIO_HIGH);
}
static void __init nslu2_init(void)
{
ixp4xx_sys_init();
pm_power_off = nslu2_power_off;
platform_add_devices(nslu2_devices, ARRAY_SIZE(nslu2_devices));
}
MACHINE_START(NSLU2, "Linksys NSLU2")
/* Maintainer: www.nslu2-linux.org */
.phys_ram = PHYS_OFFSET,
.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.map_io = ixp4xx_map_io,
.init_irq = ixp4xx_init_irq,
.timer = &ixp4xx_timer,
.init_machine = nslu2_init,
MACHINE_END
arch/arm/mach-omap1/Kconfig
浏览文件 @ a46699c9
......@@ -6,10 +6,10 @@ config ARCH_OMAP730
bool "OMAP730 Based System"
select ARCH_OMAP_OTG
config ARCH_OMAP1510
config ARCH_OMAP15XX
depends on ARCH_OMAP1
default y
bool "OMAP1510 Based System"
bool "OMAP15xx Based System"
config ARCH_OMAP16XX
depends on ARCH_OMAP1
......@@ -21,7 +21,7 @@ comment "OMAP Board Type"
config MACH_OMAP_INNOVATOR
bool "TI Innovator"
depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX)
depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
help
TI OMAP 1510 or 1610 Innovator board support. Say Y here if you
have such a board.
......@@ -64,20 +64,30 @@ config MACH_OMAP_PERSEUS2
config MACH_VOICEBLUE
bool "Voiceblue"
depends on ARCH_OMAP1 && ARCH_OMAP1510
depends on ARCH_OMAP1 && ARCH_OMAP15XX
help
Support for Voiceblue GSM/VoIP gateway. Say Y here if you have
such a board.
config MACH_NETSTAR
bool "NetStar"
depends on ARCH_OMAP1 && ARCH_OMAP1510
depends on ARCH_OMAP1 && ARCH_OMAP15XX
help
Support for NetStar PBX. Say Y here if you have such a board.
config MACH_OMAP_PALMTE
bool "Palm Tungsten E"
depends on ARCH_OMAP1 && ARCH_OMAP15XX
help
Support for the Palm Tungsten E PDA. Currently only the LCD panel
is supported. To boot the kernel, you'll need a PalmOS compatible
bootloader; check out http://palmtelinux.sourceforge.net for more
informations.
Say Y here if you have such a PDA, say NO otherwise.
config MACH_OMAP_GENERIC
bool "Generic OMAP board"
depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX)
depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX)
help
Support for generic OMAP-1510, 1610 or 1710 board with
no FPGA. Can be used as template for porting Linux to
......@@ -121,32 +131,32 @@ config OMAP_ARM_182MHZ
config OMAP_ARM_168MHZ
bool "OMAP ARM 168 MHz CPU"
depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730)
depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
help
Enable 168MHz clock for OMAP CPU. If unsure, say N.
config OMAP_ARM_150MHZ
bool "OMAP ARM 150 MHz CPU"
depends on ARCH_OMAP1 && ARCH_OMAP1510
depends on ARCH_OMAP1 && ARCH_OMAP15XX
help
Enable 150MHz clock for OMAP CPU. If unsure, say N.
config OMAP_ARM_120MHZ
bool "OMAP ARM 120 MHz CPU"
depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730)
depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
help
Enable 120MHz clock for OMAP CPU. If unsure, say N.
config OMAP_ARM_60MHZ
bool "OMAP ARM 60 MHz CPU"
depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730)
depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
default y
help
Enable 60MHz clock for OMAP CPU. If unsure, say Y.
config OMAP_ARM_30MHZ
bool "OMAP ARM 30 MHz CPU"
depends on ARCH_OMAP1 && (ARCH_OMAP1510 || ARCH_OMAP16XX || ARCH_OMAP730)
depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730)
help
Enable 30MHz clock for OMAP CPU. If unsure, say N.
arch/arm/mach-omap1/Makefile
浏览文件 @ a46699c9
......@@ -3,7 +3,7 @@
#
# Common support
obj-y := io.o id.o irq.o time.o serial.o devices.o
obj-y := io.o id.o clock.o irq.o time.o mux.o serial.o devices.o
led-y := leds.o
# Specific board support
......@@ -15,8 +15,9 @@ obj-$(CONFIG_MACH_OMAP_OSK) += board-osk.o
obj-$(CONFIG_MACH_OMAP_H3) += board-h3.o
obj-$(CONFIG_MACH_VOICEBLUE) += board-voiceblue.o
obj-$(CONFIG_MACH_NETSTAR) += board-netstar.o
obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o
ifeq ($(CONFIG_ARCH_OMAP1510),y)
ifeq ($(CONFIG_ARCH_OMAP15XX),y)
# Innovator-1510 FPGA
obj-$(CONFIG_MACH_OMAP_INNOVATOR) += fpga.o
endif
......
arch/arm/mach-omap1/board-generic.c
浏览文件 @ a46699c9
......@@ -15,7 +15,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
......@@ -28,8 +28,6 @@
#include <asm/arch/board.h>
#include <asm/arch/common.h>
static int __initdata generic_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
static void __init omap_generic_init_irq(void)
{
omap_init_irq();
......@@ -37,7 +35,7 @@ static void __init omap_generic_init_irq(void)
/* assume no Mini-AB port */
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
static struct omap_usb_config generic1510_usb_config __initdata = {
.register_host = 1,
.register_dev = 1,
......@@ -76,21 +74,19 @@ static struct omap_mmc_config generic_mmc_config __initdata = {
#endif
static struct omap_uart_config generic_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_board_config_kernel generic_config[] = {
{ OMAP_TAG_USB, NULL },
{ OMAP_TAG_MMC, &generic_mmc_config },
{ OMAP_TAG_UART, &generic_uart_config },
};
static void __init omap_generic_init(void)
{
const struct omap_uart_config *uart_conf;
/*
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on
* if not needed.
*/
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
generic_config[0].data = &generic1510_usb_config;
}
......@@ -101,20 +97,9 @@ static void __init omap_generic_init(void)
}
#endif
uart_conf = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
if (uart_conf != NULL) {
unsigned int enabled_ports, i;
enabled_ports = uart_conf->enabled_uarts;
for (i = 0; i < 3; i++) {
if (!(enabled_ports & (1 << i)))
generic_serial_ports[i] = 0;
}
}
omap_board_config = generic_config;
omap_board_config_size = ARRAY_SIZE(generic_config);
omap_serial_init(generic_serial_ports);
omap_serial_init();
}
static void __init omap_generic_map_io(void)
......
arch/arm/mach-omap1/board-h2.c
浏览文件 @ a46699c9
......@@ -40,8 +40,6 @@
extern int omap_gpio_init(void);
static int __initdata h2_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
static struct mtd_partition h2_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
......@@ -160,9 +158,20 @@ static struct omap_mmc_config h2_mmc_config __initdata = {
},
};
static struct omap_uart_config h2_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_lcd_config h2_lcd_config __initdata = {
.panel_name = "h2",
.ctrl_name = "internal",
};
static struct omap_board_config_kernel h2_config[] = {
{ OMAP_TAG_USB, &h2_usb_config },
{ OMAP_TAG_MMC, &h2_mmc_config },
{ OMAP_TAG_UART, &h2_uart_config },
{ OMAP_TAG_LCD, &h2_lcd_config },
};
static void __init h2_init(void)
......@@ -180,12 +189,12 @@ static void __init h2_init(void)
platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
omap_board_config = h2_config;
omap_board_config_size = ARRAY_SIZE(h2_config);
omap_serial_init();
}
static void __init h2_map_io(void)
{
omap_map_common_io();
omap_serial_init(h2_serial_ports);
}
MACHINE_START(OMAP_H2, "TI-H2")
......
arch/arm/mach-omap1/board-h3.c
浏览文件 @ a46699c9
......@@ -41,8 +41,6 @@
extern int omap_gpio_init(void);
static int __initdata h3_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
static struct mtd_partition h3_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
......@@ -168,9 +166,20 @@ static struct omap_mmc_config h3_mmc_config __initdata = {
},
};
static struct omap_uart_config h3_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_lcd_config h3_lcd_config __initdata = {
.panel_name = "h3",
.ctrl_name = "internal",
};
static struct omap_board_config_kernel h3_config[] = {
{ OMAP_TAG_USB, &h3_usb_config },
{ OMAP_TAG_MMC, &h3_mmc_config },
{ OMAP_TAG_USB, &h3_usb_config },
{ OMAP_TAG_MMC, &h3_mmc_config },
{ OMAP_TAG_UART, &h3_uart_config },
{ OMAP_TAG_LCD, &h3_lcd_config },
};
static void __init h3_init(void)
......@@ -180,6 +189,7 @@ static void __init h3_init(void)
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
omap_board_config = h3_config;
omap_board_config_size = ARRAY_SIZE(h3_config);
omap_serial_init();
}
static void __init h3_init_smc91x(void)
......@@ -201,7 +211,6 @@ void h3_init_irq(void)
static void __init h3_map_io(void)
{
omap_map_common_io();
omap_serial_init(h3_serial_ports);
}
MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
......
arch/arm/mach-omap1/board-innovator.c
浏览文件 @ a46699c9
......@@ -36,8 +36,6 @@
#include <asm/arch/usb.h>
#include <asm/arch/common.h>
static int __initdata innovator_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
static struct mtd_partition innovator_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
......@@ -99,7 +97,7 @@ static struct platform_device innovator_flash_device = {
.resource = &innovator_flash_resource,
};
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc innovator1510_io_desc[] __initdata = {
......@@ -136,7 +134,7 @@ static struct platform_device *innovator1510_devices[] __initdata = {
&innovator1510_smc91x_device,
};
#endif /* CONFIG_ARCH_OMAP1510 */
#endif /* CONFIG_ARCH_OMAP15XX */
#ifdef CONFIG_ARCH_OMAP16XX
......@@ -185,7 +183,7 @@ void innovator_init_irq(void)
{
omap_init_irq();
omap_gpio_init();
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
omap1510_fpga_init_irq();
}
......@@ -193,7 +191,7 @@ void innovator_init_irq(void)
innovator_init_smc91x();
}
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
static struct omap_usb_config innovator1510_usb_config __initdata = {
/* for bundled non-standard host and peripheral cables */
.hmc_mode = 4,
......@@ -205,6 +203,11 @@ static struct omap_usb_config innovator1510_usb_config __initdata = {
.register_dev = 1,
.pins[0] = 2,
};
static struct omap_lcd_config innovator1510_lcd_config __initdata = {
.panel_name = "inn1510",
.ctrl_name = "internal",
};
#endif
#ifdef CONFIG_ARCH_OMAP16XX
......@@ -222,6 +225,11 @@ static struct omap_usb_config h2_usb_config __initdata = {
.pins[1] = 3,
};
static struct omap_lcd_config innovator1610_lcd_config __initdata = {
.panel_name = "inn1610",
.ctrl_name = "internal",
};
#endif
static struct omap_mmc_config innovator_mmc_config __initdata = {
......@@ -234,14 +242,20 @@ static struct omap_mmc_config innovator_mmc_config __initdata = {
},
};
static struct omap_uart_config innovator_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_board_config_kernel innovator_config[] = {
{ OMAP_TAG_USB, NULL },
{ OMAP_TAG_LCD, NULL },
{ OMAP_TAG_MMC, &innovator_mmc_config },
{ OMAP_TAG_UART, &innovator_uart_config },
};
static void __init innovator_init(void)
{
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
platform_add_devices(innovator1510_devices, ARRAY_SIZE(innovator1510_devices));
}
......@@ -252,23 +266,28 @@ static void __init innovator_init(void)
}
#endif
#ifdef CONFIG_ARCH_OMAP1510
if (cpu_is_omap1510())
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
innovator_config[0].data = &innovator1510_usb_config;
innovator_config[1].data = &innovator1510_lcd_config;
}
#endif
#ifdef CONFIG_ARCH_OMAP16XX
if (cpu_is_omap1610())
if (cpu_is_omap1610()) {
innovator_config[0].data = &h2_usb_config;
innovator_config[1].data = &innovator1610_lcd_config;
}
#endif
omap_board_config = innovator_config;
omap_board_config_size = ARRAY_SIZE(innovator_config);
omap_serial_init();
}
static void __init innovator_map_io(void)
{
omap_map_common_io();
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
udelay(10); /* Delay needed for FPGA */
......@@ -280,7 +299,6 @@ static void __init innovator_map_io(void)
fpga_read(OMAP1510_FPGA_BOARD_REV));
}
#endif
omap_serial_init(innovator_serial_ports);
}
MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
......
arch/arm/mach-omap1/board-netstar.c
浏览文件 @ a46699c9
......@@ -55,6 +55,14 @@ static struct platform_device *netstar_devices[] __initdata = {
&netstar_smc91x_device,
};
static struct omap_uart_config netstar_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_board_config_kernel netstar_config[] = {
{ OMAP_TAG_UART, &netstar_uart_config },
};
static void __init netstar_init_irq(void)
{
omap_init_irq();
......@@ -92,14 +100,15 @@ static void __init netstar_init(void)
/* Switch off red LED */
omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
omap_writeb(0x80, OMAP_LPG1_LCR);
}
static int __initdata omap_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
omap_board_config = netstar_config;
omap_board_config_size = ARRAY_SIZE(netstar_config);
omap_serial_init();
}
static void __init netstar_map_io(void)
{
omap_map_common_io();
omap_serial_init(omap_serial_ports);
}
#define MACHINE_PANICED 1
......
arch/arm/mach-omap1/board-osk.c
浏览文件 @ a46699c9
......@@ -46,8 +46,6 @@
#include <asm/arch/tc.h>
#include <asm/arch/common.h>
static int __initdata osk_serial_ports[OMAP_MAX_NR_PORTS] = {1, 0, 0};
static struct mtd_partition osk_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
......@@ -155,7 +153,7 @@ static void __init osk_init_smc91x(void)
}
/* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */
EMIFS_CCS(1) |= 0x2;
EMIFS_CCS(1) |= 0x3;
}
static void __init osk_init_cf(void)
......@@ -193,8 +191,19 @@ static struct omap_usb_config osk_usb_config __initdata = {
.pins[0] = 2,
};
static struct omap_uart_config osk_uart_config __initdata = {
.enabled_uarts = (1 << 0),
};
static struct omap_lcd_config osk_lcd_config __initdata = {
.panel_name = "osk",
.ctrl_name = "internal",
};
static struct omap_board_config_kernel osk_config[] = {
{ OMAP_TAG_USB, &osk_usb_config },
{ OMAP_TAG_UART, &osk_uart_config },
{ OMAP_TAG_LCD, &osk_lcd_config },
};
#ifdef CONFIG_OMAP_OSK_MISTRAL
......@@ -254,13 +263,13 @@ static void __init osk_init(void)
omap_board_config_size = ARRAY_SIZE(osk_config);
USB_TRANSCEIVER_CTRL_REG |= (3 << 1);
omap_serial_init();
osk_mistral_init();
}
static void __init osk_map_io(void)
{
omap_map_common_io();
omap_serial_init(osk_serial_ports);
}
MACHINE_START(OMAP_OSK, "TI-OSK")
......
arch/arm/mach-omap1/board-palmte.c 0 → 100644
浏览文件 @ a46699c9
/*
* linux/arch/arm/mach-omap1/board-palmte.c
*
* Modified from board-generic.c
*
* Support for the Palm Tungsten E PDA.
*
* Original version : Laurent Gonzalez
*
* Maintainters : http://palmtelinux.sf.net
* palmtelinux-developpers@lists.sf.net
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/notifier.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mux.h>
#include <asm/arch/usb.h>
#include <asm/arch/board.h>
#include <asm/arch/common.h>
#include <asm/hardware/clock.h>
static void __init omap_generic_init_irq(void)
{
omap_init_irq();
}
static struct omap_usb_config palmte_usb_config __initdata = {
.register_dev = 1,
.hmc_mode = 0,
.pins[0] = 3,
};
static struct omap_mmc_config palmte_mmc_config __initdata = {
.mmc [0] = {
.enabled = 1,
.wire4 = 1,
.wp_pin = OMAP_MPUIO(3),
.power_pin = -1,
.switch_pin = -1,
},
};
static struct omap_lcd_config palmte_lcd_config __initdata = {
.panel_name = "palmte",
.ctrl_name = "internal",
};
static struct omap_board_config_kernel palmte_config[] = {
{ OMAP_TAG_USB, &palmte_usb_config },
{ OMAP_TAG_MMC, &palmte_mmc_config },
{ OMAP_TAG_LCD, &palmte_lcd_config },
};
static void __init omap_generic_init(void)
{
omap_board_config = palmte_config;
omap_board_config_size = ARRAY_SIZE(palmte_config);
}
static void __init omap_generic_map_io(void)
{
omap_map_common_io();
}
MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
.phys_ram = 0x10000000,
.phys_io = 0xfff00000,
.io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
.boot_params = 0x10000100,
.map_io = omap_generic_map_io,
.init_irq = omap_generic_init_irq,
.init_machine = omap_generic_init,
.timer = &omap_timer,
MACHINE_END
arch/arm/mach-omap1/board-perseus2.c
浏览文件 @ a46699c9
......@@ -29,6 +29,7 @@
#include <asm/arch/mux.h>
#include <asm/arch/fpga.h>
#include <asm/arch/common.h>
#include <asm/arch/board.h>
static struct resource smc91x_resources[] = {
[0] = {
......@@ -43,8 +44,6 @@ static struct resource smc91x_resources[] = {
},
};
static int __initdata p2_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 0};
static struct mtd_partition p2_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
......@@ -111,9 +110,27 @@ static struct platform_device *devices[] __initdata = {
&smc91x_device,
};
static struct omap_uart_config perseus2_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1)),
};
static struct omap_lcd_config perseus2_lcd_config __initdata = {
.panel_name = "p2",
.ctrl_name = "internal",
};
static struct omap_board_config_kernel perseus2_config[] = {
{ OMAP_TAG_UART, &perseus2_uart_config },
{ OMAP_TAG_LCD, &perseus2_lcd_config },
};
static void __init omap_perseus2_init(void)
{
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
omap_board_config = perseus2_config;
omap_board_config_size = ARRAY_SIZE(perseus2_config);
omap_serial_init();
}
static void __init perseus2_init_smc91x(void)
......@@ -131,7 +148,6 @@ void omap_perseus2_init_irq(void)
omap_gpio_init();
perseus2_init_smc91x();
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc omap_perseus2_io_desc[] __initdata = {
{
......@@ -179,7 +195,6 @@ static void __init omap_perseus2_map_io(void)
* It is used as the Ethernet controller interrupt
*/
omap_writel(omap_readl(OMAP730_IO_CONF_9) & 0x1FFFFFFF, OMAP730_IO_CONF_9);
omap_serial_init(p2_serial_ports);
}
MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
......
arch/arm/mach-omap1/board-voiceblue.c
浏览文件 @ a46699c9
......@@ -150,9 +150,14 @@ static struct omap_mmc_config voiceblue_mmc_config __initdata = {
},
};
static struct omap_uart_config voiceblue_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_board_config_kernel voiceblue_config[] = {
{ OMAP_TAG_USB, &voiceblue_usb_config },
{ OMAP_TAG_MMC, &voiceblue_mmc_config },
{ OMAP_TAG_UART, &voiceblue_uart_config },
};
static void __init voiceblue_init_irq(void)
......@@ -191,6 +196,7 @@ static void __init voiceblue_init(void)
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
omap_board_config = voiceblue_config;
omap_board_config_size = ARRAY_SIZE(voiceblue_config);
omap_serial_init();
/* There is a good chance board is going up, so enable power LED
* (it is connected through invertor) */
......@@ -198,12 +204,9 @@ static void __init voiceblue_init(void)
omap_writeb(0x00, OMAP_LPG1_PMR); /* Disable clock */
}
static int __initdata omap_serial_ports[OMAP_MAX_NR_PORTS] = {1, 1, 1};
static void __init voiceblue_map_io(void)
{
omap_map_common_io();
omap_serial_init(omap_serial_ports);
}
#define MACHINE_PANICED 1
......
arch/arm/mach-omap1/clock.c 0 → 100644
浏览文件 @ a46699c9
/*
* linux/arch/arm/mach-omap1/clock.c
*
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
*
* Modified to use omap shared clock framework by
* Tony Lindgren <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <asm/io.h>
#include <asm/hardware/clock.h>
#include <asm/arch/usb.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
#include "clock.h"
__u32 arm_idlect1_mask;
/*-------------------------------------------------------------------------
* Omap1 specific clock functions
*-------------------------------------------------------------------------*/
static void omap1_watchdog_recalc(struct clk * clk)
{
clk->rate = clk->parent->rate / 14;
}
static void omap1_uart_recalc(struct clk * clk)
{
unsigned int val = omap_readl(clk->enable_reg);
if (val & clk->enable_bit)
clk->rate = 48000000;
else
clk->rate = 12000000;
}
static int omap1_clk_enable_dsp_domain(struct clk *clk)
{
int retval;
retval = omap1_clk_use(&api_ck.clk);
if (!retval) {
retval = omap1_clk_enable(clk);
omap1_clk_unuse(&api_ck.clk);
}
return retval;
}
static void omap1_clk_disable_dsp_domain(struct clk *clk)
{
if (omap1_clk_use(&api_ck.clk) == 0) {
omap1_clk_disable(clk);
omap1_clk_unuse(&api_ck.clk);
}
}
static int omap1_clk_enable_uart_functional(struct clk *clk)
{
int ret;
struct uart_clk *uclk;
ret = omap1_clk_enable(clk);
if (ret == 0) {
/* Set smart idle acknowledgement mode */
uclk = (struct uart_clk *)clk;
omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
uclk->sysc_addr);
}
return ret;
}
static void omap1_clk_disable_uart_functional(struct clk *clk)
{
struct uart_clk *uclk;
/* Set force idle acknowledgement mode */
uclk = (struct uart_clk *)clk;
omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
omap1_clk_disable(clk);
}
static void omap1_clk_allow_idle(struct clk *clk)
{
struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
if (!(clk->flags & CLOCK_IDLE_CONTROL))
return;
if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
arm_idlect1_mask |= 1 << iclk->idlect_shift;
}
static void omap1_clk_deny_idle(struct clk *clk)
{
struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
if (!(clk->flags & CLOCK_IDLE_CONTROL))
return;
if (iclk->no_idle_count++ == 0)
arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
}
static __u16 verify_ckctl_value(__u16 newval)
{
/* This function checks for following limitations set
* by the hardware (all conditions must be true):
* DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
* ARM_CK >= TC_CK
* DSP_CK >= TC_CK
* DSPMMU_CK >= TC_CK
*
* In addition following rules are enforced:
* LCD_CK <= TC_CK
* ARMPER_CK <= TC_CK
*
* However, maximum frequencies are not checked for!
*/
__u8 per_exp;
__u8 lcd_exp;
__u8 arm_exp;
__u8 dsp_exp;
__u8 tc_exp;
__u8 dspmmu_exp;
per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
if (dspmmu_exp < dsp_exp)
dspmmu_exp = dsp_exp;
if (dspmmu_exp > dsp_exp+1)
dspmmu_exp = dsp_exp+1;
if (tc_exp < arm_exp)
tc_exp = arm_exp;
if (tc_exp < dspmmu_exp)
tc_exp = dspmmu_exp;
if (tc_exp > lcd_exp)
lcd_exp = tc_exp;
if (tc_exp > per_exp)
per_exp = tc_exp;
newval &= 0xf000;
newval |= per_exp << CKCTL_PERDIV_OFFSET;
newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
newval |= tc_exp << CKCTL_TCDIV_OFFSET;
newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
return newval;
}
static int calc_dsor_exp(struct clk *clk, unsigned long rate)
{
/* Note: If target frequency is too low, this function will return 4,
* which is invalid value. Caller must check for this value and act
* accordingly.
*
* Note: This function does not check for following limitations set
* by the hardware (all conditions must be true):
* DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
* ARM_CK >= TC_CK
* DSP_CK >= TC_CK
* DSPMMU_CK >= TC_CK
*/
unsigned long realrate;
struct clk * parent;
unsigned dsor_exp;
if (unlikely(!(clk->flags & RATE_CKCTL)))
return -EINVAL;
parent = clk->parent;
if (unlikely(parent == 0))
return -EIO;
realrate = parent->rate;
for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
if (realrate <= rate)
break;
realrate /= 2;
}
return dsor_exp;
}
static void omap1_ckctl_recalc(struct clk * clk)
{
int dsor;
/* Calculate divisor encoded as 2-bit exponent */
dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
if (unlikely(clk->rate == clk->parent->rate / dsor))
return; /* No change, quick exit */
clk->rate = clk->parent->rate / dsor;
if (unlikely(clk->flags & RATE_PROPAGATES))
propagate_rate(clk);
}
static void omap1_ckctl_recalc_dsp_domain(struct clk * clk)
{
int dsor;
/* Calculate divisor encoded as 2-bit exponent
*
* The clock control bits are in DSP domain,
* so api_ck is needed for access.
* Note that DSP_CKCTL virt addr = phys addr, so
* we must use __raw_readw() instead of omap_readw().
*/
omap1_clk_use(&api_ck.clk);
dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
omap1_clk_unuse(&api_ck.clk);
if (unlikely(clk->rate == clk->parent->rate / dsor))
return; /* No change, quick exit */
clk->rate = clk->parent->rate / dsor;
if (unlikely(clk->flags & RATE_PROPAGATES))
propagate_rate(clk);
}
/* MPU virtual clock functions */
static int omap1_select_table_rate(struct clk * clk, unsigned long rate)
{
/* Find the highest supported frequency <= rate and switch to it */
struct mpu_rate * ptr;
if (clk != &virtual_ck_mpu)
return -EINVAL;
for (ptr = rate_table; ptr->rate; ptr++) {
if (ptr->xtal != ck_ref.rate)
continue;
/* DPLL1 cannot be reprogrammed without risking system crash */
if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate)
continue;
/* Can check only after xtal frequency check */
if (ptr->rate <= rate)
break;
}
if (!ptr->rate)
return -EINVAL;
/*
* In most cases we should not need to reprogram DPLL.
* Reprogramming the DPLL is tricky, it must be done from SRAM.
*/
omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
ck_dpll1.rate = ptr->pll_rate;
propagate_rate(&ck_dpll1);
return 0;
}
static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
{
int ret = -EINVAL;
int dsor_exp;
__u16 regval;
if (clk->flags & RATE_CKCTL) {
dsor_exp = calc_dsor_exp(clk, rate);
if (dsor_exp > 3)
dsor_exp = -EINVAL;
if (dsor_exp < 0)
return dsor_exp;
regval = __raw_readw(DSP_CKCTL);
regval &= ~(3 << clk->rate_offset);
regval |= dsor_exp << clk->rate_offset;
__raw_writew(regval, DSP_CKCTL);
clk->rate = clk->parent->rate / (1 << dsor_exp);
ret = 0;
}
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
propagate_rate(clk);
return ret;
}
static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate)
{
/* Find the highest supported frequency <= rate */
struct mpu_rate * ptr;
long highest_rate;
if (clk != &virtual_ck_mpu)
return -EINVAL;
highest_rate = -EINVAL;
for (ptr = rate_table; ptr->rate; ptr++) {
if (ptr->xtal != ck_ref.rate)
continue;
highest_rate = ptr->rate;
/* Can check only after xtal frequency check */
if (ptr->rate <= rate)
break;
}
return highest_rate;
}
static unsigned calc_ext_dsor(unsigned long rate)
{
unsigned dsor;
/* MCLK and BCLK divisor selection is not linear:
* freq = 96MHz / dsor
*
* RATIO_SEL range: dsor <-> RATIO_SEL
* 0..6: (RATIO_SEL+2) <-> (dsor-2)
* 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
* Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
* can not be used.
*/
for (dsor = 2; dsor < 96; ++dsor) {
if ((dsor & 1) && dsor > 8)
continue;
if (rate >= 96000000 / dsor)
break;
}
return dsor;
}
/* Only needed on 1510 */
static int omap1_set_uart_rate(struct clk * clk, unsigned long rate)
{
unsigned int val;
val = omap_readl(clk->enable_reg);
if (rate == 12000000)
val &= ~(1 << clk->enable_bit);
else if (rate == 48000000)
val |= (1 << clk->enable_bit);
else
return -EINVAL;
omap_writel(val, clk->enable_reg);
clk->rate = rate;
return 0;
}
/* External clock (MCLK & BCLK) functions */
static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate)
{
unsigned dsor;
__u16 ratio_bits;
dsor = calc_ext_dsor(rate);
clk->rate = 96000000 / dsor;
if (dsor > 8)
ratio_bits = ((dsor - 8) / 2 + 6) << 2;
else
ratio_bits = (dsor - 2) << 2;
ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd;
omap_writew(ratio_bits, clk->enable_reg);
return 0;
}
static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate)
{
return 96000000 / calc_ext_dsor(rate);
}
static void omap1_init_ext_clk(struct clk * clk)
{
unsigned dsor;
__u16 ratio_bits;
/* Determine current rate and ensure clock is based on 96MHz APLL */
ratio_bits = omap_readw(clk->enable_reg) & ~1;
omap_writew(ratio_bits, clk->enable_reg);
ratio_bits = (ratio_bits & 0xfc) >> 2;
if (ratio_bits > 6)
dsor = (ratio_bits - 6) * 2 + 8;
else
dsor = ratio_bits + 2;
clk-> rate = 96000000 / dsor;
}
static int omap1_clk_use(struct clk *clk)
{
int ret = 0;
if (clk->usecount++ == 0) {
if (likely(clk->parent)) {
ret = omap1_clk_use(clk->parent);
if (unlikely(ret != 0)) {
clk->usecount--;
return ret;
}
if (clk->flags & CLOCK_NO_IDLE_PARENT)
if (!cpu_is_omap24xx())
omap1_clk_deny_idle(clk->parent);
}
ret = clk->enable(clk);
if (unlikely(ret != 0) && clk->parent) {
omap1_clk_unuse(clk->parent);
clk->usecount--;
}
}
return ret;
}
static void omap1_clk_unuse(struct clk *clk)
{
if (clk->usecount > 0 && !(--clk->usecount)) {
clk->disable(clk);
if (likely(clk->parent)) {
omap1_clk_unuse(clk->parent);
if (clk->flags & CLOCK_NO_IDLE_PARENT)
if (!cpu_is_omap24xx())
omap1_clk_allow_idle(clk->parent);
}
}
}
static int omap1_clk_enable(struct clk *clk)
{
__u16 regval16;
__u32 regval32;
if (clk->flags & ALWAYS_ENABLED)
return 0;
if (unlikely(clk->enable_reg == 0)) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
clk->name);
return 0;
}
if (clk->flags & ENABLE_REG_32BIT) {
if (clk->flags & VIRTUAL_IO_ADDRESS) {
regval32 = __raw_readl(clk->enable_reg);
regval32 |= (1 << clk->enable_bit);
__raw_writel(regval32, clk->enable_reg);
} else {
regval32 = omap_readl(clk->enable_reg);
regval32 |= (1 << clk->enable_bit);
omap_writel(regval32, clk->enable_reg);
}
} else {
if (clk->flags & VIRTUAL_IO_ADDRESS) {
regval16 = __raw_readw(clk->enable_reg);
regval16 |= (1 << clk->enable_bit);
__raw_writew(regval16, clk->enable_reg);
} else {
regval16 = omap_readw(clk->enable_reg);
regval16 |= (1 << clk->enable_bit);
omap_writew(regval16, clk->enable_reg);
}
}
return 0;
}
static void omap1_clk_disable(struct clk *clk)
{
__u16 regval16;
__u32 regval32;
if (clk->enable_reg == 0)
return;
if (clk->flags & ENABLE_REG_32BIT) {
if (clk->flags & VIRTUAL_IO_ADDRESS) {
regval32 = __raw_readl(clk->enable_reg);
regval32 &= ~(1 << clk->enable_bit);
__raw_writel(regval32, clk->enable_reg);
} else {
regval32 = omap_readl(clk->enable_reg);
regval32 &= ~(1 << clk->enable_bit);
omap_writel(regval32, clk->enable_reg);
}
} else {
if (clk->flags & VIRTUAL_IO_ADDRESS) {
regval16 = __raw_readw(clk->enable_reg);
regval16 &= ~(1 << clk->enable_bit);
__raw_writew(regval16, clk->enable_reg);
} else {
regval16 = omap_readw(clk->enable_reg);
regval16 &= ~(1 << clk->enable_bit);
omap_writew(regval16, clk->enable_reg);
}
}
}
static long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
{
int dsor_exp;
if (clk->flags & RATE_FIXED)
return clk->rate;
if (clk->flags & RATE_CKCTL) {
dsor_exp = calc_dsor_exp(clk, rate);
if (dsor_exp < 0)
return dsor_exp;
if (dsor_exp > 3)
dsor_exp = 3;
return clk->parent->rate / (1 << dsor_exp);
}
if(clk->round_rate != 0)
return clk->round_rate(clk, rate);
return clk->rate;
}
static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
{
int ret = -EINVAL;
int dsor_exp;
__u16 regval;
if (clk->set_rate)
ret = clk->set_rate(clk, rate);
else if (clk->flags & RATE_CKCTL) {
dsor_exp = calc_dsor_exp(clk, rate);
if (dsor_exp > 3)
dsor_exp = -EINVAL;
if (dsor_exp < 0)
return dsor_exp;
regval = omap_readw(ARM_CKCTL);
regval &= ~(3 << clk->rate_offset);
regval |= dsor_exp << clk->rate_offset;
regval = verify_ckctl_value(regval);
omap_writew(regval, ARM_CKCTL);
clk->rate = clk->parent->rate / (1 << dsor_exp);
ret = 0;
}
if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
propagate_rate(clk);
return ret;
}
/*-------------------------------------------------------------------------
* Omap1 clock reset and init functions
*-------------------------------------------------------------------------*/
#ifdef CONFIG_OMAP_RESET_CLOCKS
/*
* Resets some clocks that may be left on from bootloader,
* but leaves serial clocks on. See also omap_late_clk_reset().
*/
static inline void omap1_early_clk_reset(void)
{
//omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
}
static int __init omap1_late_clk_reset(void)
{
/* Turn off all unused clocks */
struct clk *p;
__u32 regval32;
/* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4);
omap_writew(regval32, SOFT_REQ_REG);
omap_writew(0, SOFT_REQ_REG2);
list_for_each_entry(p, &clocks, node) {
if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) ||
p->enable_reg == 0)
continue;
/* Clocks in the DSP domain need api_ck. Just assume bootloader
* has not enabled any DSP clocks */
if ((u32)p->enable_reg == DSP_IDLECT2) {
printk(KERN_INFO "Skipping reset check for DSP domain "
"clock \"%s\"\n", p->name);
continue;
}
/* Is the clock already disabled? */
if (p->flags & ENABLE_REG_32BIT) {
if (p->flags & VIRTUAL_IO_ADDRESS)
regval32 = __raw_readl(p->enable_reg);
else
regval32 = omap_readl(p->enable_reg);
} else {
if (p->flags & VIRTUAL_IO_ADDRESS)
regval32 = __raw_readw(p->enable_reg);
else
regval32 = omap_readw(p->enable_reg);
}
if ((regval32 & (1 << p->enable_bit)) == 0)
continue;
/* FIXME: This clock seems to be necessary but no-one
* has asked for its activation. */
if (p == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
|| p == &ck_dpll1out.clk // FIX: SoSSI, SSR
|| p == &arm_gpio_ck // FIX: GPIO code for 1510
) {
printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
p->name);
continue;
}
printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name);
p->disable(p);
printk(" done\n");
}
return 0;
}
late_initcall(omap1_late_clk_reset);
#else
#define omap1_early_clk_reset() {}
#endif
static struct clk_functions omap1_clk_functions = {
.clk_use = omap1_clk_use,
.clk_unuse = omap1_clk_unuse,
.clk_round_rate = omap1_clk_round_rate,
.clk_set_rate = omap1_clk_set_rate,
};
int __init omap1_clk_init(void)
{
struct clk ** clkp;
const struct omap_clock_config *info;
int crystal_type = 0; /* Default 12 MHz */
omap1_early_clk_reset();
clk_init(&omap1_clk_functions);
/* By default all idlect1 clocks are allowed to idle */
arm_idlect1_mask = ~0;
for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) {
if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) {
clk_register(*clkp);
continue;
}
if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) {
clk_register(*clkp);
continue;
}
if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) {
clk_register(*clkp);
continue;
}
}
info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
if (info != NULL) {
if (!cpu_is_omap1510())
crystal_type = info->system_clock_type;
}
#if defined(CONFIG_ARCH_OMAP730)
ck_ref.rate = 13000000;
#elif defined(CONFIG_ARCH_OMAP16XX)
if (crystal_type == 2)
ck_ref.rate = 19200000;
#endif
printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
omap_readw(ARM_CKCTL));
/* We want to be in syncronous scalable mode */
omap_writew(0x1000, ARM_SYSST);
#ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
/* Use values set by bootloader. Determine PLL rate and recalculate
* dependent clocks as if kernel had changed PLL or divisors.
*/
{
unsigned pll_ctl_val = omap_readw(DPLL_CTL);
ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
if (pll_ctl_val & 0x10) {
/* PLL enabled, apply multiplier and divisor */
if (pll_ctl_val & 0xf80)
ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
} else {
/* PLL disabled, apply bypass divisor */
switch (pll_ctl_val & 0xc) {
case 0:
break;
case 0x4:
ck_dpll1.rate /= 2;
break;
default:
ck_dpll1.rate /= 4;
break;
}
}
}
propagate_rate(&ck_dpll1);
#else
/* Find the highest supported frequency and enable it */
if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
printk(KERN_ERR "System frequencies not set. Check your config.\n");
/* Guess sane values (60MHz) */
omap_writew(0x2290, DPLL_CTL);
omap_writew(0x1005, ARM_CKCTL);
ck_dpll1.rate = 60000000;
propagate_rate(&ck_dpll1);
}
#endif
/* Cache rates for clocks connected to ck_ref (not dpll1) */
propagate_rate(&ck_ref);
printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
"%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
#ifdef CONFIG_MACH_OMAP_PERSEUS2
/* Select slicer output as OMAP input clock */
omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
#endif
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
/* Put DSP/MPUI into reset until needed */
omap_writew(0, ARM_RSTCT1);
omap_writew(1, ARM_RSTCT2);
omap_writew(0x400, ARM_IDLECT1);
/*
* According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
* of the ARM_IDLECT2 register must be set to zero. The power-on
* default value of this bit is one.
*/
omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
/*
* Only enable those clocks we will need, let the drivers
* enable other clocks as necessary
*/
clk_use(&armper_ck.clk);
clk_use(&armxor_ck.clk);
clk_use(&armtim_ck.clk); /* This should be done by timer code */
if (cpu_is_omap1510())
clk_enable(&arm_gpio_ck);
return 0;
}
arch/arm/mach-omap1/clock.h 0 → 100644
浏览文件 @ a46699c9
此差异已折叠。
arch/arm/mach-omap1/devices.c
浏览文件 @ a46699c9
......@@ -25,56 +25,7 @@
#include <asm/arch/mux.h>
#include <asm/arch/gpio.h>
static void omap_nop_release(struct device *dev)
{
/* Nothing */
}
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
#define OMAP_I2C_BASE 0xfffb3800
static struct resource i2c_resources[] = {
{
.start = OMAP_I2C_BASE,
.end = OMAP_I2C_BASE + 0x3f,
.flags = IORESOURCE_MEM,
},
{
.start = INT_I2C,
.flags = IORESOURCE_IRQ,
},
};
/* DMA not used; works around erratum writing to non-empty i2c fifo */
static struct platform_device omap_i2c_device = {
.name = "i2c_omap",
.id = -1,
.dev = {
.release = omap_nop_release,
},
.num_resources = ARRAY_SIZE(i2c_resources),
.resource = i2c_resources,
};
static void omap_init_i2c(void)
{
/* FIXME define and use a boot tag, in case of boards that
* either don't wire up I2C, or chips that mux it differently...
* it can include clocking and address info, maybe more.
*/
omap_cfg_reg(I2C_SCL);
omap_cfg_reg(I2C_SDA);
(void) platform_device_register(&omap_i2c_device);
}
#else
static inline void omap_init_i2c(void) {}
#endif
extern void omap_nop_release(struct device *dev);
/*-------------------------------------------------------------------------*/
......@@ -110,137 +61,6 @@ static inline void omap_init_irda(void) {}
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
#define OMAP_MMC1_BASE 0xfffb7800
#define OMAP_MMC2_BASE 0xfffb7c00 /* omap16xx only */
static struct omap_mmc_conf mmc1_conf;
static u64 mmc1_dmamask = 0xffffffff;
static struct resource mmc1_resources[] = {
{
.start = IO_ADDRESS(OMAP_MMC1_BASE),
.end = IO_ADDRESS(OMAP_MMC1_BASE) + 0x7f,
.flags = IORESOURCE_MEM,
},
{
.start = INT_MMC,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mmc_omap_device1 = {
.name = "mmci-omap",
.id = 1,
.dev = {
.release = omap_nop_release,
.dma_mask = &mmc1_dmamask,
.platform_data = &mmc1_conf,
},
.num_resources = ARRAY_SIZE(mmc1_resources),
.resource = mmc1_resources,
};
#ifdef CONFIG_ARCH_OMAP16XX
static struct omap_mmc_conf mmc2_conf;
static u64 mmc2_dmamask = 0xffffffff;
static struct resource mmc2_resources[] = {
{
.start = IO_ADDRESS(OMAP_MMC2_BASE),
.end = IO_ADDRESS(OMAP_MMC2_BASE) + 0x7f,
.flags = IORESOURCE_MEM,
},
{
.start = INT_1610_MMC2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mmc_omap_device2 = {
.name = "mmci-omap",
.id = 2,
.dev = {
.release = omap_nop_release,
.dma_mask = &mmc2_dmamask,
.platform_data = &mmc2_conf,
},
.num_resources = ARRAY_SIZE(mmc2_resources),
.resource = mmc2_resources,
};
#endif
static void __init omap_init_mmc(void)
{
const struct omap_mmc_config *mmc_conf;
const struct omap_mmc_conf *mmc;
/* NOTE: assumes MMC was never (wrongly) enabled */
mmc_conf = omap_get_config(OMAP_TAG_MMC, struct omap_mmc_config);
if (!mmc_conf)
return;
/* block 1 is always available and has just one pinout option */
mmc = &mmc_conf->mmc[0];
if (mmc->enabled) {
omap_cfg_reg(MMC_CMD);
omap_cfg_reg(MMC_CLK);
omap_cfg_reg(MMC_DAT0);
if (cpu_is_omap1710()) {
omap_cfg_reg(M15_1710_MMC_CLKI);
omap_cfg_reg(P19_1710_MMC_CMDDIR);
omap_cfg_reg(P20_1710_MMC_DATDIR0);
}
if (mmc->wire4) {
omap_cfg_reg(MMC_DAT1);
/* NOTE: DAT2 can be on W10 (here) or M15 */
if (!mmc->nomux)
omap_cfg_reg(MMC_DAT2);
omap_cfg_reg(MMC_DAT3);
}
mmc1_conf = *mmc;
(void) platform_device_register(&mmc_omap_device1);
}
#ifdef CONFIG_ARCH_OMAP16XX
/* block 2 is on newer chips, and has many pinout options */
mmc = &mmc_conf->mmc[1];
if (mmc->enabled) {
if (!mmc->nomux) {
omap_cfg_reg(Y8_1610_MMC2_CMD);
omap_cfg_reg(Y10_1610_MMC2_CLK);
omap_cfg_reg(R18_1610_MMC2_CLKIN);
omap_cfg_reg(W8_1610_MMC2_DAT0);
if (mmc->wire4) {
omap_cfg_reg(V8_1610_MMC2_DAT1);
omap_cfg_reg(W15_1610_MMC2_DAT2);
omap_cfg_reg(R10_1610_MMC2_DAT3);
}
/* These are needed for the level shifter */
omap_cfg_reg(V9_1610_MMC2_CMDDIR);
omap_cfg_reg(V5_1610_MMC2_DATDIR0);
omap_cfg_reg(W19_1610_MMC2_DATDIR1);
}
/* Feedback clock must be set on OMAP-1710 MMC2 */
if (cpu_is_omap1710())
omap_writel(omap_readl(MOD_CONF_CTRL_1) | (1 << 24),
MOD_CONF_CTRL_1);
mmc2_conf = *mmc;
(void) platform_device_register(&mmc_omap_device2);
}
#endif
return;
}
#else
static inline void omap_init_mmc(void) {}
#endif
#if defined(CONFIG_OMAP_RTC) || defined(CONFIG_OMAP_RTC)
#define OMAP_RTC_BASE 0xfffb4800
......@@ -279,38 +99,6 @@ static void omap_init_rtc(void)
static inline void omap_init_rtc(void) {}
#endif
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_OMAP16XX_WATCHDOG) || defined(CONFIG_OMAP16XX_WATCHDOG_MODULE)
#define OMAP_WDT_BASE 0xfffeb000
static struct resource wdt_resources[] = {
{
.start = OMAP_WDT_BASE,
.end = OMAP_WDT_BASE + 0x4f,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap_wdt_device = {
.name = "omap1610_wdt",
.id = -1,
.dev = {
.release = omap_nop_release,
},
.num_resources = ARRAY_SIZE(wdt_resources),
.resource = wdt_resources,
};
static void omap_init_wdt(void)
{
(void) platform_device_register(&omap_wdt_device);
}
#else
static inline void omap_init_wdt(void) {}
#endif
/*-------------------------------------------------------------------------*/
......@@ -334,18 +122,15 @@ static inline void omap_init_wdt(void) {}
* may be handled by the boot loader, and drivers should expect it will
* normally have been done by the time they're probed.
*/
static int __init omap_init_devices(void)
static int __init omap1_init_devices(void)
{
/* please keep these calls, and their implementations above,
* in alphabetical order so they're easier to sort through.
*/
omap_init_i2c();
omap_init_irda();
omap_init_mmc();
omap_init_rtc();
omap_init_wdt();
return 0;
}
arch_initcall(omap_init_devices);
arch_initcall(omap1_init_devices);
arch/arm/mach-omap1/id.c
浏览文件 @ a46699c9
......@@ -18,6 +18,13 @@
#include <asm/io.h>
#define OMAP_DIE_ID_0 0xfffe1800
#define OMAP_DIE_ID_1 0xfffe1804
#define OMAP_PRODUCTION_ID_0 0xfffe2000
#define OMAP_PRODUCTION_ID_1 0xfffe2004
#define OMAP32_ID_0 0xfffed400
#define OMAP32_ID_1 0xfffed404
struct omap_id {
u16 jtag_id; /* Used to determine OMAP type */
u8 die_rev; /* Processor revision */
......@@ -27,6 +34,7 @@ struct omap_id {
/* Register values to detect the OMAP version */
static struct omap_id omap_ids[] __initdata = {
{ .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000},
{ .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100},
{ .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300},
{ .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000},
......@@ -164,6 +172,7 @@ void __init omap_check_revision(void)
case 0x07:
system_rev |= 0x07;
break;
case 0x03:
case 0x15:
system_rev |= 0x15;
break;
......
arch/arm/mach-omap1/io.c
浏览文件 @ a46699c9
......@@ -15,9 +15,10 @@
#include <asm/mach/map.h>
#include <asm/io.h>
#include <asm/arch/mux.h>
#include <asm/arch/tc.h>
extern int clk_init(void);
extern int omap1_clk_init(void);
extern void omap_check_revision(void);
extern void omap_sram_init(void);
......@@ -50,7 +51,7 @@ static struct map_desc omap730_io_desc[] __initdata = {
};
#endif
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
static struct map_desc omap1510_io_desc[] __initdata = {
{
.virtual = OMAP1510_DSP_BASE,
......@@ -98,7 +99,7 @@ static void __init _omap_map_io(void)
iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc));
}
#endif
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
}
......@@ -119,7 +120,7 @@ static void __init _omap_map_io(void)
/* Must init clocks early to assure that timer interrupt works
*/
clk_init();
omap1_clk_init();
}
/*
......@@ -127,7 +128,9 @@ static void __init _omap_map_io(void)
*/
void __init omap_map_common_io(void)
{
if (!initialized)
if (!initialized) {
_omap_map_io();
omap1_mux_init();
}
}
arch/arm/mach-omap1/irq.c
浏览文件 @ a46699c9
......@@ -47,6 +47,7 @@
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/arch/gpio.h>
#include <asm/arch/cpu.h>
#include <asm/io.h>
......@@ -147,11 +148,15 @@ static struct omap_irq_bank omap730_irq_banks[] = {
};
#endif
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
static struct omap_irq_bank omap1510_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
};
static struct omap_irq_bank omap310_irq_banks[] = {
{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
};
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
......@@ -181,11 +186,15 @@ void __init omap_init_irq(void)
irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
}
#endif
#ifdef CONFIG_ARCH_OMAP1510
#ifdef CONFIG_ARCH_OMAP15XX
if (cpu_is_omap1510()) {
irq_banks = omap1510_irq_banks;
irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
}
if (cpu_is_omap310()) {
irq_banks = omap310_irq_banks;
irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
}
#endif
#if defined(CONFIG_ARCH_OMAP16XX)
if (cpu_is_omap16xx()) {
......@@ -226,9 +235,11 @@ void __init omap_init_irq(void)
}
/* Unmask level 2 handler */
if (cpu_is_omap730()) {
if (cpu_is_omap730())
omap_unmask_irq(INT_730_IH2_IRQ);
} else {
omap_unmask_irq(INT_IH2_IRQ);
}
else if (cpu_is_omap1510())
omap_unmask_irq(INT_1510_IH2_IRQ);
else if (cpu_is_omap16xx())
omap_unmask_irq(INT_1610_IH2_IRQ);
}
arch/arm/mach-omap1/leds-h2p2-debug.c
浏览文件 @ a46699c9
......@@ -18,6 +18,7 @@
#include <asm/hardware.h>
#include <asm/leds.h>
#include <asm/system.h>
#include <asm/mach-types.h>
#include <asm/arch/fpga.h>
#include <asm/arch/gpio.h>
......@@ -63,14 +64,19 @@ void h2p2_dbg_leds_event(led_event_t evt)
case led_stop:
case led_halted:
/* all leds off during suspend or shutdown */
omap_set_gpio_dataout(GPIO_TIMER, 0);
omap_set_gpio_dataout(GPIO_IDLE, 0);
if (! machine_is_omap_perseus2()) {
omap_set_gpio_dataout(GPIO_TIMER, 0);
omap_set_gpio_dataout(GPIO_IDLE, 0);
}
__raw_writew(~0, &fpga->leds);
led_state &= ~LED_STATE_ENABLED;
if (evt == led_halted) {
iounmap(fpga);
fpga = NULL;
}
goto done;
case led_claim:
......@@ -85,18 +91,37 @@ void h2p2_dbg_leds_event(led_event_t evt)
#ifdef CONFIG_LEDS_TIMER
case led_timer:
led_state ^= LED_TIMER_ON;
omap_set_gpio_dataout(GPIO_TIMER, led_state & LED_TIMER_ON);
goto done;
if (machine_is_omap_perseus2())
hw_led_state ^= H2P2_DBG_FPGA_P2_LED_TIMER;
else {
omap_set_gpio_dataout(GPIO_TIMER, led_state & LED_TIMER_ON);
goto done;
}
break;
#endif
#ifdef CONFIG_LEDS_CPU
case led_idle_start:
omap_set_gpio_dataout(GPIO_IDLE, 1);
goto done;
if (machine_is_omap_perseus2())
hw_led_state |= H2P2_DBG_FPGA_P2_LED_IDLE;
else {
omap_set_gpio_dataout(GPIO_IDLE, 1);
goto done;
}
break;
case led_idle_end:
omap_set_gpio_dataout(GPIO_IDLE, 0);
goto done;
if (machine_is_omap_perseus2())
hw_led_state &= ~H2P2_DBG_FPGA_P2_LED_IDLE;
else {
omap_set_gpio_dataout(GPIO_IDLE, 0);
goto done;
}
break;
#endif
case led_green_on:
......@@ -135,7 +160,7 @@ void h2p2_dbg_leds_event(led_event_t evt)
/*
* Actually burn the LEDs
*/
if (led_state & LED_STATE_CLAIMED)
if (led_state & LED_STATE_ENABLED)
__raw_writew(~hw_led_state, &fpga->leds);
done:
......
arch/arm/mach-omap1/leds.c
浏览文件 @ a46699c9
......@@ -33,7 +33,6 @@ omap_leds_init(void)
if (machine_is_omap_h2()
|| machine_is_omap_h3()
|| machine_is_omap_perseus2()
#ifdef CONFIG_OMAP_OSK_MISTRAL
|| machine_is_omap_osk()
#endif
......
arch/arm/mach-omap1/mux.c 0 → 100644
浏览文件 @ a46699c9
/*
* linux/arch/arm/mach-omap1/mux.c
*
* OMAP1 pin multiplexing configurations
*
* Copyright (C) 2003 - 2005 Nokia Corporation
*
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <asm/system.h>
#include <asm/io.h>
#include <linux/spinlock.h>
#include <asm/arch/mux.h>
#ifdef CONFIG_OMAP_MUX
#ifdef CONFIG_ARCH_OMAP730
struct pin_config __initdata_or_module omap730_pins[] = {
MUX_CFG_730("E2_730_KBR0", 12, 21, 0, 0, 20, 1, NA, 0, 0)
MUX_CFG_730("J7_730_KBR1", 12, 25, 0, 0, 24, 1, NA, 0, 0)
MUX_CFG_730("E1_730_KBR2", 12, 29, 0, 0, 28, 1, NA, 0, 0)
MUX_CFG_730("F3_730_KBR3", 13, 1, 0, 0, 0, 1, NA, 0, 0)
MUX_CFG_730("D2_730_KBR4", 13, 5, 0, 0, 4, 1, NA, 0, 0)
MUX_CFG_730("C2_730_KBC0", 13, 9, 0, 0, 8, 1, NA, 0, 0)
MUX_CFG_730("D3_730_KBC1", 13, 13, 0, 0, 12, 1, NA, 0, 0)
MUX_CFG_730("E4_730_KBC2", 13, 17, 0, 0, 16, 1, NA, 0, 0)
MUX_CFG_730("F4_730_KBC3", 13, 21, 0, 0, 20, 1, NA, 0, 0)
MUX_CFG_730("E3_730_KBC4", 13, 25, 0, 0, 24, 1, NA, 0, 0)
};
#endif
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
struct pin_config __initdata_or_module omap1xxx_pins[] = {
/*
* description mux mode mux pull pull pull pu_pd pu dbg
* reg offset mode reg bit ena reg
*/
MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
/* UART2 (COM_UART_GATING), conflicts with USB2 */
MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
/* UART3 (GIGA_UART_GATING) */
MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
/* PWT & PWL, conflicts with UART3 */
MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
/* USB internal master generic */
MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
/* USB1 master */
MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
/* USB2 master */
MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
/* OMAP-1510 GPIO */
MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
/* OMAP1610 GPIO */
MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
/* OMAP-1710 GPIO */
MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
/* MPUIO */
MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1)
MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
/* MCBSP2 */
MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
/* MCBSP3 NOTE: Mode must 1 for clock */
MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
/* Misc ballouts */
MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
/* OMAP-1610 MMC2 */
MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
/* OMAP-1610 External Trace Interface */
MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
/* OMAP16XX GPIO */
MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1)
MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
/* OMAP-1610 uWire */
MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
/* OMAP-1610 Flash */
MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
/* First MMC interface, same on 1510, 1610 and 1710 */
MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
/* OMAP-1610 USB0 alternate configuration */
MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
/* USB2 interface */
MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
/* 16XX UART */
MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
/* I2C interface */
MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
/* Keypad */
MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
/* Power management */
MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
/* MCLK Settings */
MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
/* CompactFlash controller, conflicts with MMC1 */
MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
};
#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
int __init omap1_mux_init(void)
{
#ifdef CONFIG_ARCH_OMAP730
omap_mux_register(omap730_pins, ARRAY_SIZE(omap730_pins));
#endif
#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
omap_mux_register(omap1xxx_pins, ARRAY_SIZE(omap1xxx_pins));
#endif
return 0;
}
#endif
arch/arm/mach-omap1/serial.c
浏览文件 @ a46699c9
......@@ -109,9 +109,10 @@ static struct platform_device serial_device = {
* By default UART2 does not work on Innovator-1510 if you have
* USB OHCI enabled. To use UART2, you must disable USB2 first.
*/
void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
void __init omap_serial_init(void)
{
int i;
const struct omap_uart_config *info;
if (cpu_is_omap730()) {
serial_platform_data[0].regshift = 0;
......@@ -126,10 +127,14 @@ void __init omap_serial_init(int ports[OMAP_MAX_NR_PORTS])
serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
}
info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
if (info == NULL)
return;
for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
unsigned char reg;
if (ports[i] == 0) {
if (!((1 << i) & info->enabled_uarts)) {
serial_platform_data[i].membase = NULL;
serial_platform_data[i].mapbase = 0;
continue;
......
arch/arm/mach-omap1/time.c
浏览文件 @ a46699c9
......@@ -226,8 +226,8 @@ unsigned long long sched_clock(void)
#ifdef CONFIG_OMAP_32K_TIMER
#ifdef CONFIG_ARCH_OMAP1510
#error OMAP 32KHz timer does not currently work on 1510!
#ifdef CONFIG_ARCH_OMAP15XX
#error OMAP 32KHz timer does not currently work on 15XX!
#endif
/*
......
arch/arm/mach-omap2/Kconfig 0 → 100644
浏览文件 @ a46699c9
comment "OMAP Core Type"
depends on ARCH_OMAP2
config ARCH_OMAP24XX
bool "OMAP24xx Based System"
depends on ARCH_OMAP2
config ARCH_OMAP2420
bool "OMAP2420 support"
depends on ARCH_OMAP24XX
comment "OMAP Board Type"
depends on ARCH_OMAP2
config MACH_OMAP_GENERIC
bool "Generic OMAP board"
depends on ARCH_OMAP2 && ARCH_OMAP24XX
config MACH_OMAP_H4
bool "OMAP 2420 H4 board"
depends on ARCH_OMAP2 && ARCH_OMAP24XX
arch/arm/mach-omap2/Makefile 0 → 100644
浏览文件 @ a46699c9
#
# Makefile for the linux kernel.
#
# Common support
obj-y := irq.o id.o io.o sram-fn.o clock.o mux.o devices.o serial.o
obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
arch/arm/mach-omap2/Makefile.boot 0 → 100644
浏览文件 @ a46699c9
zreladdr-y := 0x80008000
params_phys-y := 0x80000100
initrd_phys-y := 0x80800000
arch/arm/mach-omap2/board-generic.c 0 → 100644
浏览文件 @ a46699c9
/*
* linux/arch/arm/mach-omap/omap2/board-generic.c
*
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
*
* Modified from mach-omap/omap1/board-generic.c
*
* Code for generic OMAP2 board. Should work on many OMAP2 systems where
* the bootloader passes the board-specific data to the kernel.
* Do not put any board specific code to this file; create a new machine
* type if you need custom low-level initializations.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/device.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mux.h>
#include <asm/arch/usb.h>
#include <asm/arch/board.h>
#include <asm/arch/common.h>
static void __init omap_generic_init_irq(void)
{
omap_init_irq();
}
static struct omap_uart_config generic_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_mmc_config generic_mmc_config __initdata = {
.mmc [0] = {
.enabled = 0,
.wire4 = 0,
.wp_pin = -1,
.power_pin = -1,
.switch_pin = -1,
},
};
static struct omap_board_config_kernel generic_config[] = {
{ OMAP_TAG_UART, &generic_uart_config },
{ OMAP_TAG_MMC, &generic_mmc_config },
};
static void __init omap_generic_init(void)
{
omap_board_config = generic_config;
omap_board_config_size = ARRAY_SIZE(generic_config);
omap_serial_init();
}
static void __init omap_generic_map_io(void)
{
omap_map_common_io();
}
MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
/* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
.phys_ram = 0x80000000,
.phys_io = 0x48000000,
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_generic_map_io,
.init_irq = omap_generic_init_irq,
.init_machine = omap_generic_init,
.timer = &omap_timer,
MACHINE_END
arch/arm/mach-omap2/board-h4.c 0 → 100644
浏览文件 @ a46699c9
/*
* linux/arch/arm/mach-omap/omap2/board-h4.c
*
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
*
* Modified from mach-omap/omap1/board-generic.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/delay.h>
#include <asm/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mux.h>
#include <asm/arch/usb.h>
#include <asm/arch/board.h>
#include <asm/arch/common.h>
#include <asm/arch/prcm.h>
#include <asm/io.h>
#include <asm/delay.h>
static struct mtd_partition h4_partitions[] = {
/* bootloader (U-Boot, etc) in first sector */
{
.name = "bootloader",
.offset = 0,
.size = SZ_128K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
/* bootloader params in the next sector */
{
.name = "params",
.offset = MTDPART_OFS_APPEND,
.size = SZ_128K,
.mask_flags = 0,
},
/* kernel */
{
.name = "kernel",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M,
.mask_flags = 0
},
/* file system */
{
.name = "filesystem",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
.mask_flags = 0
}
};
static struct flash_platform_data h4_flash_data = {
.map_name = "cfi_probe",
.width = 2,
.parts = h4_partitions,
.nr_parts = ARRAY_SIZE(h4_partitions),
};
static struct resource h4_flash_resource = {
.start = H4_CS0_BASE,
.end = H4_CS0_BASE + SZ_64M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device h4_flash_device = {
.name = "omapflash",
.id = 0,
.dev = {
.platform_data = &h4_flash_data,
},
.num_resources = 1,
.resource = &h4_flash_resource,
};
static struct resource h4_smc91x_resources[] = {
[0] = {
.start = OMAP24XX_ETHR_START, /* Physical */
.end = OMAP24XX_ETHR_START + 0xf,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
.end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device h4_smc91x_device = {
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(h4_smc91x_resources),
.resource = h4_smc91x_resources,
};
static struct platform_device *h4_devices[] __initdata = {
&h4_smc91x_device,
&h4_flash_device,
};
static inline void __init h4_init_smc91x(void)
{
/* Make sure CS1 timings are correct */
GPMC_CONFIG1_1 = 0x00011200;
GPMC_CONFIG2_1 = 0x001f1f01;
GPMC_CONFIG3_1 = 0x00080803;
GPMC_CONFIG4_1 = 0x1c091c09;
GPMC_CONFIG5_1 = 0x041f1f1f;
GPMC_CONFIG6_1 = 0x000004c4;
GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24);
udelay(100);
omap_cfg_reg(M15_24XX_GPIO92);
if (omap_request_gpio(OMAP24XX_ETHR_GPIO_IRQ) < 0) {
printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
OMAP24XX_ETHR_GPIO_IRQ);
return;
}
omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
}
static void __init omap_h4_init_irq(void)
{
omap_init_irq();
omap_gpio_init();
h4_init_smc91x();
}
static struct omap_uart_config h4_uart_config __initdata = {
.enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)),
};
static struct omap_mmc_config h4_mmc_config __initdata = {
.mmc [0] = {
.enabled = 1,
.wire4 = 1,
.wp_pin = -1,
.power_pin = -1,
.switch_pin = -1,
},
};
static struct omap_lcd_config h4_lcd_config __initdata = {
.panel_name = "h4",
.ctrl_name = "internal",
};
static struct omap_board_config_kernel h4_config[] = {
{ OMAP_TAG_UART, &h4_uart_config },
{ OMAP_TAG_MMC, &h4_mmc_config },
{ OMAP_TAG_LCD, &h4_lcd_config },
};
static void __init omap_h4_init(void)
{
/*
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on
* if not needed.
*/
platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
omap_board_config = h4_config;
omap_board_config_size = ARRAY_SIZE(h4_config);
omap_serial_init();
}
static void __init omap_h4_map_io(void)
{
omap_map_common_io();
}
MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
/* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
.phys_ram = 0x80000000,
.phys_io = 0x48000000,
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap_h4_map_io,
.init_irq = omap_h4_init_irq,
.init_machine = omap_h4_init,
.timer = &omap_timer,
MACHINE_END
arch/arm/mach-omap2/clock.c 0 → 100644
浏览文件 @ a46699c9
此差异已折叠。
arch/arm/mach-omap2/clock.h 0 → 100644
浏览文件 @ a46699c9
此差异已折叠。
arch/arm/mach-omap2/devices.c 0 → 100644
浏览文件 @ a46699c9
/*
* linux/arch/arm/mach-omap2/devices.c
*
* OMAP2 platform device setup/initialization
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include <asm/arch/tc.h>
#include <asm/arch/board.h>
#include <asm/arch/mux.h>
#include <asm/arch/gpio.h>
extern void omap_nop_release(struct device *dev);
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
#define OMAP2_I2C_BASE2 0x48072000
#define OMAP2_I2C_INT2 57
static struct resource i2c_resources2[] = {
{
.start = OMAP2_I2C_BASE2,
.end = OMAP2_I2C_BASE2 + 0x3f,
.flags = IORESOURCE_MEM,
},
{
.start = OMAP2_I2C_INT2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device omap_i2c_device2 = {
.name = "i2c_omap",
.id = 2,
.dev = {
.release = omap_nop_release,
},
.num_resources = ARRAY_SIZE(i2c_resources2),
.resource = i2c_resources2,
};
/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
static void omap_init_i2c(void)
{
/* REVISIT: Second I2C not in use on H4? */
if (machine_is_omap_h4())
return;
omap_cfg_reg(J15_24XX_I2C2_SCL);
omap_cfg_reg(H19_24XX_I2C2_SDA);
(void) platform_device_register(&omap_i2c_device2);
}
#else
static void omap_init_i2c(void) {}
#endif
/*-------------------------------------------------------------------------*/
static int __init omap2_init_devices(void)
{
/* please keep these calls, and their implementations above,
* in alphabetical order so they're easier to sort through.
*/
omap_init_i2c();
return 0;
}
arch_initcall(omap2_init_devices);
arch/arm/mach-omap2/id.c 0 → 100644
浏览文件 @ a46699c9
/*
* linux/arch/arm/mach-omap2/id.c
*
* OMAP2 CPU identification code
*
* Copyright (C) 2005 Nokia Corporation
* Written by Tony Lindgren <tony@atomide.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/io.h>
#define OMAP24XX_TAP_BASE io_p2v(0x48014000)
#define OMAP_TAP_IDCODE 0x0204
#define OMAP_TAP_PROD_ID 0x0208
#define OMAP_TAP_DIE_ID_0 0x0218
#define OMAP_TAP_DIE_ID_1 0x021C
#define OMAP_TAP_DIE_ID_2 0x0220
#define OMAP_TAP_DIE_ID_3 0x0224
/* system_rev fields for OMAP2 processors:
* CPU id bits [31:16],
* CPU device type [15:12], (unprg,normal,POP)
* CPU revision [11:08]
* CPU class bits [07:00]
*/
struct omap_id {
u16 hawkeye; /* Silicon type (Hawkeye id) */
u8 dev; /* Device type from production_id reg */
u32 type; /* combined type id copied to system_rev */
};
/* Register values to detect the OMAP version */
static struct omap_id omap_ids[] __initdata = {
{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200000 },
{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201000 },
{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202000 },
{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220000 },
{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230000 },
{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
};
static u32 __init read_tap_reg(int reg)
{
return __raw_readl(OMAP24XX_TAP_BASE + reg);
}
void __init omap2_check_revision(void)
{
int i, j;
u32 idcode;
u32 prod_id;
u16 hawkeye;
u8 dev_type;
u8 rev;
idcode = read_tap_reg(OMAP_TAP_IDCODE);
prod_id = read_tap_reg(OMAP_TAP_PROD_ID);
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0x0f;
dev_type = (prod_id >> 16) & 0x0f;
#ifdef DEBUG
printk(KERN_DEBUG "OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
printk(KERN_DEBUG "OMAP_TAP_DIE_ID_0: 0x%08x\n",
read_tap_reg(OMAP_TAP_DIE_ID_0));
printk(KERN_DEBUG "OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
read_tap_reg(OMAP_TAP_DIE_ID_1),
(read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
printk(KERN_DEBUG "OMAP_TAP_DIE_ID_2: 0x%08x\n",
read_tap_reg(OMAP_TAP_DIE_ID_2));
printk(KERN_DEBUG "OMAP_TAP_DIE_ID_3: 0x%08x\n",
read_tap_reg(OMAP_TAP_DIE_ID_3));
printk(KERN_DEBUG "OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
prod_id, dev_type);
#endif
/* Check hawkeye ids */
for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
if (hawkeye == omap_ids[i].hawkeye)
break;
}
if (i == ARRAY_SIZE(omap_ids)) {
printk(KERN_ERR "Unknown OMAP CPU id\n");
return;
}
for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
if (dev_type == omap_ids[j].dev)
break;
}
if (j == ARRAY_SIZE(omap_ids)) {
printk(KERN_ERR "Unknown OMAP device type. "
"Handling it as OMAP%04x\n",
omap_ids[i].type >> 16);
j = i;
}
system_rev = omap_ids[j].type;
system_rev |= rev << 8;
/* Add the cpu class info (24xx) */
system_rev |= 0x24;
pr_info("OMAP%04x", system_rev >> 16);
if ((system_rev >> 8) & 0x0f)
printk("%x", (system_rev >> 8) & 0x0f);
printk("\n");
}
arch/arm/mach-omap2/io.c 0 → 100644
浏览文件 @ a46699c9
/*
* linux/arch/arm/mach-omap2/io.c
*
* OMAP2 I/O mapping code
*
* Copyright (C) 2005 Nokia Corporation
* Author: Juha Yrjl <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/mach/map.h>
#include <asm/io.h>
#include <asm/arch/mux.h>
extern void omap_sram_init(void);
extern int omap2_clk_init(void);
extern void omap2_check_revision(void);
/*
* The machine specific code may provide the extra mapping besides the
* default mapping provided here.
*/
static struct map_desc omap2_io_desc[] __initdata = {
{
.virtual = L3_24XX_VIRT,
.pfn = __phys_to_pfn(L3_24XX_PHYS),
.length = L3_24XX_SIZE,
.type = MT_DEVICE
},
{
.virtual = L4_24XX_VIRT,
.pfn = __phys_to_pfn(L4_24XX_PHYS),
.length = L4_24XX_SIZE,
.type = MT_DEVICE
}
};
void __init omap_map_common_io(void)
{
iotable_init(omap2_io_desc, ARRAY_SIZE(omap2_io_desc));
omap2_check_revision();
omap_sram_init();
omap2_mux_init();
omap2_clk_init();
}
arch/arm/mach-omap2/irq.c 0 → 100644
浏览文件 @ a46699c9
/*
* linux/arch/arm/mach-omap/omap2/irq.c
*
* Interrupt handler for OMAP2 boards.
*
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/config.h>
#include <linux/interrupt.h>
#include <asm/hardware.h>
#include <asm/mach/irq.h>
#include <asm/irq.h>
#include <asm/io.h>
#define INTC_REVISION 0x0000
#define INTC_SYSCONFIG 0x0010
#define INTC_SYSSTATUS 0x0014
#define INTC_CONTROL 0x0048
#define INTC_MIR_CLEAR0 0x0088
#define INTC_MIR_SET0 0x008c
/*
* OMAP2 has a number of different interrupt controllers, each interrupt
* controller is identified as its own "bank". Register definitions are
* fairly consistent for each bank, but not all registers are implemented
* for each bank.. when in doubt, consult the TRM.
*/
static struct omap_irq_bank {
unsigned long base_reg;
unsigned int nr_irqs;
} __attribute__ ((aligned(4))) irq_banks[] = {
{
/* MPU INTC */
.base_reg = OMAP24XX_IC_BASE,
.nr_irqs = 96,
}, {
/* XXX: DSP INTC */
#if 0
/*
* Commented out for now until we fix the IVA clocking
*/
#ifdef CONFIG_ARCH_OMAP2420
}, {
/* IVA INTC (2420 only) */
.base_reg = OMAP24XX_IVA_INTC_BASE,
.nr_irqs = 16, /* Actually 32, but only 16 are used */
#endif
#endif
}
};
/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(unsigned int irq)
{
omap_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL);
}
static void omap_mask_irq(unsigned int irq)
{
int offset = (irq >> 5) << 5;
if (irq >= 64) {
irq %= 64;
} else if (irq >= 32) {
irq %= 32;
}
omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset);
}
static void omap_unmask_irq(unsigned int irq)
{
int offset = (irq >> 5) << 5;
if (irq >= 64) {
irq %= 64;
} else if (irq >= 32) {
irq %= 32;
}
omap_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset);
}
static void omap_mask_ack_irq(unsigned int irq)
{
omap_mask_irq(irq);
omap_ack_irq(irq);
}
static struct irqchip omap_irq_chip = {
.ack = omap_mask_ack_irq,
.mask = omap_mask_irq,
.unmask = omap_unmask_irq,
};
static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
unsigned long tmp;
tmp = omap_readl(bank->base_reg + INTC_REVISION) & 0xff;
printk(KERN_INFO "IRQ: Found an INTC at 0x%08lx "
"(revision %ld.%ld) with %d interrupts\n",
bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
tmp = omap_readl(bank->base_reg + INTC_SYSCONFIG);
tmp |= 1 << 1; /* soft reset */
omap_writel(tmp, bank->base_reg + INTC_SYSCONFIG);
while (!(omap_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1))
/* Wait for reset to complete */;
}
void __init omap_init_irq(void)
{
unsigned long nr_irqs = 0;
unsigned int nr_banks = 0;
int i;
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
struct omap_irq_bank *bank = irq_banks + i;
/* XXX */
if (!bank->base_reg)
continue;
omap_irq_bank_init_one(bank);
nr_irqs += bank->nr_irqs;
nr_banks++;
}
printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
nr_irqs, nr_banks, nr_banks > 1 ? "s" : "");
for (i = 0; i < nr_irqs; i++) {
set_irq_chip(i, &omap_irq_chip);
set_irq_handler(i, do_level_IRQ);
set_irq_flags(i, IRQF_VALID);
}
}
arch/arm/mach-omap2/mux.c 0 → 100644
浏览文件 @ a46699c9
/*
* linux/arch/arm/mach-omap2/mux.c
*
* OMAP1 pin multiplexing configurations
*
* Copyright (C) 2003 - 2005 Nokia Corporation
*
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/init.h>
#include <asm/system.h>
#include <asm/io.h>
#include <linux/spinlock.h>
#include <asm/arch/mux.h>
#ifdef CONFIG_OMAP_MUX
/* NOTE: See mux.h for the enumeration */
struct pin_config __initdata_or_module omap24xx_pins[] = {
/*
* description mux mux pull pull debug
* offset mode ena type
*/
/* 24xx I2C */
MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1)
MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1)
MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 0, 1)
MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1)
/* Menelaus interrupt */
MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1)
/* 24xx GPIO */
MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
};
int __init omap2_mux_init(void)
{
omap_mux_register(omap24xx_pins, ARRAY_SIZE(omap24xx_pins));
return 0;
}
#endif
arch/arm/mach-omap2/prcm.h 0 → 100644
浏览文件 @ a46699c9
/*
* prcm.h - Access definations for use in OMAP24XX clock and power management
*
* Copyright (C) 2005 Texas Instruments, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_DPM_PRCM_H
#define __ASM_ARM_ARCH_DPM_PRCM_H
/* SET_PERFORMANCE_LEVEL PARAMETERS */
#define PRCM_HALF_SPEED 1
#define PRCM_FULL_SPEED 2
#ifndef __ASSEMBLER__
#define PRCM_REG32(offset) __REG32(OMAP24XX_PRCM_BASE + (offset))
#define PRCM_REVISION PRCM_REG32(0x000)
#define PRCM_SYSCONFIG PRCM_REG32(0x010)
#define PRCM_IRQSTATUS_MPU PRCM_REG32(0x018)
#define PRCM_IRQENABLE_MPU PRCM_REG32(0x01C)
#define PRCM_VOLTCTRL PRCM_REG32(0x050)
#define PRCM_VOLTST PRCM_REG32(0x054)
#define PRCM_CLKSRC_CTRL PRCM_REG32(0x060)
#define PRCM_CLKOUT_CTRL PRCM_REG32(0x070)
#define PRCM_CLKEMUL_CTRL PRCM_REG32(0x078)
#define PRCM_CLKCFG_CTRL PRCM_REG32(0x080)
#define PRCM_CLKCFG_STATUS PRCM_REG32(0x084)
#define PRCM_VOLTSETUP PRCM_REG32(0x090)
#define PRCM_CLKSSETUP PRCM_REG32(0x094)
#define PRCM_POLCTRL PRCM_REG32(0x098)
/* GENERAL PURPOSE */
#define GENERAL_PURPOSE1 PRCM_REG32(0x0B0)
#define GENERAL_PURPOSE2 PRCM_REG32(0x0B4)
#define GENERAL_PURPOSE3 PRCM_REG32(0x0B8)
#define GENERAL_PURPOSE4 PRCM_REG32(0x0BC)
#define GENERAL_PURPOSE5 PRCM_REG32(0x0C0)
#define GENERAL_PURPOSE6 PRCM_REG32(0x0C4)
#define GENERAL_PURPOSE7 PRCM_REG32(0x0C8)
#define GENERAL_PURPOSE8 PRCM_REG32(0x0CC)
#define GENERAL_PURPOSE9 PRCM_REG32(0x0D0)
#define GENERAL_PURPOSE10 PRCM_REG32(0x0D4)
#define GENERAL_PURPOSE11 PRCM_REG32(0x0D8)
#define GENERAL_PURPOSE12 PRCM_REG32(0x0DC)
#define GENERAL_PURPOSE13 PRCM_REG32(0x0E0)
#define GENERAL_PURPOSE14 PRCM_REG32(0x0E4)
#define GENERAL_PURPOSE15 PRCM_REG32(0x0E8)
#define GENERAL_PURPOSE16 PRCM_REG32(0x0EC)
#define GENERAL_PURPOSE17 PRCM_REG32(0x0F0)
#define GENERAL_PURPOSE18 PRCM_REG32(0x0F4)
#define GENERAL_PURPOSE19 PRCM_REG32(0x0F8)
#define GENERAL_PURPOSE20 PRCM_REG32(0x0FC)
/* MPU */
#define CM_CLKSEL_MPU PRCM_REG32(0x140)
#define CM_CLKSTCTRL_MPU PRCM_REG32(0x148)
#define RM_RSTST_MPU PRCM_REG32(0x158)
#define PM_WKDEP_MPU PRCM_REG32(0x1C8)
#define PM_EVGENCTRL_MPU PRCM_REG32(0x1D4)
#define PM_EVEGENONTIM_MPU PRCM_REG32(0x1D8)
#define PM_EVEGENOFFTIM_MPU PRCM_REG32(0x1DC)
#define PM_PWSTCTRL_MPU PRCM_REG32(0x1E0)
#define PM_PWSTST_MPU PRCM_REG32(0x1E4)
/* CORE */
#define CM_FCLKEN1_CORE PRCM_REG32(0x200)
#define CM_FCLKEN2_CORE PRCM_REG32(0x204)
#define CM_FCLKEN3_CORE PRCM_REG32(0x208)
#define CM_ICLKEN1_CORE PRCM_REG32(0x210)
#define CM_ICLKEN2_CORE PRCM_REG32(0x214)
#define CM_ICLKEN3_CORE PRCM_REG32(0x218)
#define CM_ICLKEN4_CORE PRCM_REG32(0x21C)
#define CM_IDLEST1_CORE PRCM_REG32(0x220)
#define CM_IDLEST2_CORE PRCM_REG32(0x224)
#define CM_IDLEST3_CORE PRCM_REG32(0x228)
#define CM_IDLEST4_CORE PRCM_REG32(0x22C)
#define CM_AUTOIDLE1_CORE PRCM_REG32(0x230)
#define CM_AUTOIDLE2_CORE PRCM_REG32(0x234)
#define CM_AUTOIDLE3_CORE PRCM_REG32(0x238)
#define CM_AUTOIDLE4_CORE PRCM_REG32(0x23C)
#define CM_CLKSEL1_CORE PRCM_REG32(0x240)
#define CM_CLKSEL2_CORE PRCM_REG32(0x244)
#define CM_CLKSTCTRL_CORE PRCM_REG32(0x248)
#define PM_WKEN1_CORE PRCM_REG32(0x2A0)
#define PM_WKEN2_CORE PRCM_REG32(0x2A4)
#define PM_WKST1_CORE PRCM_REG32(0x2B0)
#define PM_WKST2_CORE PRCM_REG32(0x2B4)
#define PM_WKDEP_CORE PRCM_REG32(0x2C8)
#define PM_PWSTCTRL_CORE PRCM_REG32(0x2E0)
#define PM_PWSTST_CORE PRCM_REG32(0x2E4)
/* GFX */
#define CM_FCLKEN_GFX PRCM_REG32(0x300)
#define CM_ICLKEN_GFX PRCM_REG32(0x310)
#define CM_IDLEST_GFX PRCM_REG32(0x320)
#define CM_CLKSEL_GFX PRCM_REG32(0x340)
#define CM_CLKSTCTRL_GFX PRCM_REG32(0x348)
#define RM_RSTCTRL_GFX PRCM_REG32(0x350)
#define RM_RSTST_GFX PRCM_REG32(0x358)
#define PM_WKDEP_GFX PRCM_REG32(0x3C8)
#define PM_PWSTCTRL_GFX PRCM_REG32(0x3E0)
#define PM_PWSTST_GFX PRCM_REG32(0x3E4)
/* WAKE-UP */
#define CM_FCLKEN_WKUP PRCM_REG32(0x400)
#define CM_ICLKEN_WKUP PRCM_REG32(0x410)
#define CM_IDLEST_WKUP PRCM_REG32(0x420)
#define CM_AUTOIDLE_WKUP PRCM_REG32(0x430)
#define CM_CLKSEL_WKUP PRCM_REG32(0x440)
#define RM_RSTCTRL_WKUP PRCM_REG32(0x450)
#define RM_RSTTIME_WKUP PRCM_REG32(0x454)
#define RM_RSTST_WKUP PRCM_REG32(0x458)
#define PM_WKEN_WKUP PRCM_REG32(0x4A0)
#define PM_WKST_WKUP PRCM_REG32(0x4B0)
/* CLOCKS */
#define CM_CLKEN_PLL PRCM_REG32(0x500)
#define CM_IDLEST_CKGEN PRCM_REG32(0x520)
#define CM_AUTOIDLE_PLL PRCM_REG32(0x530)
#define CM_CLKSEL1_PLL PRCM_REG32(0x540)
#define CM_CLKSEL2_PLL PRCM_REG32(0x544)
/* DSP */
#define CM_FCLKEN_DSP PRCM_REG32(0x800)
#define CM_ICLKEN_DSP PRCM_REG32(0x810)
#define CM_IDLEST_DSP PRCM_REG32(0x820)
#define CM_AUTOIDLE_DSP PRCM_REG32(0x830)
#define CM_CLKSEL_DSP PRCM_REG32(0x840)
#define CM_CLKSTCTRL_DSP PRCM_REG32(0x848)
#define RM_RSTCTRL_DSP PRCM_REG32(0x850)
#define RM_RSTST_DSP PRCM_REG32(0x858)
#define PM_WKEN_DSP PRCM_REG32(0x8A0)
#define PM_WKDEP_DSP PRCM_REG32(0x8C8)
#define PM_PWSTCTRL_DSP PRCM_REG32(0x8E0)
#define PM_PWSTST_DSP PRCM_REG32(0x8E4)
#define PRCM_IRQSTATUS_DSP PRCM_REG32(0x8F0)
#define PRCM_IRQENABLE_DSP PRCM_REG32(0x8F4)
/* IVA */
#define PRCM_IRQSTATUS_IVA PRCM_REG32(0x8F8)
#define PRCM_IRQENABLE_IVA PRCM_REG32(0x8FC)
/* Modem on 2430 */
#define CM_FCLKEN_MDM PRCM_REG32(0xC00)
#define CM_ICLKEN_MDM PRCM_REG32(0xC10)
#define CM_IDLEST_MDM PRCM_REG32(0xC20)
#define CM_CLKSEL_MDM PRCM_REG32(0xC40)
/* FIXME: Move to header for 2430 */
#define DISP_BASE (OMAP24XX_L4_IO_BASE+0x50000)
#define DISP_REG32(offset) __REG32(DISP_BASE + (offset))
#define GPMC_BASE (OMAP24XX_GPMC_BASE)
#define GPMC_REG32(offset) __REG32(GPMC_BASE + (offset))
#define GPT1_BASE (OMAP24XX_GPT1)
#define GPT1_REG32(offset) __REG32(GPT1_BASE + (offset))
/* Misc sysconfig */
#define DISPC_SYSCONFIG DISP_REG32(0x410)
#define SPI_BASE (OMAP24XX_L4_IO_BASE+0x98000)
#define MCSPI1_SYSCONFIG __REG32(SPI_BASE + 0x10)
#define MCSPI2_SYSCONFIG __REG32(SPI_BASE+0x2000 + 0x10)
//#define DSP_MMU_SYSCONFIG 0x5A000010
#define CAMERA_MMU_SYSCONFIG __REG32(DISP_BASE+0x2C10)
//#define IVA_MMU_SYSCONFIG 0x5D000010
//#define DSP_DMA_SYSCONFIG 0x00FCC02C
#define CAMERA_DMA_SYSCONFIG __REG32(DISP_BASE+0x282C)
#define SYSTEM_DMA_SYSCONFIG __REG32(DISP_BASE+0x602C)
#define GPMC_SYSCONFIG GPMC_REG32(0x010)
#define MAILBOXES_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x94010)
#define UART1_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6A054)
#define UART2_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6C054)
#define UART3_SYSCONFIG __REG32(OMAP24XX_L4_IO_BASE+0x6E054)
//#define IVA_SYSCONFIG 0x5C060010
#define SDRC_SYSCONFIG __REG32(OMAP24XX_SDRC_BASE+0x10)
#define SMS_SYSCONFIG __REG32(OMAP24XX_SMS_BASE+0x10)
#define SSI_SYSCONFIG __REG32(DISP_BASE+0x8010)
//#define VLYNQ_SYSCONFIG 0x67FFFE10
/* rkw - good cannidates for PM_ to start what nm was trying */
#define OMAP24XX_GPT2 (OMAP24XX_L4_IO_BASE+0x2A000)
#define OMAP24XX_GPT3 (OMAP24XX_L4_IO_BASE+0x78000)
#define OMAP24XX_GPT4 (OMAP24XX_L4_IO_BASE+0x7A000)
#define OMAP24XX_GPT5 (OMAP24XX_L4_IO_BASE+0x7C000)
#define OMAP24XX_GPT6 (OMAP24XX_L4_IO_BASE+0x7E000)
#define OMAP24XX_GPT7 (OMAP24XX_L4_IO_BASE+0x80000)
#define OMAP24XX_GPT8 (OMAP24XX_L4_IO_BASE+0x82000)
#define OMAP24XX_GPT9 (OMAP24XX_L4_IO_BASE+0x84000)
#define OMAP24XX_GPT10 (OMAP24XX_L4_IO_BASE+0x86000)
#define OMAP24XX_GPT11 (OMAP24XX_L4_IO_BASE+0x88000)
#define OMAP24XX_GPT12 (OMAP24XX_L4_IO_BASE+0x8A000)
#define GPTIMER1_SYSCONFIG GPT1_REG32(0x010)
#define GPTIMER2_SYSCONFIG __REG32(OMAP24XX_GPT2 + 0x10)
#define GPTIMER3_SYSCONFIG __REG32(OMAP24XX_GPT3 + 0x10)
#define GPTIMER4_SYSCONFIG __REG32(OMAP24XX_GPT4 + 0x10)
#define GPTIMER5_SYSCONFIG __REG32(OMAP24XX_GPT5 + 0x10)
#define GPTIMER6_SYSCONFIG __REG32(OMAP24XX_GPT6 + 0x10)
#define GPTIMER7_SYSCONFIG __REG32(OMAP24XX_GPT7 + 0x10)
#define GPTIMER8_SYSCONFIG __REG32(OMAP24XX_GPT8 + 0x10)
#define GPTIMER9_SYSCONFIG __REG32(OMAP24XX_GPT9 + 0x10)
#define GPTIMER10_SYSCONFIG __REG32(OMAP24XX_GPT10 + 0x10)
#define GPTIMER11_SYSCONFIG __REG32(OMAP24XX_GPT11 + 0x10)
#define GPTIMER12_SYSCONFIG __REG32(OMAP24XX_GPT12 + 0x10)
#define GPIOX_BASE(X) (OMAP24XX_GPIO_BASE+(0x2000*((X)-1)))
#define GPIO1_SYSCONFIG __REG32((GPIOX_BASE(1)+0x10))
#define GPIO2_SYSCONFIG __REG32((GPIOX_BASE(2)+0x10))
#define GPIO3_SYSCONFIG __REG32((GPIOX_BASE(3)+0x10))
#define GPIO4_SYSCONFIG __REG32((GPIOX_BASE(4)+0x10))
/* GP TIMER 1 */
#define GPTIMER1_TISTAT GPT1_REG32(0x014)
#define GPTIMER1_TISR GPT1_REG32(0x018)
#define GPTIMER1_TIER GPT1_REG32(0x01C)
#define GPTIMER1_TWER GPT1_REG32(0x020)
#define GPTIMER1_TCLR GPT1_REG32(0x024)
#define GPTIMER1_TCRR GPT1_REG32(0x028)
#define GPTIMER1_TLDR GPT1_REG32(0x02C)
#define GPTIMER1_TTGR GPT1_REG32(0x030)
#define GPTIMER1_TWPS GPT1_REG32(0x034)
#define GPTIMER1_TMAR GPT1_REG32(0x038)
#define GPTIMER1_TCAR1 GPT1_REG32(0x03C)
#define GPTIMER1_TSICR GPT1_REG32(0x040)
#define GPTIMER1_TCAR2 GPT1_REG32(0x044)
/* rkw -- base fix up please... */
#define GPTIMER3_TISR __REG32(OMAP24XX_L4_IO_BASE+0x78018)
/* SDRC */
#define SDRC_DLLA_CTRL __REG32(OMAP24XX_SDRC_BASE+0x060)
#define SDRC_DLLA_STATUS __REG32(OMAP24XX_SDRC_BASE+0x064)
#define SDRC_DLLB_CTRL __REG32(OMAP24XX_SDRC_BASE+0x068)
#define SDRC_DLLB_STATUS __REG32(OMAP24XX_SDRC_BASE+0x06C)
#define SDRC_POWER __REG32(OMAP24XX_SDRC_BASE+0x070)
#define SDRC_MR_0 __REG32(OMAP24XX_SDRC_BASE+0x084)
/* GPIO 1 */
#define GPIO1_BASE GPIOX_BASE(1)
#define GPIO1_REG32(offset) __REG32(GPIO1_BASE + (offset))
#define GPIO1_IRQENABLE1 GPIO1_REG32(0x01C)
#define GPIO1_IRQSTATUS1 GPIO1_REG32(0x018)
#define GPIO1_IRQENABLE2 GPIO1_REG32(0x02C)
#define GPIO1_IRQSTATUS2 GPIO1_REG32(0x028)
#define GPIO1_WAKEUPENABLE GPIO1_REG32(0x020)
#define GPIO1_RISINGDETECT GPIO1_REG32(0x048)
#define GPIO1_DATAIN GPIO1_REG32(0x038)
#define GPIO1_OE GPIO1_REG32(0x034)
#define GPIO1_DATAOUT GPIO1_REG32(0x03C)
/* GPIO2 */
#define GPIO2_BASE GPIOX_BASE(2)
#define GPIO2_REG32(offset) __REG32(GPIO2_BASE + (offset))
#define GPIO2_IRQENABLE1 GPIO2_REG32(0x01C)
#define GPIO2_IRQSTATUS1 GPIO2_REG32(0x018)
#define GPIO2_IRQENABLE2 GPIO2_REG32(0x02C)
#define GPIO2_IRQSTATUS2 GPIO2_REG32(0x028)
#define GPIO2_WAKEUPENABLE GPIO2_REG32(0x020)
#define GPIO2_RISINGDETECT GPIO2_REG32(0x048)
#define GPIO2_DATAIN GPIO2_REG32(0x038)
#define GPIO2_OE GPIO2_REG32(0x034)
#define GPIO2_DATAOUT GPIO2_REG32(0x03C)
/* GPIO 3 */
#define GPIO3_BASE GPIOX_BASE(3)
#define GPIO3_REG32(offset) __REG32(GPIO3_BASE + (offset))
#define GPIO3_IRQENABLE1 GPIO3_REG32(0x01C)
#define GPIO3_IRQSTATUS1 GPIO3_REG32(0x018)
#define GPIO3_IRQENABLE2 GPIO3_REG32(0x02C)
#define GPIO3_IRQSTATUS2 GPIO3_REG32(0x028)
#define GPIO3_WAKEUPENABLE GPIO3_REG32(0x020)
#define GPIO3_RISINGDETECT GPIO3_REG32(0x048)
#define GPIO3_FALLINGDETECT GPIO3_REG32(0x04C)
#define GPIO3_DATAIN GPIO3_REG32(0x038)
#define GPIO3_OE GPIO3_REG32(0x034)
#define GPIO3_DATAOUT GPIO3_REG32(0x03C)
#define GPIO3_DEBOUNCENABLE GPIO3_REG32(0x050)
#define GPIO3_DEBOUNCINGTIME GPIO3_REG32(0x054)
/* GPIO 4 */
#define GPIO4_BASE GPIOX_BASE(4)
#define GPIO4_REG32(offset) __REG32(GPIO4_BASE + (offset))
#define GPIO4_IRQENABLE1 GPIO4_REG32(0x01C)
#define GPIO4_IRQSTATUS1 GPIO4_REG32(0x018)
#define GPIO4_IRQENABLE2 GPIO4_REG32(0x02C)
#define GPIO4_IRQSTATUS2 GPIO4_REG32(0x028)
#define GPIO4_WAKEUPENABLE GPIO4_REG32(0x020)
#define GPIO4_RISINGDETECT GPIO4_REG32(0x048)
#define GPIO4_FALLINGDETECT GPIO4_REG32(0x04C)
#define GPIO4_DATAIN GPIO4_REG32(0x038)
#define GPIO4_OE GPIO4_REG32(0x034)
#define GPIO4_DATAOUT GPIO4_REG32(0x03C)
#define GPIO4_DEBOUNCENABLE GPIO4_REG32(0x050)
#define GPIO4_DEBOUNCINGTIME GPIO4_REG32(0x054)
/* IO CONFIG */
#define CONTROL_BASE (OMAP24XX_CTRL_BASE)
#define CONTROL_REG32(offset) __REG32(CONTROL_BASE + (offset))
#define CONTROL_PADCONF_SPI1_NCS2 CONTROL_REG32(0x104)
#define CONTROL_PADCONF_SYS_XTALOUT CONTROL_REG32(0x134)
#define CONTROL_PADCONF_UART1_RX CONTROL_REG32(0x0C8)
#define CONTROL_PADCONF_MCBSP1_DX CONTROL_REG32(0x10C)
#define CONTROL_PADCONF_GPMC_NCS4 CONTROL_REG32(0x090)
#define CONTROL_PADCONF_DSS_D5 CONTROL_REG32(0x0B8)
#define CONTROL_PADCONF_DSS_D9 CONTROL_REG32(0x0BC)
#define CONTROL_PADCONF_DSS_D13 CONTROL_REG32(0x0C0)
#define CONTROL_PADCONF_DSS_VSYNC CONTROL_REG32(0x0CC)
/* CONTROL */
#define CONTROL_DEVCONF CONTROL_REG32(0x274)
/* INTERRUPT CONTROLLER */
#define INTC_BASE (OMAP24XX_L4_IO_BASE+0xfe000)
#define INTC_REG32(offset) __REG32(INTC_BASE + (offset))
#define INTC1_U_BASE INTC_REG32(0x000)
#define INTC_MIR0 INTC_REG32(0x084)
#define INTC_MIR_SET0 INTC_REG32(0x08C)
#define INTC_MIR_CLEAR0 INTC_REG32(0x088)
#define INTC_ISR_CLEAR0 INTC_REG32(0x094)
#define INTC_MIR1 INTC_REG32(0x0A4)
#define INTC_MIR_SET1 INTC_REG32(0x0AC)
#define INTC_MIR_CLEAR1 INTC_REG32(0x0A8)
#define INTC_ISR_CLEAR1 INTC_REG32(0x0B4)
#define INTC_MIR2 INTC_REG32(0x0C4)
#define INTC_MIR_SET2 INTC_REG32(0x0CC)
#define INTC_MIR_CLEAR2 INTC_REG32(0x0C8)
#define INTC_ISR_CLEAR2 INTC_REG32(0x0D4)
#define INTC_SIR_IRQ INTC_REG32(0x040)
#define INTC_CONTROL INTC_REG32(0x048)
#define INTC_ILR11 INTC_REG32(0x12C)
#define INTC_ILR32 INTC_REG32(0x180)
#define INTC_ILR37 INTC_REG32(0x194)
#define INTC_SYSCONFIG INTC_REG32(0x010)
/* RAM FIREWALL */
#define RAMFW_BASE (0x68005000)
#define RAMFW_REG32(offset) __REG32(RAMFW_BASE + (offset))
#define RAMFW_REQINFOPERM0 RAMFW_REG32(0x048)
#define RAMFW_READPERM0 RAMFW_REG32(0x050)
#define RAMFW_WRITEPERM0 RAMFW_REG32(0x058)
/* GPMC CS1 FPGA ON USER INTERFACE MODULE */
//#define DEBUG_BOARD_LED_REGISTER 0x04000014
/* GPMC CS0 */
#define GPMC_CONFIG1_0 GPMC_REG32(0x060)
#define GPMC_CONFIG2_0 GPMC_REG32(0x064)
#define GPMC_CONFIG3_0 GPMC_REG32(0x068)
#define GPMC_CONFIG4_0 GPMC_REG32(0x06C)
#define GPMC_CONFIG5_0 GPMC_REG32(0x070)
#define GPMC_CONFIG6_0 GPMC_REG32(0x074)
#define GPMC_CONFIG7_0 GPMC_REG32(0x078)
/* DSS */
#define DSS_CONTROL DISP_REG32(0x040)
#define DISPC_CONTROL DISP_REG32(0x440)
#define DISPC_SYSSTATUS DISP_REG32(0x414)
#define DISPC_IRQSTATUS DISP_REG32(0x418)
#define DISPC_IRQENABLE DISP_REG32(0x41C)
#define DISPC_CONFIG DISP_REG32(0x444)
#define DISPC_DEFAULT_COLOR0 DISP_REG32(0x44C)
#define DISPC_DEFAULT_COLOR1 DISP_REG32(0x450)
#define DISPC_TRANS_COLOR0 DISP_REG32(0x454)
#define DISPC_TRANS_COLOR1 DISP_REG32(0x458)
#define DISPC_LINE_NUMBER DISP_REG32(0x460)
#define DISPC_TIMING_H DISP_REG32(0x464)
#define DISPC_TIMING_V DISP_REG32(0x468)
#define DISPC_POL_FREQ DISP_REG32(0x46C)
#define DISPC_DIVISOR DISP_REG32(0x470)
#define DISPC_SIZE_DIG DISP_REG32(0x478)
#define DISPC_SIZE_LCD DISP_REG32(0x47C)
#define DISPC_GFX_BA0 DISP_REG32(0x480)
#define DISPC_GFX_BA1 DISP_REG32(0x484)
#define DISPC_GFX_POSITION DISP_REG32(0x488)
#define DISPC_GFX_SIZE DISP_REG32(0x48C)
#define DISPC_GFX_ATTRIBUTES DISP_REG32(0x4A0)
#define DISPC_GFX_FIFO_THRESHOLD DISP_REG32(0x4A4)
#define DISPC_GFX_ROW_INC DISP_REG32(0x4AC)
#define DISPC_GFX_PIXEL_INC DISP_REG32(0x4B0)
#define DISPC_GFX_WINDOW_SKIP DISP_REG32(0x4B4)
#define DISPC_GFX_TABLE_BA DISP_REG32(0x4B8)
#define DISPC_DATA_CYCLE1 DISP_REG32(0x5D4)
#define DISPC_DATA_CYCLE2 DISP_REG32(0x5D8)
#define DISPC_DATA_CYCLE3 DISP_REG32(0x5DC)
/* Wake up define for board */
#define GPIO97 (1 << 1)
#define GPIO88 (1 << 24)
#endif /* __ASSEMBLER__ */
#endif
arch/arm/mach-omap2/serial.c 0 → 100644
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arch/arm/mach-omap2/sram-fn.S 0 → 100644
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arch/arm/mach-omap2/timer-gp.c 0 → 100644
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/*
* linux/arch/arm/mach-omap2/timer-gp.c
*
* OMAP2 GP timer support.
*
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@nokia.com>
* Juha Yrjl <juha.yrjola@nokia.com>
*
* Some parts based off of TI's 24xx code:
*
* Copyright (C) 2004 Texas Instruments, Inc.
*
* Roughly modelled after the OMAP1 MPU timer code.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <asm/mach/time.h>
#include <asm/delay.h>
#include <asm/io.h>
#include <asm/hardware/clock.h>
#define OMAP2_GP_TIMER1_BASE 0x48028000
#define OMAP2_GP_TIMER2_BASE 0x4802a000
#define OMAP2_GP_TIMER3_BASE 0x48078000
#define OMAP2_GP_TIMER4_BASE 0x4807a000
#define GP_TIMER_TIDR 0x00
#define GP_TIMER_TISR 0x18
#define GP_TIMER_TIER 0x1c
#define GP_TIMER_TCLR 0x24
#define GP_TIMER_TCRR 0x28
#define GP_TIMER_TLDR 0x2c
#define GP_TIMER_TSICR 0x40
#define OS_TIMER_NR 1 /* GP timer 2 */
static unsigned long timer_base[] = {
IO_ADDRESS(OMAP2_GP_TIMER1_BASE),
IO_ADDRESS(OMAP2_GP_TIMER2_BASE),
IO_ADDRESS(OMAP2_GP_TIMER3_BASE),
IO_ADDRESS(OMAP2_GP_TIMER4_BASE),
};
static inline unsigned int timer_read_reg(int nr, unsigned int reg)
{
return __raw_readl(timer_base[nr] + reg);
}
static inline void timer_write_reg(int nr, unsigned int reg, unsigned int val)
{
__raw_writel(val, timer_base[nr] + reg);
}
/* Note that we always enable the clock prescale divider bit */
static inline void omap2_gp_timer_start(int nr, unsigned long load_val)
{
unsigned int tmp;
tmp = 0xffffffff - load_val;
timer_write_reg(nr, GP_TIMER_TLDR, tmp);
timer_write_reg(nr, GP_TIMER_TCRR, tmp);
timer_write_reg(nr, GP_TIMER_TIER, 1 << 1);
timer_write_reg(nr, GP_TIMER_TCLR, (1 << 5) | (1 << 1) | 1);
}
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
struct pt_regs *regs)
{
write_seqlock(&xtime_lock);
timer_write_reg(OS_TIMER_NR, GP_TIMER_TISR, 1 << 1);
timer_tick(regs);
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
static struct irqaction omap2_gp_timer_irq = {
.name = "gp timer",
.flags = SA_INTERRUPT,
.handler = omap2_gp_timer_interrupt,
};
static void __init omap2_gp_timer_init(void)
{
struct clk * sys_ck;
u32 tick_period = 120000;
u32 l;
/* Reset clock and prescale value */
timer_write_reg(OS_TIMER_NR, GP_TIMER_TCLR, 0);
sys_ck = clk_get(NULL, "sys_ck");
if (IS_ERR(sys_ck))
printk(KERN_ERR "Could not get sys_ck\n");
else {
clk_use(sys_ck);
tick_period = clk_get_rate(sys_ck) / 100;
clk_put(sys_ck);
}
tick_period /= 2; /* Minimum prescale divider is 2 */
tick_period -= 1;
l = timer_read_reg(OS_TIMER_NR, GP_TIMER_TIDR);
printk(KERN_INFO "OMAP2 GP timer (HW version %d.%d)\n",
(l >> 4) & 0x0f, l & 0x0f);
setup_irq(38, &omap2_gp_timer_irq);
omap2_gp_timer_start(OS_TIMER_NR, tick_period);
}
struct sys_timer omap_timer = {
.init = omap2_gp_timer_init,
};
arch/arm/mach-pxa/Kconfig
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arch/arm/mach-pxa/Makefile
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......@@ -11,8 +11,8 @@ obj-$(CONFIG_PXA27x) += pxa27x.o
obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o ssp.o
obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o ssp.o
obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o
obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o
obj-$(CONFIG_MACH_POODLE) += poodle.o
obj-$(CONFIG_MACH_TOSA) += tosa.o
......@@ -26,6 +26,7 @@ obj-$(CONFIG_LEDS) += $(led-y)
# Misc features
obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_PXA_SSP) += ssp.o
ifeq ($(CONFIG_PXA27x),y)
obj-$(CONFIG_PM) += standby.o
......
arch/arm/mach-pxa/corgi_ssp.c
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arch/arm/mach-pxa/sharpsl.h
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arch/arm/mach-pxa/sharpsl_pm.c 0 → 100644
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arch/arm/mach-pxa/ssp.c
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arch/arm/mm/Kconfig
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arch/arm/plat-omap/Makefile
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arch/arm/plat-omap/clock.c
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arch/arm/plat-omap/clock.h 已删除 100644 → 0
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arch/arm/plat-omap/common.c
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arch/arm/plat-omap/devices.c 0 → 100644
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arch/arm/plat-omap/dma.c
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arch/arm/plat-omap/gpio.c
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arch/arm/plat-omap/mcbsp.c
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arch/arm/plat-omap/mux.c
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arch/arm/plat-omap/pm.c
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arch/arm/plat-omap/sleep.S
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arch/arm/plat-omap/sram.c
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arch/arm/plat-omap/usb.c
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drivers/video/backlight/corgi_bl.c
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include/asm-arm/arch-ixp4xx/irqs.h
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include/asm-arm/arch-ixp4xx/nslu2.h 0 → 100644
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include/asm-arm/arch-omap/clock.h 0 → 100644
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include/asm-arm/arch-omap/common.h
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include/asm-arm/arch-omap/cpu.h
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include/asm-arm/arch-omap/dma.h
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include/asm-arm/arch-omap/fpga.h
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include/asm-arm/arch-omap/gpio.h
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include/asm-arm/arch-omap/io.h
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include/asm-arm/arch-omap/irqs.h
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include/asm-arm/arch-omap/memory.h
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include/asm-arm/arch-omap/menelaus.h 0 → 100644
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include/asm-arm/arch-omap/mux.h
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include/asm-arm/arch-omap/omapfb.h 0 → 100644
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include/asm-arm/arch-omap/pm.h
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include/asm-arm/arch-omap/prcm.h 0 → 100644
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include/asm-arm/arch-omap/system.h
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include/asm-arm/arch-omap/timex.h
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include/asm-arm/arch-pxa/sharpsl.h
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include/asm-arm/arch-pxa/ssp.h
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