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提交 9a170cae 编写于 作者: D Dave Airlie
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Merge remote branch 'intel/drm-intel-next' of ../drm-next into drm-core-next 

* 'intel/drm-intel-next' of ../drm-next: (266 commits)
  drm/i915: Avoid circular locking from intel_fbdev_fini()
  drm/i915: mark display port DPMS state as 'ON' when enabling output
  drm/i915: Skip pread/pwrite if size to copy is 0.
  drm/i915: avoid struct mutex output_poll mutex lock loop on unload
  drm/i915: Rephrase pwrite bounds checking to avoid any potential overflow
  drm/i915: Sanity check pread/pwrite
  drm/i915: Use pipe state to tell when pipe is off
  drm/i915: vblank status not valid while training display port
  drivers/gpu/drm/i915/i915_gem.c: Add missing error handling code
  drm/i915: Don't mask the return code whilst relocating.
  drm/i915: If the GPU hangs twice within 5 seconds, declare it wedged.
  drm/i915: Only print 'generating error event' if we actually are
  drm/i915: Try to reset gen2 devices.
  drm/i915: Clear fence registers on GPU reset
  drm/i915: Force the domain to CPU on unbinding whilst wedged.
  drm: Move the GTT accounting to i915
  drm/i915: Fix refleak during eviction.
  i915: Added function to initialize VBT settings
  drm/i915: Remove redundant deletion of obj->gpu_write_list
  drm/i915: Make get/put pages static
  ...
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MAINTAINERS
浏览文件 @ 9a170cae
...@@ -2051,6 +2051,15 @@ S: Maintained ...@@ -2051,6 +2051,15 @@ S: Maintained
F: drivers/gpu/drm/ F: drivers/gpu/drm/
F: include/drm/ F: include/drm/
INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
M: Chris Wilson <chris@chris-wilson.co.uk>
L: intel-gfx@lists.freedesktop.org
L: dri-devel@lists.freedesktop.org
T: git git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel.git
S: Supported
F: drivers/gpu/drm/i915
F: include/drm/i915*
DSCC4 DRIVER DSCC4 DRIVER
M: Francois Romieu <romieu@fr.zoreil.com> M: Francois Romieu <romieu@fr.zoreil.com>
L: netdev@vger.kernel.org L: netdev@vger.kernel.org
......
drivers/char/agp/Makefile
浏览文件 @ 9a170cae
...@@ -13,6 +13,7 @@ obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o ...@@ -13,6 +13,7 @@ obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
obj-$(CONFIG_AGP_PARISC) += parisc-agp.o obj-$(CONFIG_AGP_PARISC) += parisc-agp.o
obj-$(CONFIG_AGP_I460) += i460-agp.o obj-$(CONFIG_AGP_I460) += i460-agp.o
obj-$(CONFIG_AGP_INTEL) += intel-agp.o obj-$(CONFIG_AGP_INTEL) += intel-agp.o
obj-$(CONFIG_AGP_INTEL) += intel-gtt.o
obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o
obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o
obj-$(CONFIG_AGP_SIS) += sis-agp.o obj-$(CONFIG_AGP_SIS) += sis-agp.o
......
drivers/char/agp/agp.h
浏览文件 @ 9a170cae
...@@ -121,11 +121,6 @@ struct agp_bridge_driver { ...@@ -121,11 +121,6 @@ struct agp_bridge_driver {
void (*agp_destroy_pages)(struct agp_memory *); void (*agp_destroy_pages)(struct agp_memory *);
int (*agp_type_to_mask_type) (struct agp_bridge_data *, int); int (*agp_type_to_mask_type) (struct agp_bridge_data *, int);
void (*chipset_flush)(struct agp_bridge_data *); void (*chipset_flush)(struct agp_bridge_data *);
int (*agp_map_page)(struct page *page, dma_addr_t *ret);
void (*agp_unmap_page)(struct page *page, dma_addr_t dma);
int (*agp_map_memory)(struct agp_memory *mem);
void (*agp_unmap_memory)(struct agp_memory *mem);
}; };
struct agp_bridge_data { struct agp_bridge_data {
......
drivers/char/agp/backend.c
浏览文件 @ 9a170cae
...@@ -151,17 +151,7 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge) ...@@ -151,17 +151,7 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
} }
bridge->scratch_page_page = page; bridge->scratch_page_page = page;
if (bridge->driver->agp_map_page) { bridge->scratch_page_dma = page_to_phys(page);
if (bridge->driver->agp_map_page(page,
&bridge->scratch_page_dma)) {
dev_err(&bridge->dev->dev,
"unable to dma-map scratch page\n");
rc = -ENOMEM;
goto err_out_nounmap;
}
} else {
bridge->scratch_page_dma = page_to_phys(page);
}
bridge->scratch_page = bridge->driver->mask_memory(bridge, bridge->scratch_page = bridge->driver->mask_memory(bridge,
bridge->scratch_page_dma, 0); bridge->scratch_page_dma, 0);
...@@ -204,12 +194,6 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge) ...@@ -204,12 +194,6 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
return 0; return 0;
err_out: err_out:
if (bridge->driver->needs_scratch_page &&
bridge->driver->agp_unmap_page) {
bridge->driver->agp_unmap_page(bridge->scratch_page_page,
bridge->scratch_page_dma);
}
err_out_nounmap:
if (bridge->driver->needs_scratch_page) { if (bridge->driver->needs_scratch_page) {
void *va = page_address(bridge->scratch_page_page); void *va = page_address(bridge->scratch_page_page);
...@@ -240,10 +224,6 @@ static void agp_backend_cleanup(struct agp_bridge_data *bridge) ...@@ -240,10 +224,6 @@ static void agp_backend_cleanup(struct agp_bridge_data *bridge)
bridge->driver->needs_scratch_page) { bridge->driver->needs_scratch_page) {
void *va = page_address(bridge->scratch_page_page); void *va = page_address(bridge->scratch_page_page);
if (bridge->driver->agp_unmap_page)
bridge->driver->agp_unmap_page(bridge->scratch_page_page,
bridge->scratch_page_dma);
bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP); bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_UNMAP);
bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE); bridge->driver->agp_destroy_page(va, AGP_PAGE_DESTROY_FREE);
} }
......
drivers/char/agp/generic.c
浏览文件 @ 9a170cae
...@@ -437,11 +437,6 @@ int agp_bind_memory(struct agp_memory *curr, off_t pg_start) ...@@ -437,11 +437,6 @@ int agp_bind_memory(struct agp_memory *curr, off_t pg_start)
curr->is_flushed = true; curr->is_flushed = true;
} }
if (curr->bridge->driver->agp_map_memory) {
ret_val = curr->bridge->driver->agp_map_memory(curr);
if (ret_val)
return ret_val;
}
ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type); ret_val = curr->bridge->driver->insert_memory(curr, pg_start, curr->type);
if (ret_val != 0) if (ret_val != 0)
...@@ -483,9 +478,6 @@ int agp_unbind_memory(struct agp_memory *curr) ...@@ -483,9 +478,6 @@ int agp_unbind_memory(struct agp_memory *curr)
if (ret_val != 0) if (ret_val != 0)
return ret_val; return ret_val;
if (curr->bridge->driver->agp_unmap_memory)
curr->bridge->driver->agp_unmap_memory(curr);
curr->is_bound = false; curr->is_bound = false;
curr->pg_start = 0; curr->pg_start = 0;
spin_lock(&curr->bridge->mapped_lock); spin_lock(&curr->bridge->mapped_lock);
......
drivers/char/agp/intel-agp.c
浏览文件 @ 9a170cae
...@@ -12,9 +12,6 @@ ...@@ -12,9 +12,6 @@
#include <asm/smp.h> #include <asm/smp.h>
#include "agp.h" #include "agp.h"
#include "intel-agp.h" #include "intel-agp.h"
#include <linux/intel-gtt.h>
#include "intel-gtt.c"
int intel_agp_enabled; int intel_agp_enabled;
EXPORT_SYMBOL(intel_agp_enabled); EXPORT_SYMBOL(intel_agp_enabled);
...@@ -703,179 +700,37 @@ static const struct agp_bridge_driver intel_7505_driver = { ...@@ -703,179 +700,37 @@ static const struct agp_bridge_driver intel_7505_driver = {
.agp_type_to_mask_type = agp_generic_type_to_mask_type, .agp_type_to_mask_type = agp_generic_type_to_mask_type,
}; };
static int find_gmch(u16 device)
{
struct pci_dev *gmch_device;
gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
device, gmch_device);
}
if (!gmch_device)
return 0;
intel_private.pcidev = gmch_device;
return 1;
}
/* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
* driver and gmch_driver must be non-null, and find_gmch will determine * driver and gmch_driver must be non-null, and find_gmch will determine
* which one should be used if a gmch_chip_id is present. * which one should be used if a gmch_chip_id is present.
*/ */
static const struct intel_driver_description { static const struct intel_agp_driver_description {
unsigned int chip_id; unsigned int chip_id;
unsigned int gmch_chip_id;
char *name; char *name;
const struct agp_bridge_driver *driver; const struct agp_bridge_driver *driver;
const struct agp_bridge_driver *gmch_driver;
} intel_agp_chipsets[] = { } intel_agp_chipsets[] = {
{ PCI_DEVICE_ID_INTEL_82443LX_0, 0, "440LX", &intel_generic_driver, NULL }, { PCI_DEVICE_ID_INTEL_82443LX_0, "440LX", &intel_generic_driver },
{ PCI_DEVICE_ID_INTEL_82443BX_0, 0, "440BX", &intel_generic_driver, NULL }, { PCI_DEVICE_ID_INTEL_82443BX_0, "440BX", &intel_generic_driver },
{ PCI_DEVICE_ID_INTEL_82443GX_0, 0, "440GX", &intel_generic_driver, NULL }, { PCI_DEVICE_ID_INTEL_82443GX_0, "440GX", &intel_generic_driver },
{ PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, "i810", { PCI_DEVICE_ID_INTEL_82815_MC, "i815", &intel_815_driver },
NULL, &intel_810_driver }, { PCI_DEVICE_ID_INTEL_82820_HB, "i820", &intel_820_driver },
{ PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, "i810", { PCI_DEVICE_ID_INTEL_82820_UP_HB, "i820", &intel_820_driver },
NULL, &intel_810_driver }, { PCI_DEVICE_ID_INTEL_82830_HB, "830M", &intel_830mp_driver },
{ PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, "i810", { PCI_DEVICE_ID_INTEL_82840_HB, "i840", &intel_840_driver },
NULL, &intel_810_driver }, { PCI_DEVICE_ID_INTEL_82845_HB, "845G", &intel_845_driver },
{ PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, "i815", { PCI_DEVICE_ID_INTEL_82845G_HB, "830M", &intel_845_driver },
&intel_815_driver, &intel_810_driver }, { PCI_DEVICE_ID_INTEL_82850_HB, "i850", &intel_850_driver },
{ PCI_DEVICE_ID_INTEL_82820_HB, 0, "i820", &intel_820_driver, NULL }, { PCI_DEVICE_ID_INTEL_82854_HB, "854", &intel_845_driver },
{ PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, "i820", &intel_820_driver, NULL }, { PCI_DEVICE_ID_INTEL_82855PM_HB, "855PM", &intel_845_driver },
{ PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, "830M", { PCI_DEVICE_ID_INTEL_82855GM_HB, "855GM", &intel_845_driver },
&intel_830mp_driver, &intel_830_driver }, { PCI_DEVICE_ID_INTEL_82860_HB, "i860", &intel_860_driver },
{ PCI_DEVICE_ID_INTEL_82840_HB, 0, "i840", &intel_840_driver, NULL }, { PCI_DEVICE_ID_INTEL_82865_HB, "865", &intel_845_driver },
{ PCI_DEVICE_ID_INTEL_82845_HB, 0, "845G", &intel_845_driver, NULL }, { PCI_DEVICE_ID_INTEL_82875_HB, "i875", &intel_845_driver },
{ PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, "830M", { PCI_DEVICE_ID_INTEL_7505_0, "E7505", &intel_7505_driver },
&intel_845_driver, &intel_830_driver }, { PCI_DEVICE_ID_INTEL_7205_0, "E7205", &intel_7505_driver },
{ PCI_DEVICE_ID_INTEL_82850_HB, 0, "i850", &intel_850_driver, NULL }, { 0, NULL, NULL }
{ PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, "854",
&intel_845_driver, &intel_830_driver },
{ PCI_DEVICE_ID_INTEL_82855PM_HB, 0, "855PM", &intel_845_driver, NULL },
{ PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
&intel_845_driver, &intel_830_driver },
{ PCI_DEVICE_ID_INTEL_82860_HB, 0, "i860", &intel_860_driver, NULL },
{ PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, "865",
&intel_845_driver, &intel_830_driver },
{ PCI_DEVICE_ID_INTEL_82875_HB, 0, "i875", &intel_845_driver, NULL },
{ PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
NULL, &intel_915_driver },
{ PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
NULL, &intel_915_driver },
{ PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
NULL, &intel_915_driver },
{ PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
NULL, &intel_915_driver },
{ PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
NULL, &intel_915_driver },
{ PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
NULL, &intel_915_driver },
{ PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_7505_0, 0, "E7505", &intel_7505_driver, NULL },
{ PCI_DEVICE_ID_INTEL_7205_0, 0, "E7205", &intel_7505_driver, NULL },
{ PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, "G33",
NULL, &intel_g33_driver },
{ PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
NULL, &intel_g33_driver },
{ PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
NULL, &intel_g33_driver },
{ PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
NULL, &intel_g33_driver },
{ PCI_DEVICE_ID_INTEL_PINEVIEW_HB, PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
NULL, &intel_g33_driver },
{ PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG,
"GM45", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_EAGLELAKE_HB, PCI_DEVICE_ID_INTEL_EAGLELAKE_IG,
"Eaglelake", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG,
"Q45/Q43", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG,
"G45/G43", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_B43_HB, PCI_DEVICE_ID_INTEL_B43_IG,
"B43", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_B43_1_HB, PCI_DEVICE_ID_INTEL_B43_1_IG,
"B43", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG,
"G41", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
"HD Graphics", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
"HD Graphics", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
"HD Graphics", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB, PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
"HD Graphics", NULL, &intel_i965_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
"Sandybridge", NULL, &intel_gen6_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
"Sandybridge", NULL, &intel_gen6_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
"Sandybridge", NULL, &intel_gen6_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
"Sandybridge", NULL, &intel_gen6_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
"Sandybridge", NULL, &intel_gen6_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
"Sandybridge", NULL, &intel_gen6_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB, PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
"Sandybridge", NULL, &intel_gen6_driver },
{ 0, 0, NULL, NULL, NULL }
}; };
static int __devinit intel_gmch_probe(struct pci_dev *pdev,
struct agp_bridge_data *bridge)
{
int i, mask;
bridge->driver = NULL;
for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
bridge->driver =
intel_agp_chipsets[i].gmch_driver;
break;
}
}
if (!bridge->driver)
return 0;
bridge->dev_private_data = &intel_private;
bridge->dev = pdev;
dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
if (bridge->driver->mask_memory == intel_gen6_mask_memory)
mask = 40;
else if (bridge->driver->mask_memory == intel_i965_mask_memory)
mask = 36;
else
mask = 32;
if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
dev_err(&intel_private.pcidev->dev,
"set gfx device dma mask %d-bit failed!\n", mask);
else
pci_set_consistent_dma_mask(intel_private.pcidev,
DMA_BIT_MASK(mask));
return 1;
}
static int __devinit agp_intel_probe(struct pci_dev *pdev, static int __devinit agp_intel_probe(struct pci_dev *pdev,
const struct pci_device_id *ent) const struct pci_device_id *ent)
{ {
...@@ -905,7 +760,7 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev, ...@@ -905,7 +760,7 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
} }
} }
if (intel_agp_chipsets[i].name == NULL) { if (!bridge->driver) {
if (cap_ptr) if (cap_ptr)
dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n", dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
pdev->vendor, pdev->device); pdev->vendor, pdev->device);
...@@ -913,14 +768,6 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev, ...@@ -913,14 +768,6 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
return -ENODEV; return -ENODEV;
} }
if (!bridge->driver) {
if (cap_ptr)
dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
intel_agp_chipsets[i].gmch_chip_id);
agp_put_bridge(bridge);
return -ENODEV;
}
bridge->dev = pdev; bridge->dev = pdev;
bridge->dev_private_data = NULL; bridge->dev_private_data = NULL;
...@@ -972,8 +819,7 @@ static void __devexit agp_intel_remove(struct pci_dev *pdev) ...@@ -972,8 +819,7 @@ static void __devexit agp_intel_remove(struct pci_dev *pdev)
agp_remove_bridge(bridge); agp_remove_bridge(bridge);
if (intel_private.pcidev) intel_gmch_remove(pdev);
pci_dev_put(intel_private.pcidev);
agp_put_bridge(bridge); agp_put_bridge(bridge);
} }
......
drivers/char/agp/intel-agp.h
浏览文件 @ 9a170cae
...@@ -215,44 +215,7 @@ ...@@ -215,44 +215,7 @@
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */ #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A #define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
/* cover 915 and 945 variants */ int intel_gmch_probe(struct pci_dev *pdev,
#define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \ struct agp_bridge_data *bridge);
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \ void intel_gmch_remove(struct pci_dev *pdev);
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
#define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
#define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
#define IS_PINEVIEW (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_PINEVIEW_HB)
#define IS_SNB (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB)
#define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_EAGLELAKE_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_B43_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB || \
agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB || \
IS_SNB)
#endif #endif
drivers/char/agp/intel-gtt.c
浏览文件 @ 9a170cae
此差异已折叠。
drivers/gpu/drm/drm_debugfs.c
浏览文件 @ 9a170cae
...@@ -48,7 +48,6 @@ static struct drm_info_list drm_debugfs_list[] = { ...@@ -48,7 +48,6 @@ static struct drm_info_list drm_debugfs_list[] = {
{"queues", drm_queues_info, 0}, {"queues", drm_queues_info, 0},
{"bufs", drm_bufs_info, 0}, {"bufs", drm_bufs_info, 0},
{"gem_names", drm_gem_name_info, DRIVER_GEM}, {"gem_names", drm_gem_name_info, DRIVER_GEM},
{"gem_objects", drm_gem_object_info, DRIVER_GEM},
#if DRM_DEBUG_CODE #if DRM_DEBUG_CODE
{"vma", drm_vma_info, 0}, {"vma", drm_vma_info, 0},
#endif #endif
......
drivers/gpu/drm/drm_edid.c
浏览文件 @ 9a170cae
...@@ -30,7 +30,6 @@ ...@@ -30,7 +30,6 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/i2c.h> #include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include "drmP.h" #include "drmP.h"
#include "drm_edid.h" #include "drm_edid.h"
#include "drm_edid_modes.h" #include "drm_edid_modes.h"
......
drivers/gpu/drm/drm_gem.c
浏览文件 @ 9a170cae
...@@ -92,12 +92,6 @@ drm_gem_init(struct drm_device *dev) ...@@ -92,12 +92,6 @@ drm_gem_init(struct drm_device *dev)
spin_lock_init(&dev->object_name_lock); spin_lock_init(&dev->object_name_lock);
idr_init(&dev->object_name_idr); idr_init(&dev->object_name_idr);
atomic_set(&dev->object_count, 0);
atomic_set(&dev->object_memory, 0);
atomic_set(&dev->pin_count, 0);
atomic_set(&dev->pin_memory, 0);
atomic_set(&dev->gtt_count, 0);
atomic_set(&dev->gtt_memory, 0);
mm = kzalloc(sizeof(struct drm_gem_mm), GFP_KERNEL); mm = kzalloc(sizeof(struct drm_gem_mm), GFP_KERNEL);
if (!mm) { if (!mm) {
...@@ -151,9 +145,6 @@ int drm_gem_object_init(struct drm_device *dev, ...@@ -151,9 +145,6 @@ int drm_gem_object_init(struct drm_device *dev,
kref_init(&obj->handlecount); kref_init(&obj->handlecount);
obj->size = size; obj->size = size;
atomic_inc(&dev->object_count);
atomic_add(obj->size, &dev->object_memory);
return 0; return 0;
} }
EXPORT_SYMBOL(drm_gem_object_init); EXPORT_SYMBOL(drm_gem_object_init);
...@@ -180,8 +171,6 @@ drm_gem_object_alloc(struct drm_device *dev, size_t size) ...@@ -180,8 +171,6 @@ drm_gem_object_alloc(struct drm_device *dev, size_t size)
return obj; return obj;
fput: fput:
/* Object_init mangles the global counters - readjust them. */ /* Object_init mangles the global counters - readjust them. */
atomic_dec(&dev->object_count);
atomic_sub(obj->size, &dev->object_memory);
fput(obj->filp); fput(obj->filp);
free: free:
kfree(obj); kfree(obj);
...@@ -436,10 +425,7 @@ drm_gem_release(struct drm_device *dev, struct drm_file *file_private) ...@@ -436,10 +425,7 @@ drm_gem_release(struct drm_device *dev, struct drm_file *file_private)
void void
drm_gem_object_release(struct drm_gem_object *obj) drm_gem_object_release(struct drm_gem_object *obj)
{ {
struct drm_device *dev = obj->dev;
fput(obj->filp); fput(obj->filp);
atomic_dec(&dev->object_count);
atomic_sub(obj->size, &dev->object_memory);
} }
EXPORT_SYMBOL(drm_gem_object_release); EXPORT_SYMBOL(drm_gem_object_release);
......
drivers/gpu/drm/drm_info.c
浏览文件 @ 9a170cae
...@@ -270,20 +270,6 @@ int drm_gem_name_info(struct seq_file *m, void *data) ...@@ -270,20 +270,6 @@ int drm_gem_name_info(struct seq_file *m, void *data)
return 0; return 0;
} }
int drm_gem_object_info(struct seq_file *m, void* data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
seq_printf(m, "%d objects\n", atomic_read(&dev->object_count));
seq_printf(m, "%d object bytes\n", atomic_read(&dev->object_memory));
seq_printf(m, "%d pinned\n", atomic_read(&dev->pin_count));
seq_printf(m, "%d pin bytes\n", atomic_read(&dev->pin_memory));
seq_printf(m, "%d gtt bytes\n", atomic_read(&dev->gtt_memory));
seq_printf(m, "%d gtt total\n", dev->gtt_total);
return 0;
}
#if DRM_DEBUG_CODE #if DRM_DEBUG_CODE
int drm_vma_info(struct seq_file *m, void *data) int drm_vma_info(struct seq_file *m, void *data)
......
drivers/gpu/drm/drm_proc.c
浏览文件 @ 9a170cae
...@@ -55,7 +55,6 @@ static struct drm_info_list drm_proc_list[] = { ...@@ -55,7 +55,6 @@ static struct drm_info_list drm_proc_list[] = {
{"queues", drm_queues_info, 0}, {"queues", drm_queues_info, 0},
{"bufs", drm_bufs_info, 0}, {"bufs", drm_bufs_info, 0},
{"gem_names", drm_gem_name_info, DRIVER_GEM}, {"gem_names", drm_gem_name_info, DRIVER_GEM},
{"gem_objects", drm_gem_object_info, DRIVER_GEM},
#if DRM_DEBUG_CODE #if DRM_DEBUG_CODE
{"vma", drm_vma_info, 0}, {"vma", drm_vma_info, 0},
#endif #endif
......
drivers/gpu/drm/i915/Makefile
浏览文件 @ 9a170cae
...@@ -26,13 +26,13 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ ...@@ -26,13 +26,13 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
intel_dvo.o \ intel_dvo.o \
intel_ringbuffer.o \ intel_ringbuffer.o \
intel_overlay.o \ intel_overlay.o \
intel_opregion.o \
dvo_ch7xxx.o \ dvo_ch7xxx.o \
dvo_ch7017.o \ dvo_ch7017.o \
dvo_ivch.o \ dvo_ivch.o \
dvo_tfp410.o \ dvo_tfp410.o \
dvo_sil164.o dvo_sil164.o
i915-$(CONFIG_ACPI) += i915_opregion.o
i915-$(CONFIG_COMPAT) += i915_ioc32.o i915-$(CONFIG_COMPAT) += i915_ioc32.o
obj-$(CONFIG_DRM_I915) += i915.o obj-$(CONFIG_DRM_I915) += i915.o
......
drivers/gpu/drm/i915/dvo_ch7017.c
浏览文件 @ 9a170cae
...@@ -165,67 +165,44 @@ struct ch7017_priv { ...@@ -165,67 +165,44 @@ struct ch7017_priv {
static void ch7017_dump_regs(struct intel_dvo_device *dvo); static void ch7017_dump_regs(struct intel_dvo_device *dvo);
static void ch7017_dpms(struct intel_dvo_device *dvo, int mode); static void ch7017_dpms(struct intel_dvo_device *dvo, int mode);
static bool ch7017_read(struct intel_dvo_device *dvo, int addr, uint8_t *val) static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val)
{ {
struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
u8 out_buf[2];
u8 in_buf[2];
struct i2c_msg msgs[] = { struct i2c_msg msgs[] = {
{ {
.addr = dvo->slave_addr, .addr = dvo->slave_addr,
.flags = 0, .flags = 0,
.len = 1, .len = 1,
.buf = out_buf, .buf = &addr,
}, },
{ {
.addr = dvo->slave_addr, .addr = dvo->slave_addr,
.flags = I2C_M_RD, .flags = I2C_M_RD,
.len = 1, .len = 1,
.buf = in_buf, .buf = val,
} }
}; };
return i2c_transfer(dvo->i2c_bus, msgs, 2) == 2;
out_buf[0] = addr;
out_buf[1] = 0;
if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) {
*val= in_buf[0];
return true;
};
return false;
} }
static bool ch7017_write(struct intel_dvo_device *dvo, int addr, uint8_t val) static bool ch7017_write(struct intel_dvo_device *dvo, u8 addr, u8 val)
{ {
struct i2c_adapter *adapter = dvo->i2c_bus; uint8_t buf[2] = { addr, val };
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
uint8_t out_buf[2];
struct i2c_msg msg = { struct i2c_msg msg = {
.addr = dvo->slave_addr, .addr = dvo->slave_addr,
.flags = 0, .flags = 0,
.len = 2, .len = 2,
.buf = out_buf, .buf = buf,
}; };
return i2c_transfer(dvo->i2c_bus, &msg, 1) == 1;
out_buf[0] = addr;
out_buf[1] = val;
if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
return true;
return false;
} }
/** Probes for a CH7017 on the given bus and slave address. */ /** Probes for a CH7017 on the given bus and slave address. */
static bool ch7017_init(struct intel_dvo_device *dvo, static bool ch7017_init(struct intel_dvo_device *dvo,
struct i2c_adapter *adapter) struct i2c_adapter *adapter)
{ {
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
struct ch7017_priv *priv; struct ch7017_priv *priv;
uint8_t val; const char *str;
u8 val;
priv = kzalloc(sizeof(struct ch7017_priv), GFP_KERNEL); priv = kzalloc(sizeof(struct ch7017_priv), GFP_KERNEL);
if (priv == NULL) if (priv == NULL)
...@@ -237,16 +214,27 @@ static bool ch7017_init(struct intel_dvo_device *dvo, ...@@ -237,16 +214,27 @@ static bool ch7017_init(struct intel_dvo_device *dvo,
if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val)) if (!ch7017_read(dvo, CH7017_DEVICE_ID, &val))
goto fail; goto fail;
if (val != CH7017_DEVICE_ID_VALUE && switch (val) {
val != CH7018_DEVICE_ID_VALUE && case CH7017_DEVICE_ID_VALUE:
val != CH7019_DEVICE_ID_VALUE) { str = "ch7017";
break;
case CH7018_DEVICE_ID_VALUE:
str = "ch7018";
break;
case CH7019_DEVICE_ID_VALUE:
str = "ch7019";
break;
default:
DRM_DEBUG_KMS("ch701x not detected, got %d: from %s " DRM_DEBUG_KMS("ch701x not detected, got %d: from %s "
"Slave %d.\n", "slave %d.\n",
val, i2cbus->adapter.name,dvo->slave_addr); val, adapter->name,dvo->slave_addr);
goto fail; goto fail;
} }
DRM_DEBUG_KMS("%s detected on %s, addr %d\n",
str, adapter->name, dvo->slave_addr);
return true; return true;
fail: fail:
kfree(priv); kfree(priv);
return false; return false;
...@@ -368,7 +356,7 @@ static void ch7017_dpms(struct intel_dvo_device *dvo, int mode) ...@@ -368,7 +356,7 @@ static void ch7017_dpms(struct intel_dvo_device *dvo, int mode)
} }
/* XXX: Should actually wait for update power status somehow */ /* XXX: Should actually wait for update power status somehow */
udelay(20000); msleep(20);
} }
static void ch7017_dump_regs(struct intel_dvo_device *dvo) static void ch7017_dump_regs(struct intel_dvo_device *dvo)
......
drivers/gpu/drm/i915/dvo_ch7xxx.c
浏览文件 @ 9a170cae
...@@ -113,7 +113,6 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) ...@@ -113,7 +113,6 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
{ {
struct ch7xxx_priv *ch7xxx= dvo->dev_priv; struct ch7xxx_priv *ch7xxx= dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus; struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
u8 out_buf[2]; u8 out_buf[2];
u8 in_buf[2]; u8 in_buf[2];
...@@ -135,14 +134,14 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) ...@@ -135,14 +134,14 @@ static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
out_buf[0] = addr; out_buf[0] = addr;
out_buf[1] = 0; out_buf[1] = 0;
if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) { if (i2c_transfer(adapter, msgs, 2) == 2) {
*ch = in_buf[0]; *ch = in_buf[0];
return true; return true;
}; };
if (!ch7xxx->quiet) { if (!ch7xxx->quiet) {
DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, adapter->name, dvo->slave_addr);
} }
return false; return false;
} }
...@@ -152,7 +151,6 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) ...@@ -152,7 +151,6 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
{ {
struct ch7xxx_priv *ch7xxx = dvo->dev_priv; struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus; struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
uint8_t out_buf[2]; uint8_t out_buf[2];
struct i2c_msg msg = { struct i2c_msg msg = {
.addr = dvo->slave_addr, .addr = dvo->slave_addr,
...@@ -164,12 +162,12 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) ...@@ -164,12 +162,12 @@ static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
out_buf[0] = addr; out_buf[0] = addr;
out_buf[1] = ch; out_buf[1] = ch;
if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1) if (i2c_transfer(adapter, &msg, 1) == 1)
return true; return true;
if (!ch7xxx->quiet) { if (!ch7xxx->quiet) {
DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, adapter->name, dvo->slave_addr);
} }
return false; return false;
......
drivers/gpu/drm/i915/dvo_ivch.c
浏览文件 @ 9a170cae
...@@ -167,7 +167,6 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data) ...@@ -167,7 +167,6 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
{ {
struct ivch_priv *priv = dvo->dev_priv; struct ivch_priv *priv = dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus; struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
u8 out_buf[1]; u8 out_buf[1];
u8 in_buf[2]; u8 in_buf[2];
...@@ -193,7 +192,7 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data) ...@@ -193,7 +192,7 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
out_buf[0] = addr; out_buf[0] = addr;
if (i2c_transfer(&i2cbus->adapter, msgs, 3) == 3) { if (i2c_transfer(adapter, msgs, 3) == 3) {
*data = (in_buf[1] << 8) | in_buf[0]; *data = (in_buf[1] << 8) | in_buf[0];
return true; return true;
}; };
...@@ -201,7 +200,7 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data) ...@@ -201,7 +200,7 @@ static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
if (!priv->quiet) { if (!priv->quiet) {
DRM_DEBUG_KMS("Unable to read register 0x%02x from " DRM_DEBUG_KMS("Unable to read register 0x%02x from "
"%s:%02x.\n", "%s:%02x.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, adapter->name, dvo->slave_addr);
} }
return false; return false;
} }
...@@ -211,7 +210,6 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data) ...@@ -211,7 +210,6 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
{ {
struct ivch_priv *priv = dvo->dev_priv; struct ivch_priv *priv = dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus; struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
u8 out_buf[3]; u8 out_buf[3];
struct i2c_msg msg = { struct i2c_msg msg = {
.addr = dvo->slave_addr, .addr = dvo->slave_addr,
...@@ -224,12 +222,12 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data) ...@@ -224,12 +222,12 @@ static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
out_buf[1] = data & 0xff; out_buf[1] = data & 0xff;
out_buf[2] = data >> 8; out_buf[2] = data >> 8;
if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1) if (i2c_transfer(adapter, &msg, 1) == 1)
return true; return true;
if (!priv->quiet) { if (!priv->quiet) {
DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, adapter->name, dvo->slave_addr);
} }
return false; return false;
......
drivers/gpu/drm/i915/dvo_sil164.c
浏览文件 @ 9a170cae
...@@ -69,7 +69,6 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) ...@@ -69,7 +69,6 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
{ {
struct sil164_priv *sil = dvo->dev_priv; struct sil164_priv *sil = dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus; struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
u8 out_buf[2]; u8 out_buf[2];
u8 in_buf[2]; u8 in_buf[2];
...@@ -91,14 +90,14 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) ...@@ -91,14 +90,14 @@ static bool sil164_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
out_buf[0] = addr; out_buf[0] = addr;
out_buf[1] = 0; out_buf[1] = 0;
if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) { if (i2c_transfer(adapter, msgs, 2) == 2) {
*ch = in_buf[0]; *ch = in_buf[0];
return true; return true;
}; };
if (!sil->quiet) { if (!sil->quiet) {
DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, adapter->name, dvo->slave_addr);
} }
return false; return false;
} }
...@@ -107,7 +106,6 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) ...@@ -107,7 +106,6 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
{ {
struct sil164_priv *sil= dvo->dev_priv; struct sil164_priv *sil= dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus; struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
uint8_t out_buf[2]; uint8_t out_buf[2];
struct i2c_msg msg = { struct i2c_msg msg = {
.addr = dvo->slave_addr, .addr = dvo->slave_addr,
...@@ -119,12 +117,12 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) ...@@ -119,12 +117,12 @@ static bool sil164_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
out_buf[0] = addr; out_buf[0] = addr;
out_buf[1] = ch; out_buf[1] = ch;
if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1) if (i2c_transfer(adapter, &msg, 1) == 1)
return true; return true;
if (!sil->quiet) { if (!sil->quiet) {
DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, adapter->name, dvo->slave_addr);
} }
return false; return false;
......
drivers/gpu/drm/i915/dvo_tfp410.c
浏览文件 @ 9a170cae
...@@ -94,7 +94,6 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) ...@@ -94,7 +94,6 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
{ {
struct tfp410_priv *tfp = dvo->dev_priv; struct tfp410_priv *tfp = dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus; struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
u8 out_buf[2]; u8 out_buf[2];
u8 in_buf[2]; u8 in_buf[2];
...@@ -116,14 +115,14 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch) ...@@ -116,14 +115,14 @@ static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
out_buf[0] = addr; out_buf[0] = addr;
out_buf[1] = 0; out_buf[1] = 0;
if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) { if (i2c_transfer(adapter, msgs, 2) == 2) {
*ch = in_buf[0]; *ch = in_buf[0];
return true; return true;
}; };
if (!tfp->quiet) { if (!tfp->quiet) {
DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n", DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, adapter->name, dvo->slave_addr);
} }
return false; return false;
} }
...@@ -132,7 +131,6 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) ...@@ -132,7 +131,6 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
{ {
struct tfp410_priv *tfp = dvo->dev_priv; struct tfp410_priv *tfp = dvo->dev_priv;
struct i2c_adapter *adapter = dvo->i2c_bus; struct i2c_adapter *adapter = dvo->i2c_bus;
struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
uint8_t out_buf[2]; uint8_t out_buf[2];
struct i2c_msg msg = { struct i2c_msg msg = {
.addr = dvo->slave_addr, .addr = dvo->slave_addr,
...@@ -144,12 +142,12 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch) ...@@ -144,12 +142,12 @@ static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
out_buf[0] = addr; out_buf[0] = addr;
out_buf[1] = ch; out_buf[1] = ch;
if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1) if (i2c_transfer(adapter, &msg, 1) == 1)
return true; return true;
if (!tfp->quiet) { if (!tfp->quiet) {
DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
addr, i2cbus->adapter.name, dvo->slave_addr); addr, adapter->name, dvo->slave_addr);
} }
return false; return false;
......
drivers/gpu/drm/i915/i915_debugfs.c
浏览文件 @ 9a170cae
...@@ -40,9 +40,51 @@ ...@@ -40,9 +40,51 @@
#if defined(CONFIG_DEBUG_FS) #if defined(CONFIG_DEBUG_FS)
#define ACTIVE_LIST 1 enum {
#define FLUSHING_LIST 2 RENDER_LIST,
#define INACTIVE_LIST 3 BSD_LIST,
FLUSHING_LIST,
INACTIVE_LIST,
PINNED_LIST,
DEFERRED_FREE_LIST,
};
static const char *yesno(int v)
{
return v ? "yes" : "no";
}
static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
const struct intel_device_info *info = INTEL_INFO(dev);
seq_printf(m, "gen: %d\n", info->gen);
#define B(x) seq_printf(m, #x ": %s\n", yesno(info->x))
B(is_mobile);
B(is_i85x);
B(is_i915g);
B(is_i945gm);
B(is_g33);
B(need_gfx_hws);
B(is_g4x);
B(is_pineview);
B(is_broadwater);
B(is_crestline);
B(is_ironlake);
B(has_fbc);
B(has_rc6);
B(has_pipe_cxsr);
B(has_hotplug);
B(cursor_needs_physical);
B(has_overlay);
B(overlay_needs_physical);
B(supports_tv);
#undef B
return 0;
}
static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv) static const char *get_pin_flag(struct drm_i915_gem_object *obj_priv)
{ {
...@@ -64,6 +106,27 @@ static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv) ...@@ -64,6 +106,27 @@ static const char *get_tiling_flag(struct drm_i915_gem_object *obj_priv)
} }
} }
static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
seq_printf(m, "%p: %s%s %8zd %08x %08x %d%s%s",
&obj->base,
get_pin_flag(obj),
get_tiling_flag(obj),
obj->base.size,
obj->base.read_domains,
obj->base.write_domain,
obj->last_rendering_seqno,
obj->dirty ? " dirty" : "",
obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
if (obj->base.name)
seq_printf(m, " (name: %d)", obj->base.name);
if (obj->fence_reg != I915_FENCE_REG_NONE)
seq_printf(m, " (fence: %d)", obj->fence_reg);
if (obj->gtt_space != NULL)
seq_printf(m, " (gtt_offset: %08x)", obj->gtt_offset);
}
static int i915_gem_object_list_info(struct seq_file *m, void *data) static int i915_gem_object_list_info(struct seq_file *m, void *data)
{ {
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
...@@ -72,56 +135,84 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data) ...@@ -72,56 +135,84 @@ static int i915_gem_object_list_info(struct seq_file *m, void *data)
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj_priv; struct drm_i915_gem_object *obj_priv;
spinlock_t *lock = NULL; size_t total_obj_size, total_gtt_size;
int count, ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
switch (list) { switch (list) {
case ACTIVE_LIST: case RENDER_LIST:
seq_printf(m, "Active:\n"); seq_printf(m, "Render:\n");
lock = &dev_priv->mm.active_list_lock;
head = &dev_priv->render_ring.active_list; head = &dev_priv->render_ring.active_list;
break; break;
case BSD_LIST:
seq_printf(m, "BSD:\n");
head = &dev_priv->bsd_ring.active_list;
break;
case INACTIVE_LIST: case INACTIVE_LIST:
seq_printf(m, "Inactive:\n"); seq_printf(m, "Inactive:\n");
head = &dev_priv->mm.inactive_list; head = &dev_priv->mm.inactive_list;
break; break;
case PINNED_LIST:
seq_printf(m, "Pinned:\n");
head = &dev_priv->mm.pinned_list;
break;
case FLUSHING_LIST: case FLUSHING_LIST:
seq_printf(m, "Flushing:\n"); seq_printf(m, "Flushing:\n");
head = &dev_priv->mm.flushing_list; head = &dev_priv->mm.flushing_list;
break; break;
case DEFERRED_FREE_LIST:
seq_printf(m, "Deferred free:\n");
head = &dev_priv->mm.deferred_free_list;
break;
default: default:
DRM_INFO("Ooops, unexpected list\n"); mutex_unlock(&dev->struct_mutex);
return 0; return -EINVAL;
} }
if (lock) total_obj_size = total_gtt_size = count = 0;
spin_lock(lock); list_for_each_entry(obj_priv, head, list) {
list_for_each_entry(obj_priv, head, list) seq_printf(m, " ");
{ describe_obj(m, obj_priv);
seq_printf(m, " %p: %s %8zd %08x %08x %d%s%s",
&obj_priv->base,
get_pin_flag(obj_priv),
obj_priv->base.size,
obj_priv->base.read_domains,
obj_priv->base.write_domain,
obj_priv->last_rendering_seqno,
obj_priv->dirty ? " dirty" : "",
obj_priv->madv == I915_MADV_DONTNEED ? " purgeable" : "");
if (obj_priv->base.name)
seq_printf(m, " (name: %d)", obj_priv->base.name);
if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
seq_printf(m, " (fence: %d)", obj_priv->fence_reg);
if (obj_priv->gtt_space != NULL)
seq_printf(m, " (gtt_offset: %08x)", obj_priv->gtt_offset);
seq_printf(m, "\n"); seq_printf(m, "\n");
total_obj_size += obj_priv->base.size;
total_gtt_size += obj_priv->gtt_space->size;
count++;
} }
mutex_unlock(&dev->struct_mutex);
if (lock) seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
spin_unlock(lock); count, total_obj_size, total_gtt_size);
return 0; return 0;
} }
static int i915_gem_object_info(struct seq_file *m, void* data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
seq_printf(m, "%u objects\n", dev_priv->mm.object_count);
seq_printf(m, "%zu object bytes\n", dev_priv->mm.object_memory);
seq_printf(m, "%u pinned\n", dev_priv->mm.pin_count);
seq_printf(m, "%zu pin bytes\n", dev_priv->mm.pin_memory);
seq_printf(m, "%u objects in gtt\n", dev_priv->mm.gtt_count);
seq_printf(m, "%zu gtt bytes\n", dev_priv->mm.gtt_memory);
seq_printf(m, "%zu gtt total\n", dev_priv->mm.gtt_total);
mutex_unlock(&dev->struct_mutex);
return 0;
}
static int i915_gem_pageflip_info(struct seq_file *m, void *data) static int i915_gem_pageflip_info(struct seq_file *m, void *data)
{ {
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
...@@ -176,6 +267,11 @@ static int i915_gem_request_info(struct seq_file *m, void *data) ...@@ -176,6 +267,11 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
struct drm_i915_gem_request *gem_request; struct drm_i915_gem_request *gem_request;
int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
seq_printf(m, "Request:\n"); seq_printf(m, "Request:\n");
list_for_each_entry(gem_request, &dev_priv->render_ring.request_list, list_for_each_entry(gem_request, &dev_priv->render_ring.request_list,
...@@ -184,6 +280,8 @@ static int i915_gem_request_info(struct seq_file *m, void *data) ...@@ -184,6 +280,8 @@ static int i915_gem_request_info(struct seq_file *m, void *data)
gem_request->seqno, gem_request->seqno,
(int) (jiffies - gem_request->emitted_jiffies)); (int) (jiffies - gem_request->emitted_jiffies));
} }
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
...@@ -192,16 +290,24 @@ static int i915_gem_seqno_info(struct seq_file *m, void *data) ...@@ -192,16 +290,24 @@ static int i915_gem_seqno_info(struct seq_file *m, void *data)
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
if (dev_priv->render_ring.status_page.page_addr != NULL) { if (dev_priv->render_ring.status_page.page_addr != NULL) {
seq_printf(m, "Current sequence: %d\n", seq_printf(m, "Current sequence: %d\n",
i915_get_gem_seqno(dev, &dev_priv->render_ring)); dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring));
} else { } else {
seq_printf(m, "Current sequence: hws uninitialized\n"); seq_printf(m, "Current sequence: hws uninitialized\n");
} }
seq_printf(m, "Waiter sequence: %d\n", seq_printf(m, "Waiter sequence: %d\n",
dev_priv->mm.waiting_gem_seqno); dev_priv->mm.waiting_gem_seqno);
seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno); seq_printf(m, "IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno);
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
...@@ -211,6 +317,11 @@ static int i915_interrupt_info(struct seq_file *m, void *data) ...@@ -211,6 +317,11 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
if (!HAS_PCH_SPLIT(dev)) { if (!HAS_PCH_SPLIT(dev)) {
seq_printf(m, "Interrupt enable: %08x\n", seq_printf(m, "Interrupt enable: %08x\n",
...@@ -247,7 +358,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) ...@@ -247,7 +358,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
atomic_read(&dev_priv->irq_received)); atomic_read(&dev_priv->irq_received));
if (dev_priv->render_ring.status_page.page_addr != NULL) { if (dev_priv->render_ring.status_page.page_addr != NULL) {
seq_printf(m, "Current sequence: %d\n", seq_printf(m, "Current sequence: %d\n",
i915_get_gem_seqno(dev, &dev_priv->render_ring)); dev_priv->render_ring.get_seqno(dev, &dev_priv->render_ring));
} else { } else {
seq_printf(m, "Current sequence: hws uninitialized\n"); seq_printf(m, "Current sequence: hws uninitialized\n");
} }
...@@ -255,6 +366,8 @@ static int i915_interrupt_info(struct seq_file *m, void *data) ...@@ -255,6 +366,8 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
dev_priv->mm.waiting_gem_seqno); dev_priv->mm.waiting_gem_seqno);
seq_printf(m, "IRQ sequence: %d\n", seq_printf(m, "IRQ sequence: %d\n",
dev_priv->mm.irq_gem_seqno); dev_priv->mm.irq_gem_seqno);
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
...@@ -263,7 +376,11 @@ static int i915_gem_fence_regs_info(struct seq_file *m, void *data) ...@@ -263,7 +376,11 @@ static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
int i; int i, ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
...@@ -289,6 +406,7 @@ static int i915_gem_fence_regs_info(struct seq_file *m, void *data) ...@@ -289,6 +406,7 @@ static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
seq_printf(m, "\n"); seq_printf(m, "\n");
} }
} }
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
...@@ -313,16 +431,19 @@ static int i915_hws_info(struct seq_file *m, void *data) ...@@ -313,16 +431,19 @@ static int i915_hws_info(struct seq_file *m, void *data)
return 0; return 0;
} }
static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_count) static void i915_dump_object(struct seq_file *m,
struct io_mapping *mapping,
struct drm_i915_gem_object *obj_priv)
{ {
int page, i; int page, page_count, i;
uint32_t *mem;
page_count = obj_priv->base.size / PAGE_SIZE;
for (page = 0; page < page_count; page++) { for (page = 0; page < page_count; page++) {
mem = kmap_atomic(pages[page], KM_USER0); u32 *mem = io_mapping_map_wc(mapping,
obj_priv->gtt_offset + page * PAGE_SIZE);
for (i = 0; i < PAGE_SIZE; i += 4) for (i = 0; i < PAGE_SIZE; i += 4)
seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
kunmap_atomic(mem, KM_USER0); io_mapping_unmap(mem);
} }
} }
...@@ -335,27 +456,21 @@ static int i915_batchbuffer_info(struct seq_file *m, void *data) ...@@ -335,27 +456,21 @@ static int i915_batchbuffer_info(struct seq_file *m, void *data)
struct drm_i915_gem_object *obj_priv; struct drm_i915_gem_object *obj_priv;
int ret; int ret;
spin_lock(&dev_priv->mm.active_list_lock); ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
list_for_each_entry(obj_priv, &dev_priv->render_ring.active_list, list_for_each_entry(obj_priv, &dev_priv->render_ring.active_list,
list) { list) {
obj = &obj_priv->base; obj = &obj_priv->base;
if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) { if (obj->read_domains & I915_GEM_DOMAIN_COMMAND) {
ret = i915_gem_object_get_pages(obj, 0); seq_printf(m, "--- gtt_offset = 0x%08x\n",
if (ret) { obj_priv->gtt_offset);
DRM_ERROR("Failed to get pages: %d\n", ret); i915_dump_object(m, dev_priv->mm.gtt_mapping, obj_priv);
spin_unlock(&dev_priv->mm.active_list_lock);
return ret;
}
seq_printf(m, "--- gtt_offset = 0x%08x\n", obj_priv->gtt_offset);
i915_dump_pages(m, obj_priv->pages, obj->size / PAGE_SIZE);
i915_gem_object_put_pages(obj);
} }
} }
spin_unlock(&dev_priv->mm.active_list_lock); mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
...@@ -365,20 +480,24 @@ static int i915_ringbuffer_data(struct seq_file *m, void *data) ...@@ -365,20 +480,24 @@ static int i915_ringbuffer_data(struct seq_file *m, void *data)
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
u8 *virt; int ret;
uint32_t *ptr, off;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
if (!dev_priv->render_ring.gem_object) { if (!dev_priv->render_ring.gem_object) {
seq_printf(m, "No ringbuffer setup\n"); seq_printf(m, "No ringbuffer setup\n");
return 0; } else {
} u8 *virt = dev_priv->render_ring.virtual_start;
uint32_t off;
virt = dev_priv->render_ring.virtual_start;
for (off = 0; off < dev_priv->render_ring.size; off += 4) { for (off = 0; off < dev_priv->render_ring.size; off += 4) {
ptr = (uint32_t *)(virt + off); uint32_t *ptr = (uint32_t *)(virt + off);
seq_printf(m, "%08x : %08x\n", off, *ptr); seq_printf(m, "%08x : %08x\n", off, *ptr);
}
} }
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
...@@ -396,7 +515,7 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) ...@@ -396,7 +515,7 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data)
seq_printf(m, "RingHead : %08x\n", head); seq_printf(m, "RingHead : %08x\n", head);
seq_printf(m, "RingTail : %08x\n", tail); seq_printf(m, "RingTail : %08x\n", tail);
seq_printf(m, "RingSize : %08lx\n", dev_priv->render_ring.size); seq_printf(m, "RingSize : %08lx\n", dev_priv->render_ring.size);
seq_printf(m, "Acthd : %08x\n", I915_READ(IS_I965G(dev) ? ACTHD_I965 : ACTHD)); seq_printf(m, "Acthd : %08x\n", I915_READ(INTEL_INFO(dev)->gen >= 4 ? ACTHD_I965 : ACTHD));
return 0; return 0;
} }
...@@ -458,7 +577,7 @@ static int i915_error_state(struct seq_file *m, void *unused) ...@@ -458,7 +577,7 @@ static int i915_error_state(struct seq_file *m, void *unused)
seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr); seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr);
seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone); seq_printf(m, " INSTDONE: 0x%08x\n", error->instdone);
seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); seq_printf(m, " ACTHD: 0x%08x\n", error->acthd);
if (IS_I965G(dev)) { if (INTEL_INFO(dev)->gen >= 4) {
seq_printf(m, " INSTPS: 0x%08x\n", error->instps); seq_printf(m, " INSTPS: 0x%08x\n", error->instps);
seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1);
} }
...@@ -642,6 +761,9 @@ static int i915_fbc_status(struct seq_file *m, void *unused) ...@@ -642,6 +761,9 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
} else { } else {
seq_printf(m, "FBC disabled: "); seq_printf(m, "FBC disabled: ");
switch (dev_priv->no_fbc_reason) { switch (dev_priv->no_fbc_reason) {
case FBC_NO_OUTPUT:
seq_printf(m, "no outputs");
break;
case FBC_STOLEN_TOO_SMALL: case FBC_STOLEN_TOO_SMALL:
seq_printf(m, "not enough stolen memory"); seq_printf(m, "not enough stolen memory");
break; break;
...@@ -675,15 +797,17 @@ static int i915_sr_status(struct seq_file *m, void *unused) ...@@ -675,15 +797,17 @@ static int i915_sr_status(struct seq_file *m, void *unused)
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
bool sr_enabled = false; bool sr_enabled = false;
if (IS_I965GM(dev) || IS_I945G(dev) || IS_I945GM(dev)) if (IS_IRONLAKE(dev))
sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
else if (IS_I915GM(dev)) else if (IS_I915GM(dev))
sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
else if (IS_PINEVIEW(dev)) else if (IS_PINEVIEW(dev))
sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN; sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
seq_printf(m, "self-refresh: %s\n", sr_enabled ? "enabled" : seq_printf(m, "self-refresh: %s\n",
"disabled"); sr_enabled ? "enabled" : "disabled");
return 0; return 0;
} }
...@@ -694,10 +818,16 @@ static int i915_emon_status(struct seq_file *m, void *unused) ...@@ -694,10 +818,16 @@ static int i915_emon_status(struct seq_file *m, void *unused)
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
unsigned long temp, chipset, gfx; unsigned long temp, chipset, gfx;
int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
temp = i915_mch_val(dev_priv); temp = i915_mch_val(dev_priv);
chipset = i915_chipset_val(dev_priv); chipset = i915_chipset_val(dev_priv);
gfx = i915_gfx_val(dev_priv); gfx = i915_gfx_val(dev_priv);
mutex_unlock(&dev->struct_mutex);
seq_printf(m, "GMCH temp: %ld\n", temp); seq_printf(m, "GMCH temp: %ld\n", temp);
seq_printf(m, "Chipset power: %ld\n", chipset); seq_printf(m, "Chipset power: %ld\n", chipset);
...@@ -718,6 +848,68 @@ static int i915_gfxec(struct seq_file *m, void *unused) ...@@ -718,6 +848,68 @@ static int i915_gfxec(struct seq_file *m, void *unused)
return 0; return 0;
} }
static int i915_opregion(struct seq_file *m, void *unused)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
struct intel_opregion *opregion = &dev_priv->opregion;
int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
if (opregion->header)
seq_write(m, opregion->header, OPREGION_SIZE);
mutex_unlock(&dev->struct_mutex);
return 0;
}
static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
struct intel_fbdev *ifbdev;
struct intel_framebuffer *fb;
int ret;
ret = mutex_lock_interruptible(&dev->mode_config.mutex);
if (ret)
return ret;
ifbdev = dev_priv->fbdev;
fb = to_intel_framebuffer(ifbdev->helper.fb);
seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
fb->base.width,
fb->base.height,
fb->base.depth,
fb->base.bits_per_pixel);
describe_obj(m, to_intel_bo(fb->obj));
seq_printf(m, "\n");
list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
if (&fb->base == ifbdev->helper.fb)
continue;
seq_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
fb->base.width,
fb->base.height,
fb->base.depth,
fb->base.bits_per_pixel);
describe_obj(m, to_intel_bo(fb->obj));
seq_printf(m, "\n");
}
mutex_unlock(&dev->mode_config.mutex);
return 0;
}
static int static int
i915_wedged_open(struct inode *inode, i915_wedged_open(struct inode *inode,
struct file *filp) struct file *filp)
...@@ -741,6 +933,9 @@ i915_wedged_read(struct file *filp, ...@@ -741,6 +933,9 @@ i915_wedged_read(struct file *filp,
"wedged : %d\n", "wedged : %d\n",
atomic_read(&dev_priv->mm.wedged)); atomic_read(&dev_priv->mm.wedged));
if (len > sizeof (buf))
len = sizeof (buf);
return simple_read_from_buffer(ubuf, max, ppos, buf, len); return simple_read_from_buffer(ubuf, max, ppos, buf, len);
} }
...@@ -770,7 +965,7 @@ i915_wedged_write(struct file *filp, ...@@ -770,7 +965,7 @@ i915_wedged_write(struct file *filp,
atomic_set(&dev_priv->mm.wedged, val); atomic_set(&dev_priv->mm.wedged, val);
if (val) { if (val) {
DRM_WAKEUP(&dev_priv->irq_queue); wake_up_all(&dev_priv->irq_queue);
queue_work(dev_priv->wq, &dev_priv->error_work); queue_work(dev_priv->wq, &dev_priv->error_work);
} }
...@@ -823,9 +1018,14 @@ static int i915_wedged_create(struct dentry *root, struct drm_minor *minor) ...@@ -823,9 +1018,14 @@ static int i915_wedged_create(struct dentry *root, struct drm_minor *minor)
} }
static struct drm_info_list i915_debugfs_list[] = { static struct drm_info_list i915_debugfs_list[] = {
{"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST}, {"i915_capabilities", i915_capabilities, 0, 0},
{"i915_gem_objects", i915_gem_object_info, 0},
{"i915_gem_render_active", i915_gem_object_list_info, 0, (void *) RENDER_LIST},
{"i915_gem_bsd_active", i915_gem_object_list_info, 0, (void *) BSD_LIST},
{"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST}, {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
{"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST}, {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
{"i915_gem_pinned", i915_gem_object_list_info, 0, (void *) PINNED_LIST},
{"i915_gem_deferred_free", i915_gem_object_list_info, 0, (void *) DEFERRED_FREE_LIST},
{"i915_gem_pageflip", i915_gem_pageflip_info, 0}, {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
{"i915_gem_request", i915_gem_request_info, 0}, {"i915_gem_request", i915_gem_request_info, 0},
{"i915_gem_seqno", i915_gem_seqno_info, 0}, {"i915_gem_seqno", i915_gem_seqno_info, 0},
...@@ -845,6 +1045,8 @@ static struct drm_info_list i915_debugfs_list[] = { ...@@ -845,6 +1045,8 @@ static struct drm_info_list i915_debugfs_list[] = {
{"i915_gfxec", i915_gfxec, 0}, {"i915_gfxec", i915_gfxec, 0},
{"i915_fbc_status", i915_fbc_status, 0}, {"i915_fbc_status", i915_fbc_status, 0},
{"i915_sr_status", i915_sr_status, 0}, {"i915_sr_status", i915_sr_status, 0},
{"i915_opregion", i915_opregion, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
}; };
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
......
drivers/gpu/drm/i915/i915_dma.c
浏览文件 @ 9a170cae
...@@ -40,8 +40,7 @@ ...@@ -40,8 +40,7 @@
#include <linux/pnp.h> #include <linux/pnp.h>
#include <linux/vga_switcheroo.h> #include <linux/vga_switcheroo.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <acpi/video.h>
extern int intel_max_stolen; /* from AGP driver */
/** /**
* Sets up the hardware status page for devices that need a physical address * Sets up the hardware status page for devices that need a physical address
...@@ -64,7 +63,7 @@ static int i915_init_phys_hws(struct drm_device *dev) ...@@ -64,7 +63,7 @@ static int i915_init_phys_hws(struct drm_device *dev)
memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE); memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
if (IS_I965G(dev)) if (INTEL_INFO(dev)->gen >= 4)
dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) & dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
0xf0; 0xf0;
...@@ -222,7 +221,7 @@ static int i915_dma_resume(struct drm_device * dev) ...@@ -222,7 +221,7 @@ static int i915_dma_resume(struct drm_device * dev)
DRM_DEBUG_DRIVER("hw status page @ %p\n", DRM_DEBUG_DRIVER("hw status page @ %p\n",
ring->status_page.page_addr); ring->status_page.page_addr);
if (ring->status_page.gfx_addr != 0) if (ring->status_page.gfx_addr != 0)
ring->setup_status_page(dev, ring); intel_ring_setup_status_page(dev, ring);
else else
I915_WRITE(HWS_PGA, dev_priv->dma_status_page); I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
...@@ -377,7 +376,7 @@ i915_emit_box(struct drm_device *dev, ...@@ -377,7 +376,7 @@ i915_emit_box(struct drm_device *dev,
return -EINVAL; return -EINVAL;
} }
if (IS_I965G(dev)) { if (INTEL_INFO(dev)->gen >= 4) {
BEGIN_LP_RING(4); BEGIN_LP_RING(4);
OUT_RING(GFX_OP_DRAWRECT_INFO_I965); OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
OUT_RING((box.x1 & 0xffff) | (box.y1 << 16)); OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
...@@ -481,7 +480,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev, ...@@ -481,7 +480,7 @@ static int i915_dispatch_batchbuffer(struct drm_device * dev,
if (!IS_I830(dev) && !IS_845G(dev)) { if (!IS_I830(dev) && !IS_845G(dev)) {
BEGIN_LP_RING(2); BEGIN_LP_RING(2);
if (IS_I965G(dev)) { if (INTEL_INFO(dev)->gen >= 4) {
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965); OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
OUT_RING(batch->start); OUT_RING(batch->start);
} else { } else {
...@@ -888,12 +887,12 @@ static int ...@@ -888,12 +887,12 @@ static int
intel_alloc_mchbar_resource(struct drm_device *dev) intel_alloc_mchbar_resource(struct drm_device *dev)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp_lo, temp_hi = 0; u32 temp_lo, temp_hi = 0;
u64 mchbar_addr; u64 mchbar_addr;
int ret; int ret;
if (IS_I965G(dev)) if (INTEL_INFO(dev)->gen >= 4)
pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
mchbar_addr = ((u64)temp_hi << 32) | temp_lo; mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
...@@ -920,7 +919,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev) ...@@ -920,7 +919,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
return ret; return ret;
} }
if (IS_I965G(dev)) if (INTEL_INFO(dev)->gen >= 4)
pci_write_config_dword(dev_priv->bridge_dev, reg + 4, pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
upper_32_bits(dev_priv->mch_res.start)); upper_32_bits(dev_priv->mch_res.start));
...@@ -934,7 +933,7 @@ static void ...@@ -934,7 +933,7 @@ static void
intel_setup_mchbar(struct drm_device *dev) intel_setup_mchbar(struct drm_device *dev)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp; u32 temp;
bool enabled; bool enabled;
...@@ -971,7 +970,7 @@ static void ...@@ -971,7 +970,7 @@ static void
intel_teardown_mchbar(struct drm_device *dev) intel_teardown_mchbar(struct drm_device *dev)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915; int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
u32 temp; u32 temp;
if (dev_priv->mchbar_need_disable) { if (dev_priv->mchbar_need_disable) {
...@@ -990,174 +989,6 @@ intel_teardown_mchbar(struct drm_device *dev) ...@@ -990,174 +989,6 @@ intel_teardown_mchbar(struct drm_device *dev)
release_resource(&dev_priv->mch_res); release_resource(&dev_priv->mch_res);
} }
/**
* i915_probe_agp - get AGP bootup configuration
* @pdev: PCI device
* @aperture_size: returns AGP aperture configured size
* @preallocated_size: returns size of BIOS preallocated AGP space
*
* Since Intel integrated graphics are UMA, the BIOS has to set aside
* some RAM for the framebuffer at early boot. This code figures out
* how much was set aside so we can use it for our own purposes.
*/
static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
uint32_t *preallocated_size,
uint32_t *start)
{
struct drm_i915_private *dev_priv = dev->dev_private;
u16 tmp = 0;
unsigned long overhead;
unsigned long stolen;
/* Get the fb aperture size and "stolen" memory amount. */
pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
*aperture_size = 1024 * 1024;
*preallocated_size = 1024 * 1024;
switch (dev->pdev->device) {
case PCI_DEVICE_ID_INTEL_82830_CGC:
case PCI_DEVICE_ID_INTEL_82845G_IG:
case PCI_DEVICE_ID_INTEL_82855GM_IG:
case PCI_DEVICE_ID_INTEL_82865_IG:
if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
*aperture_size *= 64;
else
*aperture_size *= 128;
break;
default:
/* 9xx supports large sizes, just look at the length */
*aperture_size = pci_resource_len(dev->pdev, 2);
break;
}
/*
* Some of the preallocated space is taken by the GTT
* and popup. GTT is 1K per MB of aperture size, and popup is 4K.
*/
if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
overhead = 4096;
else
overhead = (*aperture_size / 1024) + 4096;
if (IS_GEN6(dev)) {
/* SNB has memory control reg at 0x50.w */
pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
case INTEL_855_GMCH_GMS_DISABLED:
DRM_ERROR("video memory is disabled\n");
return -1;
case SNB_GMCH_GMS_STOLEN_32M:
stolen = 32 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_64M:
stolen = 64 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_96M:
stolen = 96 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_128M:
stolen = 128 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_160M:
stolen = 160 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_192M:
stolen = 192 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_224M:
stolen = 224 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_256M:
stolen = 256 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_288M:
stolen = 288 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_320M:
stolen = 320 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_352M:
stolen = 352 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_384M:
stolen = 384 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_416M:
stolen = 416 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_448M:
stolen = 448 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_480M:
stolen = 480 * 1024 * 1024;
break;
case SNB_GMCH_GMS_STOLEN_512M:
stolen = 512 * 1024 * 1024;
break;
default:
DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
tmp & SNB_GMCH_GMS_STOLEN_MASK);
return -1;
}
} else {
switch (tmp & INTEL_GMCH_GMS_MASK) {
case INTEL_855_GMCH_GMS_DISABLED:
DRM_ERROR("video memory is disabled\n");
return -1;
case INTEL_855_GMCH_GMS_STOLEN_1M:
stolen = 1 * 1024 * 1024;
break;
case INTEL_855_GMCH_GMS_STOLEN_4M:
stolen = 4 * 1024 * 1024;
break;
case INTEL_855_GMCH_GMS_STOLEN_8M:
stolen = 8 * 1024 * 1024;
break;
case INTEL_855_GMCH_GMS_STOLEN_16M:
stolen = 16 * 1024 * 1024;
break;
case INTEL_855_GMCH_GMS_STOLEN_32M:
stolen = 32 * 1024 * 1024;
break;
case INTEL_915G_GMCH_GMS_STOLEN_48M:
stolen = 48 * 1024 * 1024;
break;
case INTEL_915G_GMCH_GMS_STOLEN_64M:
stolen = 64 * 1024 * 1024;
break;
case INTEL_GMCH_GMS_STOLEN_128M:
stolen = 128 * 1024 * 1024;
break;
case INTEL_GMCH_GMS_STOLEN_256M:
stolen = 256 * 1024 * 1024;
break;
case INTEL_GMCH_GMS_STOLEN_96M:
stolen = 96 * 1024 * 1024;
break;
case INTEL_GMCH_GMS_STOLEN_160M:
stolen = 160 * 1024 * 1024;
break;
case INTEL_GMCH_GMS_STOLEN_224M:
stolen = 224 * 1024 * 1024;
break;
case INTEL_GMCH_GMS_STOLEN_352M:
stolen = 352 * 1024 * 1024;
break;
default:
DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
tmp & INTEL_GMCH_GMS_MASK);
return -1;
}
}
*preallocated_size = stolen - overhead;
*start = overhead;
return 0;
}
#define PTE_ADDRESS_MASK 0xfffff000 #define PTE_ADDRESS_MASK 0xfffff000
#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */ #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
#define PTE_MAPPING_TYPE_UNCACHED (0 << 1) #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
...@@ -1181,11 +1012,11 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev, ...@@ -1181,11 +1012,11 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev,
{ {
unsigned long *gtt; unsigned long *gtt;
unsigned long entry, phys; unsigned long entry, phys;
int gtt_bar = IS_I9XX(dev) ? 0 : 1; int gtt_bar = IS_GEN2(dev) ? 1 : 0;
int gtt_offset, gtt_size; int gtt_offset, gtt_size;
if (IS_I965G(dev)) { if (INTEL_INFO(dev)->gen >= 4) {
if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) { if (IS_G4X(dev) || INTEL_INFO(dev)->gen > 4) {
gtt_offset = 2*1024*1024; gtt_offset = 2*1024*1024;
gtt_size = 2*1024*1024; gtt_size = 2*1024*1024;
} else { } else {
...@@ -1210,10 +1041,8 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev, ...@@ -1210,10 +1041,8 @@ static unsigned long i915_gtt_to_phys(struct drm_device *dev,
DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry); DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
/* Mask out these reserved bits on this hardware. */ /* Mask out these reserved bits on this hardware. */
if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) || if (INTEL_INFO(dev)->gen < 4 && !IS_G33(dev))
IS_I945G(dev) || IS_I945GM(dev)) {
entry &= ~PTE_ADDRESS_MASK_HIGH; entry &= ~PTE_ADDRESS_MASK_HIGH;
}
/* If it's not a mapping type we know, then bail. */ /* If it's not a mapping type we know, then bail. */
if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED && if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
...@@ -1252,7 +1081,7 @@ static void i915_setup_compression(struct drm_device *dev, int size) ...@@ -1252,7 +1081,7 @@ static void i915_setup_compression(struct drm_device *dev, int size)
unsigned long ll_base = 0; unsigned long ll_base = 0;
/* Leave 1M for line length buffer & misc. */ /* Leave 1M for line length buffer & misc. */
compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0); compressed_fb = drm_mm_search_free(&dev_priv->mm.vram, size, 4096, 0);
if (!compressed_fb) { if (!compressed_fb) {
dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
i915_warn_stolen(dev); i915_warn_stolen(dev);
...@@ -1273,7 +1102,7 @@ static void i915_setup_compression(struct drm_device *dev, int size) ...@@ -1273,7 +1102,7 @@ static void i915_setup_compression(struct drm_device *dev, int size)
} }
if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) { if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096, compressed_llb = drm_mm_search_free(&dev_priv->mm.vram, 4096,
4096, 0); 4096, 0);
if (!compressed_llb) { if (!compressed_llb) {
i915_warn_stolen(dev); i915_warn_stolen(dev);
...@@ -1343,10 +1172,8 @@ static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_ ...@@ -1343,10 +1172,8 @@ static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_
/* i915 resume handler doesn't set to D0 */ /* i915 resume handler doesn't set to D0 */
pci_set_power_state(dev->pdev, PCI_D0); pci_set_power_state(dev->pdev, PCI_D0);
i915_resume(dev); i915_resume(dev);
drm_kms_helper_poll_enable(dev);
} else { } else {
printk(KERN_ERR "i915: switched off\n"); printk(KERN_ERR "i915: switched off\n");
drm_kms_helper_poll_disable(dev);
i915_suspend(dev, pmm); i915_suspend(dev, pmm);
} }
} }
...@@ -1363,20 +1190,14 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev) ...@@ -1363,20 +1190,14 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
} }
static int i915_load_modeset_init(struct drm_device *dev, static int i915_load_modeset_init(struct drm_device *dev,
unsigned long prealloc_start,
unsigned long prealloc_size, unsigned long prealloc_size,
unsigned long agp_size) unsigned long agp_size)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
int fb_bar = IS_I9XX(dev) ? 2 : 0;
int ret = 0; int ret = 0;
dev->mode_config.fb_base = pci_resource_start(dev->pdev, fb_bar) & /* Basic memrange allocator for stolen space (aka mm.vram) */
0xff000000; drm_mm_init(&dev_priv->mm.vram, 0, prealloc_size);
/* Basic memrange allocator for stolen space (aka vram) */
drm_mm_init(&dev_priv->vram, 0, prealloc_size);
DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
/* We're off and running w/KMS */ /* We're off and running w/KMS */
dev_priv->mm.suspended = 0; dev_priv->mm.suspended = 0;
...@@ -1443,12 +1264,6 @@ static int i915_load_modeset_init(struct drm_device *dev, ...@@ -1443,12 +1264,6 @@ static int i915_load_modeset_init(struct drm_device *dev,
/* FIXME: do pre/post-mode set stuff in core KMS code */ /* FIXME: do pre/post-mode set stuff in core KMS code */
dev->vblank_disable_allowed = 1; dev->vblank_disable_allowed = 1;
/*
* Initialize the hardware status page IRQ location.
*/
I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
ret = intel_fbdev_init(dev); ret = intel_fbdev_init(dev);
if (ret) if (ret)
goto cleanup_irq; goto cleanup_irq;
...@@ -1787,9 +1602,9 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) ...@@ -1787,9 +1602,9 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
} }
} }
div_u64(diff, diff1); diff = div_u64(diff, diff1);
ret = ((m * diff) + c); ret = ((m * diff) + c);
div_u64(ret, 10); ret = div_u64(ret, 10);
dev_priv->last_count1 = total_count; dev_priv->last_count1 = total_count;
dev_priv->last_time1 = now; dev_priv->last_time1 = now;
...@@ -1858,7 +1673,7 @@ void i915_update_gfx_val(struct drm_i915_private *dev_priv) ...@@ -1858,7 +1673,7 @@ void i915_update_gfx_val(struct drm_i915_private *dev_priv)
/* More magic constants... */ /* More magic constants... */
diff = diff * 1181; diff = diff * 1181;
div_u64(diff, diffms * 10); diff = div_u64(diff, diffms * 10);
dev_priv->gfx_power = diff; dev_priv->gfx_power = diff;
} }
...@@ -1907,7 +1722,7 @@ static struct drm_i915_private *i915_mch_dev; ...@@ -1907,7 +1722,7 @@ static struct drm_i915_private *i915_mch_dev;
* - dev_priv->fmax * - dev_priv->fmax
* - dev_priv->gpu_busy * - dev_priv->gpu_busy
*/ */
DEFINE_SPINLOCK(mchdev_lock); static DEFINE_SPINLOCK(mchdev_lock);
/** /**
* i915_read_mch_val - return value for IPS use * i915_read_mch_val - return value for IPS use
...@@ -2062,7 +1877,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -2062,7 +1877,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
struct drm_i915_private *dev_priv; struct drm_i915_private *dev_priv;
resource_size_t base, size; resource_size_t base, size;
int ret = 0, mmio_bar; int ret = 0, mmio_bar;
uint32_t agp_size, prealloc_size, prealloc_start; uint32_t agp_size, prealloc_size;
/* i915 has 4 more counters */ /* i915 has 4 more counters */
dev->counters += 4; dev->counters += 4;
dev->types[6] = _DRM_STAT_IRQ; dev->types[6] = _DRM_STAT_IRQ;
...@@ -2079,7 +1894,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -2079,7 +1894,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
dev_priv->info = (struct intel_device_info *) flags; dev_priv->info = (struct intel_device_info *) flags;
/* Add register map (needed for suspend/resume) */ /* Add register map (needed for suspend/resume) */
mmio_bar = IS_I9XX(dev) ? 0 : 1; mmio_bar = IS_GEN2(dev) ? 1 : 0;
base = pci_resource_start(dev->pdev, mmio_bar); base = pci_resource_start(dev->pdev, mmio_bar);
size = pci_resource_len(dev->pdev, mmio_bar); size = pci_resource_len(dev->pdev, mmio_bar);
...@@ -2121,17 +1936,32 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -2121,17 +1936,32 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
"performance may suffer.\n"); "performance may suffer.\n");
} }
ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start); dev_priv->mm.gtt = intel_gtt_get();
if (ret) if (!dev_priv->mm.gtt) {
DRM_ERROR("Failed to initialize GTT\n");
ret = -ENODEV;
goto out_iomapfree; goto out_iomapfree;
if (prealloc_size > intel_max_stolen) {
DRM_INFO("detected %dM stolen memory, trimming to %dM\n",
prealloc_size >> 20, intel_max_stolen >> 20);
prealloc_size = intel_max_stolen;
} }
dev_priv->wq = create_singlethread_workqueue("i915"); prealloc_size = dev_priv->mm.gtt->gtt_stolen_entries << PAGE_SHIFT;
agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
/* The i915 workqueue is primarily used for batched retirement of
* requests (and thus managing bo) once the task has been completed
* by the GPU. i915_gem_retire_requests() is called directly when we
* need high-priority retirement, such as waiting for an explicit
* bo.
*
* It is also used for periodic low-priority events, such as
* idle-timers and hangcheck.
*
* All tasks on the workqueue are expected to acquire the dev mutex
* so there is no point in running more than one instance of the
* workqueue at any time: max_active = 1 and NON_REENTRANT.
*/
dev_priv->wq = alloc_workqueue("i915",
WQ_UNBOUND | WQ_NON_REENTRANT,
1);
if (dev_priv->wq == NULL) { if (dev_priv->wq == NULL) {
DRM_ERROR("Failed to create our workqueue.\n"); DRM_ERROR("Failed to create our workqueue.\n");
ret = -ENOMEM; ret = -ENOMEM;
...@@ -2166,6 +1996,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -2166,6 +1996,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
/* Try to make sure MCHBAR is enabled before poking at it */ /* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev); intel_setup_mchbar(dev);
intel_setup_gmbus(dev);
intel_opregion_setup(dev);
i915_gem_load(dev); i915_gem_load(dev);
...@@ -2212,8 +2044,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -2212,8 +2044,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_detect_pch(dev); intel_detect_pch(dev);
if (drm_core_check_feature(dev, DRIVER_MODESET)) { if (drm_core_check_feature(dev, DRIVER_MODESET)) {
ret = i915_load_modeset_init(dev, prealloc_start, ret = i915_load_modeset_init(dev, prealloc_size, agp_size);
prealloc_size, agp_size);
if (ret < 0) { if (ret < 0) {
DRM_ERROR("failed to init modeset\n"); DRM_ERROR("failed to init modeset\n");
goto out_workqueue_free; goto out_workqueue_free;
...@@ -2221,7 +2052,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -2221,7 +2052,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
} }
/* Must be done after probing outputs */ /* Must be done after probing outputs */
intel_opregion_init(dev, 0); intel_opregion_init(dev);
acpi_video_register();
setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
(unsigned long) dev); (unsigned long) dev);
...@@ -2249,15 +2081,20 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) ...@@ -2249,15 +2081,20 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
int i915_driver_unload(struct drm_device *dev) int i915_driver_unload(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
i915_destroy_error_state(dev);
spin_lock(&mchdev_lock); spin_lock(&mchdev_lock);
i915_mch_dev = NULL; i915_mch_dev = NULL;
spin_unlock(&mchdev_lock); spin_unlock(&mchdev_lock);
destroy_workqueue(dev_priv->wq); mutex_lock(&dev->struct_mutex);
del_timer_sync(&dev_priv->hangcheck_timer); ret = i915_gpu_idle(dev);
if (ret)
DRM_ERROR("failed to idle hardware: %d\n", ret);
mutex_unlock(&dev->struct_mutex);
/* Cancel the retire work handler, which should be idle now. */
cancel_delayed_work_sync(&dev_priv->mm.retire_work);
io_mapping_free(dev_priv->mm.gtt_mapping); io_mapping_free(dev_priv->mm.gtt_mapping);
if (dev_priv->mm.gtt_mtrr >= 0) { if (dev_priv->mm.gtt_mtrr >= 0) {
...@@ -2266,7 +2103,10 @@ int i915_driver_unload(struct drm_device *dev) ...@@ -2266,7 +2103,10 @@ int i915_driver_unload(struct drm_device *dev)
dev_priv->mm.gtt_mtrr = -1; dev_priv->mm.gtt_mtrr = -1;
} }
acpi_video_unregister();
if (drm_core_check_feature(dev, DRIVER_MODESET)) { if (drm_core_check_feature(dev, DRIVER_MODESET)) {
intel_fbdev_fini(dev);
intel_modeset_cleanup(dev); intel_modeset_cleanup(dev);
/* /*
...@@ -2278,20 +2118,28 @@ int i915_driver_unload(struct drm_device *dev) ...@@ -2278,20 +2118,28 @@ int i915_driver_unload(struct drm_device *dev)
dev_priv->child_dev = NULL; dev_priv->child_dev = NULL;
dev_priv->child_dev_num = 0; dev_priv->child_dev_num = 0;
} }
drm_irq_uninstall(dev);
vga_switcheroo_unregister_client(dev->pdev); vga_switcheroo_unregister_client(dev->pdev);
vga_client_register(dev->pdev, NULL, NULL, NULL); vga_client_register(dev->pdev, NULL, NULL, NULL);
} }
/* Free error state after interrupts are fully disabled. */
del_timer_sync(&dev_priv->hangcheck_timer);
cancel_work_sync(&dev_priv->error_work);
i915_destroy_error_state(dev);
if (dev->pdev->msi_enabled) if (dev->pdev->msi_enabled)
pci_disable_msi(dev->pdev); pci_disable_msi(dev->pdev);
if (dev_priv->regs != NULL) if (dev_priv->regs != NULL)
iounmap(dev_priv->regs); iounmap(dev_priv->regs);
intel_opregion_free(dev, 0); intel_opregion_fini(dev);
if (drm_core_check_feature(dev, DRIVER_MODESET)) { if (drm_core_check_feature(dev, DRIVER_MODESET)) {
/* Flush any outstanding unpin_work. */
flush_workqueue(dev_priv->wq);
i915_gem_free_all_phys_object(dev); i915_gem_free_all_phys_object(dev);
mutex_lock(&dev->struct_mutex); mutex_lock(&dev->struct_mutex);
...@@ -2299,34 +2147,35 @@ int i915_driver_unload(struct drm_device *dev) ...@@ -2299,34 +2147,35 @@ int i915_driver_unload(struct drm_device *dev)
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
if (I915_HAS_FBC(dev) && i915_powersave) if (I915_HAS_FBC(dev) && i915_powersave)
i915_cleanup_compression(dev); i915_cleanup_compression(dev);
drm_mm_takedown(&dev_priv->vram); drm_mm_takedown(&dev_priv->mm.vram);
i915_gem_lastclose(dev);
intel_cleanup_overlay(dev); intel_cleanup_overlay(dev);
} }
intel_teardown_gmbus(dev);
intel_teardown_mchbar(dev); intel_teardown_mchbar(dev);
destroy_workqueue(dev_priv->wq);
pci_dev_put(dev_priv->bridge_dev); pci_dev_put(dev_priv->bridge_dev);
kfree(dev->dev_private); kfree(dev->dev_private);
return 0; return 0;
} }
int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv) int i915_driver_open(struct drm_device *dev, struct drm_file *file)
{ {
struct drm_i915_file_private *i915_file_priv; struct drm_i915_file_private *file_priv;
DRM_DEBUG_DRIVER("\n"); DRM_DEBUG_DRIVER("\n");
i915_file_priv = (struct drm_i915_file_private *) file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
kmalloc(sizeof(*i915_file_priv), GFP_KERNEL); if (!file_priv)
if (!i915_file_priv)
return -ENOMEM; return -ENOMEM;
file_priv->driver_priv = i915_file_priv; file->driver_priv = file_priv;
INIT_LIST_HEAD(&i915_file_priv->mm.request_list); spin_lock_init(&file_priv->mm.lock);
INIT_LIST_HEAD(&file_priv->mm.request_list);
return 0; return 0;
} }
...@@ -2369,11 +2218,11 @@ void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv) ...@@ -2369,11 +2218,11 @@ void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
i915_mem_release(dev, file_priv, dev_priv->agp_heap); i915_mem_release(dev, file_priv, dev_priv->agp_heap);
} }
void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv) void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
{ {
struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; struct drm_i915_file_private *file_priv = file->driver_priv;
kfree(i915_file_priv); kfree(file_priv);
} }
struct drm_ioctl_desc i915_ioctls[] = { struct drm_ioctl_desc i915_ioctls[] = {
......
drivers/gpu/drm/i915/i915_drv.c
浏览文件 @ 9a170cae
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
#include "drm.h" #include "drm.h"
#include "i915_drm.h" #include "i915_drm.h"
#include "i915_drv.h" #include "i915_drv.h"
#include "intel_drv.h"
#include <linux/console.h> #include <linux/console.h>
#include "drm_crtc_helper.h" #include "drm_crtc_helper.h"
...@@ -61,86 +62,108 @@ extern int intel_agp_enabled; ...@@ -61,86 +62,108 @@ extern int intel_agp_enabled;
.driver_data = (unsigned long) info } .driver_data = (unsigned long) info }
static const struct intel_device_info intel_i830_info = { static const struct intel_device_info intel_i830_info = {
.gen = 2, .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1, .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
}; };
static const struct intel_device_info intel_845g_info = { static const struct intel_device_info intel_845g_info = {
.gen = 2, .is_i8xx = 1, .gen = 2,
.has_overlay = 1, .overlay_needs_physical = 1,
}; };
static const struct intel_device_info intel_i85x_info = { static const struct intel_device_info intel_i85x_info = {
.gen = 2, .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1, .gen = 2, .is_i85x = 1, .is_mobile = 1,
.cursor_needs_physical = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
}; };
static const struct intel_device_info intel_i865g_info = { static const struct intel_device_info intel_i865g_info = {
.gen = 2, .is_i8xx = 1, .gen = 2,
.has_overlay = 1, .overlay_needs_physical = 1,
}; };
static const struct intel_device_info intel_i915g_info = { static const struct intel_device_info intel_i915g_info = {
.gen = 3, .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1, .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
}; };
static const struct intel_device_info intel_i915gm_info = { static const struct intel_device_info intel_i915gm_info = {
.gen = 3, .is_i9xx = 1, .is_mobile = 1, .gen = 3, .is_mobile = 1,
.cursor_needs_physical = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
}; };
static const struct intel_device_info intel_i945g_info = { static const struct intel_device_info intel_i945g_info = {
.gen = 3, .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1, .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
}; };
static const struct intel_device_info intel_i945gm_info = { static const struct intel_device_info intel_i945gm_info = {
.gen = 3, .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .gen = 3, .is_i945gm = 1, .is_mobile = 1,
.has_hotplug = 1, .cursor_needs_physical = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
.has_overlay = 1, .overlay_needs_physical = 1,
.supports_tv = 1,
}; };
static const struct intel_device_info intel_i965g_info = { static const struct intel_device_info intel_i965g_info = {
.gen = 4, .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1, .gen = 4, .is_broadwater = 1,
.has_hotplug = 1, .has_hotplug = 1,
.has_overlay = 1,
}; };
static const struct intel_device_info intel_i965gm_info = { static const struct intel_device_info intel_i965gm_info = {
.gen = 4, .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1, .gen = 4, .is_crestline = 1,
.is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1, .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
.has_overlay = 1,
.supports_tv = 1,
}; };
static const struct intel_device_info intel_g33_info = { static const struct intel_device_info intel_g33_info = {
.gen = 3, .is_g33 = 1, .is_i9xx = 1, .gen = 3, .is_g33 = 1,
.need_gfx_hws = 1, .has_hotplug = 1, .need_gfx_hws = 1, .has_hotplug = 1,
.has_overlay = 1,
}; };
static const struct intel_device_info intel_g45_info = { static const struct intel_device_info intel_g45_info = {
.gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .need_gfx_hws = 1, .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
.has_pipe_cxsr = 1, .has_hotplug = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
}; };
static const struct intel_device_info intel_gm45_info = { static const struct intel_device_info intel_gm45_info = {
.gen = 4, .is_i965g = 1, .is_g4x = 1, .is_i9xx = 1, .gen = 4, .is_g4x = 1,
.is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1,
.has_pipe_cxsr = 1, .has_hotplug = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
.supports_tv = 1,
.has_bsd_ring = 1,
}; };
static const struct intel_device_info intel_pineview_info = { static const struct intel_device_info intel_pineview_info = {
.gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1, .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
.need_gfx_hws = 1, .has_hotplug = 1, .need_gfx_hws = 1, .has_hotplug = 1,
.has_overlay = 1,
}; };
static const struct intel_device_info intel_ironlake_d_info = { static const struct intel_device_info intel_ironlake_d_info = {
.gen = 5, .is_ironlake = 1, .is_i965g = 1, .is_i9xx = 1, .gen = 5, .is_ironlake = 1,
.need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1, .need_gfx_hws = 1, .has_pipe_cxsr = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
}; };
static const struct intel_device_info intel_ironlake_m_info = { static const struct intel_device_info intel_ironlake_m_info = {
.gen = 5, .is_ironlake = 1, .is_mobile = 1, .is_i965g = 1, .is_i9xx = 1, .gen = 5, .is_ironlake = 1, .is_mobile = 1,
.need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1, .need_gfx_hws = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
}; };
static const struct intel_device_info intel_sandybridge_d_info = { static const struct intel_device_info intel_sandybridge_d_info = {
.gen = 6, .is_i965g = 1, .is_i9xx = 1, .gen = 6,
.need_gfx_hws = 1, .has_hotplug = 1, .need_gfx_hws = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
}; };
static const struct intel_device_info intel_sandybridge_m_info = { static const struct intel_device_info intel_sandybridge_m_info = {
.gen = 6, .is_i965g = 1, .is_mobile = 1, .is_i9xx = 1, .gen = 6, .is_mobile = 1,
.need_gfx_hws = 1, .has_hotplug = 1, .need_gfx_hws = 1, .has_hotplug = 1,
.has_bsd_ring = 1,
}; };
static const struct pci_device_id pciidlist[] = { /* aka */ static const struct pci_device_id pciidlist[] = { /* aka */
...@@ -237,7 +260,7 @@ static int i915_drm_freeze(struct drm_device *dev) ...@@ -237,7 +260,7 @@ static int i915_drm_freeze(struct drm_device *dev)
i915_save_state(dev); i915_save_state(dev);
intel_opregion_free(dev, 1); intel_opregion_fini(dev);
/* Modeset on resume, not lid events */ /* Modeset on resume, not lid events */
dev_priv->modeset_on_lid = 0; dev_priv->modeset_on_lid = 0;
...@@ -258,6 +281,8 @@ int i915_suspend(struct drm_device *dev, pm_message_t state) ...@@ -258,6 +281,8 @@ int i915_suspend(struct drm_device *dev, pm_message_t state)
if (state.event == PM_EVENT_PRETHAW) if (state.event == PM_EVENT_PRETHAW)
return 0; return 0;
drm_kms_helper_poll_disable(dev);
error = i915_drm_freeze(dev); error = i915_drm_freeze(dev);
if (error) if (error)
return error; return error;
...@@ -277,8 +302,7 @@ static int i915_drm_thaw(struct drm_device *dev) ...@@ -277,8 +302,7 @@ static int i915_drm_thaw(struct drm_device *dev)
int error = 0; int error = 0;
i915_restore_state(dev); i915_restore_state(dev);
intel_opregion_setup(dev);
intel_opregion_init(dev, 1);
/* KMS EnterVT equivalent */ /* KMS EnterVT equivalent */
if (drm_core_check_feature(dev, DRIVER_MODESET)) { if (drm_core_check_feature(dev, DRIVER_MODESET)) {
...@@ -294,6 +318,8 @@ static int i915_drm_thaw(struct drm_device *dev) ...@@ -294,6 +318,8 @@ static int i915_drm_thaw(struct drm_device *dev)
drm_helper_resume_force_mode(dev); drm_helper_resume_force_mode(dev);
} }
intel_opregion_init(dev);
dev_priv->modeset_on_lid = 0; dev_priv->modeset_on_lid = 0;
return error; return error;
...@@ -301,12 +327,79 @@ static int i915_drm_thaw(struct drm_device *dev) ...@@ -301,12 +327,79 @@ static int i915_drm_thaw(struct drm_device *dev)
int i915_resume(struct drm_device *dev) int i915_resume(struct drm_device *dev)
{ {
int ret;
if (pci_enable_device(dev->pdev)) if (pci_enable_device(dev->pdev))
return -EIO; return -EIO;
pci_set_master(dev->pdev); pci_set_master(dev->pdev);
return i915_drm_thaw(dev); ret = i915_drm_thaw(dev);
if (ret)
return ret;
drm_kms_helper_poll_enable(dev);
return 0;
}
static int i8xx_do_reset(struct drm_device *dev, u8 flags)
{
struct drm_i915_private *dev_priv = dev->dev_private;
if (IS_I85X(dev))
return -ENODEV;
I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
POSTING_READ(D_STATE);
if (IS_I830(dev) || IS_845G(dev)) {
I915_WRITE(DEBUG_RESET_I830,
DEBUG_RESET_DISPLAY |
DEBUG_RESET_RENDER |
DEBUG_RESET_FULL);
POSTING_READ(DEBUG_RESET_I830);
msleep(1);
I915_WRITE(DEBUG_RESET_I830, 0);
POSTING_READ(DEBUG_RESET_I830);
}
msleep(1);
I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
POSTING_READ(D_STATE);
return 0;
}
static int i965_reset_complete(struct drm_device *dev)
{
u8 gdrst;
pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
return gdrst & 0x1;
}
static int i965_do_reset(struct drm_device *dev, u8 flags)
{
u8 gdrst;
/*
* Set the domains we want to reset (GRDOM/bits 2 and 3) as
* well as the reset bit (GR/bit 0). Setting the GR bit
* triggers the reset; when done, the hardware will clear it.
*/
pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
return wait_for(i965_reset_complete(dev), 500);
}
static int ironlake_do_reset(struct drm_device *dev, u8 flags)
{
struct drm_i915_private *dev_priv = dev->dev_private;
u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
} }
/** /**
...@@ -325,54 +418,39 @@ int i915_resume(struct drm_device *dev) ...@@ -325,54 +418,39 @@ int i915_resume(struct drm_device *dev)
* - re-init interrupt state * - re-init interrupt state
* - re-init display * - re-init display
*/ */
int i965_reset(struct drm_device *dev, u8 flags) int i915_reset(struct drm_device *dev, u8 flags)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
unsigned long timeout;
u8 gdrst;
/* /*
* We really should only reset the display subsystem if we actually * We really should only reset the display subsystem if we actually
* need to * need to
*/ */
bool need_display = true; bool need_display = true;
int ret;
mutex_lock(&dev->struct_mutex); mutex_lock(&dev->struct_mutex);
/* i915_gem_reset(dev);
* Clear request list
*/ ret = -ENODEV;
i915_gem_retire_requests(dev); if (get_seconds() - dev_priv->last_gpu_reset < 5) {
DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
if (need_display) } else switch (INTEL_INFO(dev)->gen) {
i915_save_display(dev); case 5:
ret = ironlake_do_reset(dev, flags);
if (IS_I965G(dev) || IS_G4X(dev)) { break;
/* case 4:
* Set the domains we want to reset, then the reset bit (bit 0). ret = i965_do_reset(dev, flags);
* Clear the reset bit after a while and wait for hardware status break;
* bit (bit 1) to be set case 2:
*/ ret = i8xx_do_reset(dev, flags);
pci_read_config_byte(dev->pdev, GDRST, &gdrst); break;
pci_write_config_byte(dev->pdev, GDRST, gdrst | flags | ((flags == GDRST_FULL) ? 0x1 : 0x0)); }
udelay(50); dev_priv->last_gpu_reset = get_seconds();
pci_write_config_byte(dev->pdev, GDRST, gdrst & 0xfe); if (ret) {
DRM_ERROR("Failed to reset chip.\n");
/* ...we don't want to loop forever though, 500ms should be plenty */
timeout = jiffies + msecs_to_jiffies(500);
do {
udelay(100);
pci_read_config_byte(dev->pdev, GDRST, &gdrst);
} while ((gdrst & 0x1) && time_after(timeout, jiffies));
if (gdrst & 0x1) {
WARN(true, "i915: Failed to reset chip\n");
mutex_unlock(&dev->struct_mutex);
return -EIO;
}
} else {
DRM_ERROR("Error occurred. Don't know how to reset this chip.\n");
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
return -ENODEV; return ret;
} }
/* Ok, now get things going again... */ /* Ok, now get things going again... */
...@@ -400,13 +478,19 @@ int i965_reset(struct drm_device *dev, u8 flags) ...@@ -400,13 +478,19 @@ int i965_reset(struct drm_device *dev, u8 flags)
mutex_lock(&dev->struct_mutex); mutex_lock(&dev->struct_mutex);
} }
mutex_unlock(&dev->struct_mutex);
/* /*
* Display needs restore too... * Perform a full modeset as on later generations, e.g. Ironlake, we may
* need to retrain the display link and cannot just restore the register
* values.
*/ */
if (need_display) if (need_display) {
i915_restore_display(dev); mutex_lock(&dev->mode_config.mutex);
drm_helper_resume_force_mode(dev);
mutex_unlock(&dev->mode_config.mutex);
}
mutex_unlock(&dev->struct_mutex);
return 0; return 0;
} }
......
drivers/gpu/drm/i915/i915_drv.h
浏览文件 @ 9a170cae
...@@ -34,6 +34,8 @@ ...@@ -34,6 +34,8 @@
#include "intel_bios.h" #include "intel_bios.h"
#include "intel_ringbuffer.h" #include "intel_ringbuffer.h"
#include <linux/io-mapping.h> #include <linux/io-mapping.h>
#include <linux/i2c.h>
#include <drm/intel-gtt.h>
/* General customization: /* General customization:
*/ */
...@@ -73,11 +75,9 @@ enum plane { ...@@ -73,11 +75,9 @@ enum plane {
#define DRIVER_PATCHLEVEL 0 #define DRIVER_PATCHLEVEL 0
#define WATCH_COHERENCY 0 #define WATCH_COHERENCY 0
#define WATCH_BUF 0
#define WATCH_EXEC 0 #define WATCH_EXEC 0
#define WATCH_LRU 0
#define WATCH_RELOC 0 #define WATCH_RELOC 0
#define WATCH_INACTIVE 0 #define WATCH_LISTS 0
#define WATCH_PWRITE 0 #define WATCH_PWRITE 0
#define I915_GEM_PHYS_CURSOR_0 1 #define I915_GEM_PHYS_CURSOR_0 1
...@@ -110,8 +110,9 @@ struct intel_opregion { ...@@ -110,8 +110,9 @@ struct intel_opregion {
struct opregion_acpi *acpi; struct opregion_acpi *acpi;
struct opregion_swsci *swsci; struct opregion_swsci *swsci;
struct opregion_asle *asle; struct opregion_asle *asle;
int enabled; void *vbt;
}; };
#define OPREGION_SIZE (8*1024)
struct intel_overlay; struct intel_overlay;
struct intel_overlay_error_state; struct intel_overlay_error_state;
...@@ -125,13 +126,16 @@ struct drm_i915_master_private { ...@@ -125,13 +126,16 @@ struct drm_i915_master_private {
struct drm_i915_fence_reg { struct drm_i915_fence_reg {
struct drm_gem_object *obj; struct drm_gem_object *obj;
struct list_head lru_list; struct list_head lru_list;
bool gpu;
}; };
struct sdvo_device_mapping { struct sdvo_device_mapping {
u8 initialized;
u8 dvo_port; u8 dvo_port;
u8 slave_addr; u8 slave_addr;
u8 dvo_wiring; u8 dvo_wiring;
u8 initialized; u8 i2c_pin;
u8 i2c_speed;
u8 ddc_pin; u8 ddc_pin;
}; };
...@@ -193,13 +197,9 @@ struct drm_i915_display_funcs { ...@@ -193,13 +197,9 @@ struct drm_i915_display_funcs {
struct intel_device_info { struct intel_device_info {
u8 gen; u8 gen;
u8 is_mobile : 1; u8 is_mobile : 1;
u8 is_i8xx : 1;
u8 is_i85x : 1; u8 is_i85x : 1;
u8 is_i915g : 1; u8 is_i915g : 1;
u8 is_i9xx : 1;
u8 is_i945gm : 1; u8 is_i945gm : 1;
u8 is_i965g : 1;
u8 is_i965gm : 1;
u8 is_g33 : 1; u8 is_g33 : 1;
u8 need_gfx_hws : 1; u8 need_gfx_hws : 1;
u8 is_g4x : 1; u8 is_g4x : 1;
...@@ -212,9 +212,14 @@ struct intel_device_info { ...@@ -212,9 +212,14 @@ struct intel_device_info {
u8 has_pipe_cxsr : 1; u8 has_pipe_cxsr : 1;
u8 has_hotplug : 1; u8 has_hotplug : 1;
u8 cursor_needs_physical : 1; u8 cursor_needs_physical : 1;
u8 has_overlay : 1;
u8 overlay_needs_physical : 1;
u8 supports_tv : 1;
u8 has_bsd_ring : 1;
}; };
enum no_fbc_reason { enum no_fbc_reason {
FBC_NO_OUTPUT, /* no outputs enabled to compress */
FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
FBC_MODE_TOO_LARGE, /* mode too large for compression */ FBC_MODE_TOO_LARGE, /* mode too large for compression */
...@@ -241,6 +246,12 @@ typedef struct drm_i915_private { ...@@ -241,6 +246,12 @@ typedef struct drm_i915_private {
void __iomem *regs; void __iomem *regs;
struct intel_gmbus {
struct i2c_adapter adapter;
struct i2c_adapter *force_bit;
u32 reg0;
} *gmbus;
struct pci_dev *bridge_dev; struct pci_dev *bridge_dev;
struct intel_ring_buffer render_ring; struct intel_ring_buffer render_ring;
struct intel_ring_buffer bsd_ring; struct intel_ring_buffer bsd_ring;
...@@ -263,6 +274,9 @@ typedef struct drm_i915_private { ...@@ -263,6 +274,9 @@ typedef struct drm_i915_private {
int front_offset; int front_offset;
int current_page; int current_page;
int page_flipping; int page_flipping;
#define I915_DEBUG_READ (1<<0)
#define I915_DEBUG_WRITE (1<<1)
unsigned long debug_flags;
wait_queue_head_t irq_queue; wait_queue_head_t irq_queue;
atomic_t irq_received; atomic_t irq_received;
...@@ -289,24 +303,21 @@ typedef struct drm_i915_private { ...@@ -289,24 +303,21 @@ typedef struct drm_i915_private {
unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
int vblank_pipe; int vblank_pipe;
int num_pipe; int num_pipe;
u32 flush_rings;
#define FLUSH_RENDER_RING 0x1
#define FLUSH_BSD_RING 0x2
/* For hangcheck timer */ /* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
struct timer_list hangcheck_timer; struct timer_list hangcheck_timer;
int hangcheck_count; int hangcheck_count;
uint32_t last_acthd; uint32_t last_acthd;
uint32_t last_instdone; uint32_t last_instdone;
uint32_t last_instdone1; uint32_t last_instdone1;
struct drm_mm vram;
unsigned long cfb_size; unsigned long cfb_size;
unsigned long cfb_pitch; unsigned long cfb_pitch;
unsigned long cfb_offset;
int cfb_fence; int cfb_fence;
int cfb_plane; int cfb_plane;
int cfb_y;
int irq_enabled; int irq_enabled;
...@@ -316,8 +327,7 @@ typedef struct drm_i915_private { ...@@ -316,8 +327,7 @@ typedef struct drm_i915_private {
struct intel_overlay *overlay; struct intel_overlay *overlay;
/* LVDS info */ /* LVDS info */
int backlight_duty_cycle; /* restore backlight to this value */ int backlight_level; /* restore backlight to this value */
bool panel_wants_dither;
struct drm_display_mode *panel_fixed_mode; struct drm_display_mode *panel_fixed_mode;
struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
...@@ -328,13 +338,22 @@ typedef struct drm_i915_private { ...@@ -328,13 +338,22 @@ typedef struct drm_i915_private {
unsigned int lvds_vbt:1; unsigned int lvds_vbt:1;
unsigned int int_crt_support:1; unsigned int int_crt_support:1;
unsigned int lvds_use_ssc:1; unsigned int lvds_use_ssc:1;
unsigned int edp_support:1;
int lvds_ssc_freq; int lvds_ssc_freq;
int edp_bpp;
struct {
u8 rate:4;
u8 lanes:4;
u8 preemphasis:4;
u8 vswing:4;
u8 initialized:1;
u8 support:1;
u8 bpp:6;
} edp;
struct notifier_block lid_notifier; struct notifier_block lid_notifier;
int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */ int crt_ddc_pin;
struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
int num_fence_regs; /* 8 on pre-965, 16 otherwise */ int num_fence_regs; /* 8 on pre-965, 16 otherwise */
...@@ -344,6 +363,7 @@ typedef struct drm_i915_private { ...@@ -344,6 +363,7 @@ typedef struct drm_i915_private {
spinlock_t error_lock; spinlock_t error_lock;
struct drm_i915_error_state *first_error; struct drm_i915_error_state *first_error;
struct work_struct error_work; struct work_struct error_work;
struct completion error_completion;
struct workqueue_struct *wq; struct workqueue_struct *wq;
/* Display functions */ /* Display functions */
...@@ -507,6 +527,11 @@ typedef struct drm_i915_private { ...@@ -507,6 +527,11 @@ typedef struct drm_i915_private {
u32 saveMCHBAR_RENDER_STANDBY; u32 saveMCHBAR_RENDER_STANDBY;
struct { struct {
/** Bridge to intel-gtt-ko */
struct intel_gtt *gtt;
/** Memory allocator for GTT stolen memory */
struct drm_mm vram;
/** Memory allocator for GTT */
struct drm_mm gtt_space; struct drm_mm gtt_space;
struct io_mapping *gtt_mapping; struct io_mapping *gtt_mapping;
...@@ -521,8 +546,6 @@ typedef struct drm_i915_private { ...@@ -521,8 +546,6 @@ typedef struct drm_i915_private {
*/ */
struct list_head shrink_list; struct list_head shrink_list;
spinlock_t active_list_lock;
/** /**
* List of objects which are not in the ringbuffer but which * List of objects which are not in the ringbuffer but which
* still have a write_domain which needs to be flushed before * still have a write_domain which needs to be flushed before
...@@ -555,6 +578,12 @@ typedef struct drm_i915_private { ...@@ -555,6 +578,12 @@ typedef struct drm_i915_private {
*/ */
struct list_head inactive_list; struct list_head inactive_list;
/**
* LRU list of objects which are not in the ringbuffer but
* are still pinned in the GTT.
*/
struct list_head pinned_list;
/** LRU list of objects with fence regs on them. */ /** LRU list of objects with fence regs on them. */
struct list_head fence_list; struct list_head fence_list;
...@@ -611,6 +640,17 @@ typedef struct drm_i915_private { ...@@ -611,6 +640,17 @@ typedef struct drm_i915_private {
/* storage for physical objects */ /* storage for physical objects */
struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
uint32_t flush_rings;
/* accounting, useful for userland debugging */
size_t object_memory;
size_t pin_memory;
size_t gtt_memory;
size_t gtt_total;
u32 object_count;
u32 pin_count;
u32 gtt_count;
} mm; } mm;
struct sdvo_device_mapping sdvo_mappings[2]; struct sdvo_device_mapping sdvo_mappings[2];
/* indicate whether the LVDS_BORDER should be enabled or not */ /* indicate whether the LVDS_BORDER should be enabled or not */
...@@ -626,8 +666,6 @@ typedef struct drm_i915_private { ...@@ -626,8 +666,6 @@ typedef struct drm_i915_private {
/* Reclocking support */ /* Reclocking support */
bool render_reclock_avail; bool render_reclock_avail;
bool lvds_downclock_avail; bool lvds_downclock_avail;
/* indicate whether the LVDS EDID is OK */
bool lvds_edid_good;
/* indicates the reduced downclock for LVDS*/ /* indicates the reduced downclock for LVDS*/
int lvds_downclock; int lvds_downclock;
struct work_struct idle_work; struct work_struct idle_work;
...@@ -661,6 +699,8 @@ typedef struct drm_i915_private { ...@@ -661,6 +699,8 @@ typedef struct drm_i915_private {
struct drm_mm_node *compressed_fb; struct drm_mm_node *compressed_fb;
struct drm_mm_node *compressed_llb; struct drm_mm_node *compressed_llb;
unsigned long last_gpu_reset;
/* list of fbdev register on this device */ /* list of fbdev register on this device */
struct intel_fbdev *fbdev; struct intel_fbdev *fbdev;
} drm_i915_private_t; } drm_i915_private_t;
...@@ -816,12 +856,14 @@ struct drm_i915_gem_request { ...@@ -816,12 +856,14 @@ struct drm_i915_gem_request {
/** global list entry for this request */ /** global list entry for this request */
struct list_head list; struct list_head list;
struct drm_i915_file_private *file_priv;
/** file_priv list entry for this request */ /** file_priv list entry for this request */
struct list_head client_list; struct list_head client_list;
}; };
struct drm_i915_file_private { struct drm_i915_file_private {
struct { struct {
struct spinlock lock;
struct list_head request_list; struct list_head request_list;
} mm; } mm;
}; };
...@@ -862,7 +904,7 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, ...@@ -862,7 +904,7 @@ extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
extern int i915_emit_box(struct drm_device *dev, extern int i915_emit_box(struct drm_device *dev,
struct drm_clip_rect *boxes, struct drm_clip_rect *boxes,
int i, int DR1, int DR4); int i, int DR1, int DR4);
extern int i965_reset(struct drm_device *dev, u8 flags); extern int i915_reset(struct drm_device *dev, u8 flags);
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
...@@ -871,7 +913,6 @@ extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); ...@@ -871,7 +913,6 @@ extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
/* i915_irq.c */ /* i915_irq.c */
void i915_hangcheck_elapsed(unsigned long data); void i915_hangcheck_elapsed(unsigned long data);
void i915_destroy_error_state(struct drm_device *dev);
extern int i915_irq_emit(struct drm_device *dev, void *data, extern int i915_irq_emit(struct drm_device *dev, void *data,
struct drm_file *file_priv); struct drm_file *file_priv);
extern int i915_irq_wait(struct drm_device *dev, void *data, extern int i915_irq_wait(struct drm_device *dev, void *data,
...@@ -908,6 +949,12 @@ i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); ...@@ -908,6 +949,12 @@ i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
void intel_enable_asle (struct drm_device *dev); void intel_enable_asle (struct drm_device *dev);
#ifdef CONFIG_DEBUG_FS
extern void i915_destroy_error_state(struct drm_device *dev);
#else
#define i915_destroy_error_state(x)
#endif
/* i915_mem.c */ /* i915_mem.c */
extern int i915_mem_alloc(struct drm_device *dev, void *data, extern int i915_mem_alloc(struct drm_device *dev, void *data,
...@@ -922,6 +969,7 @@ extern void i915_mem_takedown(struct mem_block **heap); ...@@ -922,6 +969,7 @@ extern void i915_mem_takedown(struct mem_block **heap);
extern void i915_mem_release(struct drm_device * dev, extern void i915_mem_release(struct drm_device * dev,
struct drm_file *file_priv, struct mem_block *heap); struct drm_file *file_priv, struct mem_block *heap);
/* i915_gem.c */ /* i915_gem.c */
int i915_gem_check_is_wedged(struct drm_device *dev);
int i915_gem_init_ioctl(struct drm_device *dev, void *data, int i915_gem_init_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv); struct drm_file *file_priv);
int i915_gem_create_ioctl(struct drm_device *dev, void *data, int i915_gem_create_ioctl(struct drm_device *dev, void *data,
...@@ -972,13 +1020,22 @@ void i915_gem_object_unpin(struct drm_gem_object *obj); ...@@ -972,13 +1020,22 @@ void i915_gem_object_unpin(struct drm_gem_object *obj);
int i915_gem_object_unbind(struct drm_gem_object *obj); int i915_gem_object_unbind(struct drm_gem_object *obj);
void i915_gem_release_mmap(struct drm_gem_object *obj); void i915_gem_release_mmap(struct drm_gem_object *obj);
void i915_gem_lastclose(struct drm_device *dev); void i915_gem_lastclose(struct drm_device *dev);
uint32_t i915_get_gem_seqno(struct drm_device *dev,
struct intel_ring_buffer *ring); /**
bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); * Returns true if seq1 is later than seq2.
int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); */
int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); static inline bool
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
{
return (int32_t)(seq1 - seq2) >= 0;
}
int i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
bool interruptible);
int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
bool interruptible);
void i915_gem_retire_requests(struct drm_device *dev); void i915_gem_retire_requests(struct drm_device *dev);
void i915_gem_retire_work_handler(struct work_struct *work); void i915_gem_reset(struct drm_device *dev);
void i915_gem_clflush_object(struct drm_gem_object *obj); void i915_gem_clflush_object(struct drm_gem_object *obj);
int i915_gem_object_set_domain(struct drm_gem_object *obj, int i915_gem_object_set_domain(struct drm_gem_object *obj,
uint32_t read_domains, uint32_t read_domains,
...@@ -990,16 +1047,18 @@ int i915_gem_do_init(struct drm_device *dev, unsigned long start, ...@@ -990,16 +1047,18 @@ int i915_gem_do_init(struct drm_device *dev, unsigned long start,
int i915_gpu_idle(struct drm_device *dev); int i915_gpu_idle(struct drm_device *dev);
int i915_gem_idle(struct drm_device *dev); int i915_gem_idle(struct drm_device *dev);
uint32_t i915_add_request(struct drm_device *dev, uint32_t i915_add_request(struct drm_device *dev,
struct drm_file *file_priv, struct drm_file *file_priv,
uint32_t flush_domains, struct drm_i915_gem_request *request,
struct intel_ring_buffer *ring); struct intel_ring_buffer *ring);
int i915_do_wait_request(struct drm_device *dev, int i915_do_wait_request(struct drm_device *dev,
uint32_t seqno, int interruptible, uint32_t seqno,
struct intel_ring_buffer *ring); bool interruptible,
struct intel_ring_buffer *ring);
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
int write); int write);
int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
bool pipelined);
int i915_gem_attach_phys_object(struct drm_device *dev, int i915_gem_attach_phys_object(struct drm_device *dev,
struct drm_gem_object *obj, struct drm_gem_object *obj,
int id, int id,
...@@ -1007,10 +1066,7 @@ int i915_gem_attach_phys_object(struct drm_device *dev, ...@@ -1007,10 +1066,7 @@ int i915_gem_attach_phys_object(struct drm_device *dev,
void i915_gem_detach_phys_object(struct drm_device *dev, void i915_gem_detach_phys_object(struct drm_device *dev,
struct drm_gem_object *obj); struct drm_gem_object *obj);
void i915_gem_free_all_phys_object(struct drm_device *dev); void i915_gem_free_all_phys_object(struct drm_device *dev);
int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
void i915_gem_object_put_pages(struct drm_gem_object *obj);
void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
int i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
void i915_gem_shrinker_init(void); void i915_gem_shrinker_init(void);
void i915_gem_shrinker_exit(void); void i915_gem_shrinker_exit(void);
...@@ -1032,15 +1088,14 @@ bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, ...@@ -1032,15 +1088,14 @@ bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
/* i915_gem_debug.c */ /* i915_gem_debug.c */
void i915_gem_dump_object(struct drm_gem_object *obj, int len, void i915_gem_dump_object(struct drm_gem_object *obj, int len,
const char *where, uint32_t mark); const char *where, uint32_t mark);
#if WATCH_INACTIVE #if WATCH_LISTS
void i915_verify_inactive(struct drm_device *dev, char *file, int line); int i915_verify_lists(struct drm_device *dev);
#else #else
#define i915_verify_inactive(dev, file, line) #define i915_verify_lists(dev) 0
#endif #endif
void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
void i915_gem_dump_object(struct drm_gem_object *obj, int len, void i915_gem_dump_object(struct drm_gem_object *obj, int len,
const char *where, uint32_t mark); const char *where, uint32_t mark);
void i915_dump_lru(struct drm_device *dev, const char *where);
/* i915_debugfs.c */ /* i915_debugfs.c */
int i915_debugfs_init(struct drm_minor *minor); int i915_debugfs_init(struct drm_minor *minor);
...@@ -1054,19 +1109,31 @@ extern int i915_restore_state(struct drm_device *dev); ...@@ -1054,19 +1109,31 @@ extern int i915_restore_state(struct drm_device *dev);
extern int i915_save_state(struct drm_device *dev); extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev); extern int i915_restore_state(struct drm_device *dev);
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
{
return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
extern void intel_i2c_reset(struct drm_device *dev);
/* intel_opregion.c */
extern int intel_opregion_setup(struct drm_device *dev);
#ifdef CONFIG_ACPI #ifdef CONFIG_ACPI
/* i915_opregion.c */ extern void intel_opregion_init(struct drm_device *dev);
extern int intel_opregion_init(struct drm_device *dev, int resume); extern void intel_opregion_fini(struct drm_device *dev);
extern void intel_opregion_free(struct drm_device *dev, int suspend); extern void intel_opregion_asle_intr(struct drm_device *dev);
extern void opregion_asle_intr(struct drm_device *dev); extern void intel_opregion_gse_intr(struct drm_device *dev);
extern void ironlake_opregion_gse_intr(struct drm_device *dev); extern void intel_opregion_enable_asle(struct drm_device *dev);
extern void opregion_enable_asle(struct drm_device *dev);
#else #else
static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } static inline void intel_opregion_init(struct drm_device *dev) { return; }
static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } static inline void intel_opregion_fini(struct drm_device *dev) { return; }
static inline void opregion_asle_intr(struct drm_device *dev) { return; } static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; } static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
static inline void opregion_enable_asle(struct drm_device *dev) { return; } static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
#endif #endif
/* modesetting */ /* modesetting */
...@@ -1084,8 +1151,10 @@ extern void intel_detect_pch (struct drm_device *dev); ...@@ -1084,8 +1151,10 @@ extern void intel_detect_pch (struct drm_device *dev);
extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
/* overlay */ /* overlay */
#ifdef CONFIG_DEBUG_FS
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
#endif
/** /**
* Lock test for when it's just for synchronization of ring access. * Lock test for when it's just for synchronization of ring access.
...@@ -1099,8 +1168,26 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove ...@@ -1099,8 +1168,26 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
LOCK_TEST_WITH_RETURN(dev, file_priv); \ LOCK_TEST_WITH_RETURN(dev, file_priv); \
} while (0) } while (0)
#define I915_READ(reg) readl(dev_priv->regs + (reg)) static inline u32 i915_read(struct drm_i915_private *dev_priv, u32 reg)
#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) {
u32 val;
val = readl(dev_priv->regs + reg);
if (dev_priv->debug_flags & I915_DEBUG_READ)
printk(KERN_ERR "read 0x%08x from 0x%08x\n", val, reg);
return val;
}
static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
u32 val)
{
writel(val, dev_priv->regs + reg);
if (dev_priv->debug_flags & I915_DEBUG_WRITE)
printk(KERN_ERR "wrote 0x%08x to 0x%08x\n", val, reg);
}
#define I915_READ(reg) i915_read(dev_priv, (reg))
#define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val))
#define I915_READ16(reg) readw(dev_priv->regs + (reg)) #define I915_READ16(reg) readw(dev_priv->regs + (reg))
#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
#define I915_READ8(reg) readb(dev_priv->regs + (reg)) #define I915_READ8(reg) readb(dev_priv->regs + (reg))
...@@ -1110,6 +1197,11 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove ...@@ -1110,6 +1197,11 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
#define POSTING_READ(reg) (void)I915_READ(reg) #define POSTING_READ(reg) (void)I915_READ(reg)
#define POSTING_READ16(reg) (void)I915_READ16(reg) #define POSTING_READ16(reg) (void)I915_READ16(reg)
#define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
I915_DEBUG_WRITE)
#define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
I915_DEBUG_WRITE))
#define I915_VERBOSE 0 #define I915_VERBOSE 0
#define BEGIN_LP_RING(n) do { \ #define BEGIN_LP_RING(n) do { \
...@@ -1166,8 +1258,6 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove ...@@ -1166,8 +1258,6 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
#define IS_I945G(dev) ((dev)->pci_device == 0x2772) #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
#define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
#define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
#define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
#define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
...@@ -1179,7 +1269,6 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove ...@@ -1179,7 +1269,6 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
#define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
#define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
...@@ -1188,26 +1277,27 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove ...@@ -1188,26 +1277,27 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
#define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev)) #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming. * rows, which changed the alignment requirements and fence programming.
*/ */
#define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
IS_I915GM(dev))) IS_I915GM(dev)))
#define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev)) #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
#define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
#define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
#define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
#define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
!IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
!IS_GEN6(dev))
#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
/* dsparb controlled by hw only */ /* dsparb controlled by hw only */
#define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
#define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
......
drivers/gpu/drm/i915/i915_gem.c
浏览文件 @ 9a170cae
此差异已折叠。
drivers/gpu/drm/i915/i915_gem_debug.c
浏览文件 @ 9a170cae
...@@ -30,29 +30,112 @@ ...@@ -30,29 +30,112 @@
#include "i915_drm.h" #include "i915_drm.h"
#include "i915_drv.h" #include "i915_drv.h"
#if WATCH_INACTIVE #if WATCH_LISTS
void int
i915_verify_inactive(struct drm_device *dev, char *file, int line) i915_verify_lists(struct drm_device *dev)
{ {
static int warned;
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
struct drm_gem_object *obj; struct drm_i915_gem_object *obj;
struct drm_i915_gem_object *obj_priv; int err = 0;
list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { if (warned)
obj = &obj_priv->base; return 0;
if (obj_priv->pin_count || obj_priv->active ||
(obj->write_domain & ~(I915_GEM_DOMAIN_CPU | list_for_each_entry(obj, &dev_priv->render_ring.active_list, list) {
I915_GEM_DOMAIN_GTT))) if (obj->base.dev != dev ||
DRM_ERROR("inactive %p (p %d a %d w %x) %s:%d\n", !atomic_read(&obj->base.refcount.refcount)) {
DRM_ERROR("freed render active %p\n", obj);
err++;
break;
} else if (!obj->active ||
(obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) {
DRM_ERROR("invalid render active %p (a %d r %x)\n",
obj,
obj->active,
obj->base.read_domains);
err++;
} else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) {
DRM_ERROR("invalid render active %p (w %x, gwl %d)\n",
obj,
obj->base.write_domain,
!list_empty(&obj->gpu_write_list));
err++;
}
}
list_for_each_entry(obj, &dev_priv->mm.flushing_list, list) {
if (obj->base.dev != dev ||
!atomic_read(&obj->base.refcount.refcount)) {
DRM_ERROR("freed flushing %p\n", obj);
err++;
break;
} else if (!obj->active ||
(obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 ||
list_empty(&obj->gpu_write_list)){
DRM_ERROR("invalid flushing %p (a %d w %x gwl %d)\n",
obj, obj,
obj_priv->pin_count, obj_priv->active, obj->active,
obj->write_domain, file, line); obj->base.write_domain,
!list_empty(&obj->gpu_write_list));
err++;
}
}
list_for_each_entry(obj, &dev_priv->mm.gpu_write_list, gpu_write_list) {
if (obj->base.dev != dev ||
!atomic_read(&obj->base.refcount.refcount)) {
DRM_ERROR("freed gpu write %p\n", obj);
err++;
break;
} else if (!obj->active ||
(obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) {
DRM_ERROR("invalid gpu write %p (a %d w %x)\n",
obj,
obj->active,
obj->base.write_domain);
err++;
}
}
list_for_each_entry(obj, &dev_priv->mm.inactive_list, list) {
if (obj->base.dev != dev ||
!atomic_read(&obj->base.refcount.refcount)) {
DRM_ERROR("freed inactive %p\n", obj);
err++;
break;
} else if (obj->pin_count || obj->active ||
(obj->base.write_domain & I915_GEM_GPU_DOMAINS)) {
DRM_ERROR("invalid inactive %p (p %d a %d w %x)\n",
obj,
obj->pin_count, obj->active,
obj->base.write_domain);
err++;
}
} }
list_for_each_entry(obj, &dev_priv->mm.pinned_list, list) {
if (obj->base.dev != dev ||
!atomic_read(&obj->base.refcount.refcount)) {
DRM_ERROR("freed pinned %p\n", obj);
err++;
break;
} else if (!obj->pin_count || obj->active ||
(obj->base.write_domain & I915_GEM_GPU_DOMAINS)) {
DRM_ERROR("invalid pinned %p (p %d a %d w %x)\n",
obj,
obj->pin_count, obj->active,
obj->base.write_domain);
err++;
}
}
return warned = err;
} }
#endif /* WATCH_INACTIVE */ #endif /* WATCH_INACTIVE */
#if WATCH_BUF | WATCH_EXEC | WATCH_PWRITE #if WATCH_EXEC | WATCH_PWRITE
static void static void
i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end, i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end,
uint32_t bias, uint32_t mark) uint32_t bias, uint32_t mark)
...@@ -97,41 +180,6 @@ i915_gem_dump_object(struct drm_gem_object *obj, int len, ...@@ -97,41 +180,6 @@ i915_gem_dump_object(struct drm_gem_object *obj, int len,
} }
#endif #endif
#if WATCH_LRU
void
i915_dump_lru(struct drm_device *dev, const char *where)
{
drm_i915_private_t *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj_priv;
DRM_INFO("active list %s {\n", where);
spin_lock(&dev_priv->mm.active_list_lock);
list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
list)
{
DRM_INFO(" %p: %08x\n", obj_priv,
obj_priv->last_rendering_seqno);
}
spin_unlock(&dev_priv->mm.active_list_lock);
DRM_INFO("}\n");
DRM_INFO("flushing list %s {\n", where);
list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
list)
{
DRM_INFO(" %p: %08x\n", obj_priv,
obj_priv->last_rendering_seqno);
}
DRM_INFO("}\n");
DRM_INFO("inactive %s {\n", where);
list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
DRM_INFO(" %p: %08x\n", obj_priv,
obj_priv->last_rendering_seqno);
}
DRM_INFO("}\n");
}
#endif
#if WATCH_COHERENCY #if WATCH_COHERENCY
void void
i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle) i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
......
drivers/gpu/drm/i915/i915_gem_evict.c
浏览文件 @ 9a170cae
...@@ -93,7 +93,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignmen ...@@ -93,7 +93,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignmen
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
struct list_head eviction_list, unwind_list; struct list_head eviction_list, unwind_list;
struct drm_i915_gem_object *obj_priv, *tmp_obj_priv; struct drm_i915_gem_object *obj_priv;
struct list_head *render_iter, *bsd_iter; struct list_head *render_iter, *bsd_iter;
int ret = 0; int ret = 0;
...@@ -175,39 +175,34 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignmen ...@@ -175,39 +175,34 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, unsigned alignmen
return -ENOSPC; return -ENOSPC;
found: found:
/* drm_mm doesn't allow any other other operations while
* scanning, therefore store to be evicted objects on a
* temporary list. */
INIT_LIST_HEAD(&eviction_list); INIT_LIST_HEAD(&eviction_list);
list_for_each_entry_safe(obj_priv, tmp_obj_priv, while (!list_empty(&unwind_list)) {
&unwind_list, evict_list) { obj_priv = list_first_entry(&unwind_list,
struct drm_i915_gem_object,
evict_list);
if (drm_mm_scan_remove_block(obj_priv->gtt_space)) { if (drm_mm_scan_remove_block(obj_priv->gtt_space)) {
/* drm_mm doesn't allow any other other operations while
* scanning, therefore store to be evicted objects on a
* temporary list. */
list_move(&obj_priv->evict_list, &eviction_list); list_move(&obj_priv->evict_list, &eviction_list);
} else continue;
drm_gem_object_unreference(&obj_priv->base); }
list_del(&obj_priv->evict_list);
drm_gem_object_unreference(&obj_priv->base);
} }
/* Unbinding will emit any required flushes */ /* Unbinding will emit any required flushes */
list_for_each_entry_safe(obj_priv, tmp_obj_priv, while (!list_empty(&eviction_list)) {
&eviction_list, evict_list) { obj_priv = list_first_entry(&eviction_list,
#if WATCH_LRU struct drm_i915_gem_object,
DRM_INFO("%s: evicting %p\n", __func__, &obj_priv->base); evict_list);
#endif if (ret == 0)
ret = i915_gem_object_unbind(&obj_priv->base); ret = i915_gem_object_unbind(&obj_priv->base);
if (ret) list_del(&obj_priv->evict_list);
return ret;
drm_gem_object_unreference(&obj_priv->base); drm_gem_object_unreference(&obj_priv->base);
} }
/* The just created free hole should be on the top of the free stack return ret;
* maintained by drm_mm, so this BUG_ON actually executes in O(1).
* Furthermore all accessed data has just recently been used, so it
* should be really fast, too. */
BUG_ON(!drm_mm_search_free(&dev_priv->mm.gtt_space, min_size,
alignment, 0));
return 0;
} }
int int
...@@ -217,14 +212,11 @@ i915_gem_evict_everything(struct drm_device *dev) ...@@ -217,14 +212,11 @@ i915_gem_evict_everything(struct drm_device *dev)
int ret; int ret;
bool lists_empty; bool lists_empty;
spin_lock(&dev_priv->mm.active_list_lock);
lists_empty = (list_empty(&dev_priv->mm.inactive_list) && lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
list_empty(&dev_priv->mm.flushing_list) && list_empty(&dev_priv->mm.flushing_list) &&
list_empty(&dev_priv->render_ring.active_list) && list_empty(&dev_priv->render_ring.active_list) &&
(!HAS_BSD(dev) (!HAS_BSD(dev)
|| list_empty(&dev_priv->bsd_ring.active_list))); || list_empty(&dev_priv->bsd_ring.active_list)));
spin_unlock(&dev_priv->mm.active_list_lock);
if (lists_empty) if (lists_empty)
return -ENOSPC; return -ENOSPC;
...@@ -239,13 +231,11 @@ i915_gem_evict_everything(struct drm_device *dev) ...@@ -239,13 +231,11 @@ i915_gem_evict_everything(struct drm_device *dev)
if (ret) if (ret)
return ret; return ret;
spin_lock(&dev_priv->mm.active_list_lock);
lists_empty = (list_empty(&dev_priv->mm.inactive_list) && lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
list_empty(&dev_priv->mm.flushing_list) && list_empty(&dev_priv->mm.flushing_list) &&
list_empty(&dev_priv->render_ring.active_list) && list_empty(&dev_priv->render_ring.active_list) &&
(!HAS_BSD(dev) (!HAS_BSD(dev)
|| list_empty(&dev_priv->bsd_ring.active_list))); || list_empty(&dev_priv->bsd_ring.active_list)));
spin_unlock(&dev_priv->mm.active_list_lock);
BUG_ON(!lists_empty); BUG_ON(!lists_empty);
return 0; return 0;
......
drivers/gpu/drm/i915/i915_irq.c
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drivers/gpu/drm/i915/i915_reg.h
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drivers/gpu/drm/i915/i915_suspend.c
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drivers/gpu/drm/i915/intel_bios.c
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drivers/gpu/drm/i915/intel_bios.h
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drivers/gpu/drm/i915/intel_crt.c
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drivers/gpu/drm/i915/intel_dp.c
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drivers/gpu/drm/i915/intel_drv.h
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drivers/gpu/drm/i915/intel_dvo.c
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drivers/gpu/drm/i915/intel_fb.c
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drivers/gpu/drm/i915/intel_hdmi.c
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drivers/gpu/drm/i915/intel_i2c.c
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drivers/gpu/drm/i915/intel_lvds.c
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drivers/gpu/drm/i915/intel_modes.c
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drivers/gpu/drm/i915/intel_panel.c
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drivers/gpu/drm/i915/intel_sdvo.c
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drivers/gpu/drm/i915/intel_tv.c
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include/drm/drmP.h
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include/drm/intel-gtt.h 0 → 100644
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此差异已折叠。
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