提交 97303480 编写于 作者: T Tirumalesh Chalamarla 提交者: Catalin Marinas

arm64: Increase the max granular size

Increase the standard cacheline size to avoid having locks in the same
cacheline.

Cavium's ThunderX core implements cache lines of 128 byte size. With
current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could
share the same cache line leading a performance degradation.
Increasing the size fixes that.

Increasing the size has no negative impact to cache invalidation on
systems with a smaller cache line. There is an impact on memory usage,
but that's not too important for arm64 use cases.
Signed-off-by: NTirumalesh Chalamarla <tchalamarla@cavium.com>
Signed-off-by: NRobert Richter <rrichter@cavium.com>
Acked-by: NTimur Tabi <timur@codeaurora.org>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
上级 6e4a0f2b
......@@ -18,7 +18,7 @@
#include <asm/cachetype.h>
#define L1_CACHE_SHIFT 6
#define L1_CACHE_SHIFT 7
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*
......
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