提交 9512c6fe 编写于 作者: T Tomi Valkeinen

ARM: dts: fix omap3 dss clock handle names

The DSS fclk and iclk handles are named differently on OMAP3430 ES1 than
on later OMAP revisions. The ES1 has handles 'dss1_alwon_fck_3430es1'
and 'dss_ick_3430es1', whereas later revisions have similar names but
ending with 'es2'.

This means we don't have one clock handle to which we could refer to
when defining the DSS clocks.

However, as the namespaces are separate for ES1 and ES2+ OMAPs, we can
just rename the handles to 'dss1_alwon_fck' and 'dss_ick' for both ES1
and ES2+, removing the issue.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: NChristoph Fritz <chf.fritz@googlemail.com>
Tested-by: NMarek Belisko <marek@goldelico.com>
Acked-by: NTero Kristo <t-kristo@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
上级 e1902bbe
......@@ -152,7 +152,7 @@
clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
};
dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
dss1_alwon_fck: dss1_alwon_fck_3430es1 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll4_m4x2_ck>;
......@@ -161,7 +161,7 @@
ti,set-rate-parent;
};
dss_ick_3430es1: dss_ick_3430es1 {
dss_ick: dss_ick_3430es1 {
#clock-cells = <0>;
compatible = "ti,omap3-no-wait-interface-clock";
clocks = <&l4_ick>;
......@@ -184,7 +184,7 @@
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
<&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
<&dss1_alwon_fck>, <&dss_ick>;
};
d2d_clkdm: d2d_clkdm {
......
......@@ -160,7 +160,7 @@
ti,bit-shift = <30>;
};
dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
dss1_alwon_fck: dss1_alwon_fck_3430es2 {
#clock-cells = <0>;
compatible = "ti,dss-gate-clock";
clocks = <&dpll4_m4x2_ck>;
......@@ -169,7 +169,7 @@
ti,set-rate-parent;
};
dss_ick_3430es2: dss_ick_3430es2 {
dss_ick: dss_ick_3430es2 {
#clock-cells = <0>;
compatible = "ti,omap3-dss-interface-clock";
clocks = <&l4_ick>;
......@@ -216,7 +216,7 @@
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
<&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
<&dss1_alwon_fck>, <&dss_ick>;
};
core_l4_clkdm: core_l4_clkdm {
......
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