提交 8e504bcc 编写于 作者: Y Yongqiang Sun 提交者: Alex Deucher

drm/amd/display: Disable plane right after disconnected

HDR display playing video underflow is observed when switching
to full screen due to program a lower watermark right after unlock otg.

Instead of disable plane in next flip coming, if there is a
plane disconnected, after otg unlock wait for mpcc idle and disable
the plane, then program watermark. So there is enough warter mark to make
sure current frame data pass through.
Signed-off-by: NYongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: NTony Cheng <Tony.Cheng@amd.com>
Acked-by: NHarry Wentland <harry.wentland@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 9168a586
...@@ -2297,7 +2297,7 @@ static void dcn10_apply_ctx_for_surface( ...@@ -2297,7 +2297,7 @@ static void dcn10_apply_ctx_for_surface(
pipe_ctx->plane_state->update_flags.bits.full_update) pipe_ctx->plane_state->update_flags.bits.full_update)
program_water_mark = true; program_water_mark = true;
if (removed_pipe[i] && num_planes == 0) if (removed_pipe[i])
dcn10_disable_plane(dc, old_pipe_ctx); dcn10_disable_plane(dc, old_pipe_ctx);
} }
...@@ -2306,6 +2306,7 @@ static void dcn10_apply_ctx_for_surface( ...@@ -2306,6 +2306,7 @@ static void dcn10_apply_ctx_for_surface(
/* pstate stuck check after watermark update */ /* pstate stuck check after watermark update */
dcn10_verify_allow_pstate_change_high(dc); dcn10_verify_allow_pstate_change_high(dc);
} }
/* watermark is for all pipes */ /* watermark is for all pipes */
hubbub1_program_watermarks(dc->res_pool->hubbub, hubbub1_program_watermarks(dc->res_pool->hubbub,
&context->bw.dcn.watermarks, ref_clk_mhz); &context->bw.dcn.watermarks, ref_clk_mhz);
......
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