mmc: msm_sdcc: Wrap readl/writel calls with appropriate clk delays
As it turns out, all sdcc register writes must be delayed by at least 3 core clock cycles for the writes to take effect. *sigh* Also removes the 30us constant delay on clock enable in favor of a 3 core clock delay. Signed-off-by: NSan Mehat <san@google.com> Signed-off-by: NDaniel Walker <dwalker@codeaurora.org>
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