提交 8abef06b 编写于 作者: M Michal Simek

ARM: zynq: DT: Add missing address for L2 pl310

By in sync with others node and add also baseaddr
to the node name.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
上级 e8b39775
......@@ -136,7 +136,7 @@
<0xF8F00100 0x100>;
};
L2: cache-controller {
L2: cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
arm,data-latency = <3 2 2>;
......
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