ARM: OMAP4460/4470: PMU: Enable PMU for OMAP4460/70

OMAP4460 and OMAP4470 devices have dedicated PMU interrupts and so add these
interrupts to the MPU HWMOD so we can use these for PMU events on these
devices. The PMU interrupts need to be the first interrupts in the array of
interrupts as the ARM PMU driver assumes this.

By using these dedicated interrupts we only need to enable the MPU and DEBUG
sub-systems for PMU to work. This is different to OMAP4430 that did not have
dedicated interrupts and required other power domains in addition to the DEBUG
sub-system to be enabled so we could route the PMU events to the CTI interrupts.
Hence, OMAP4460 and OMAP4470 devices can use the same list of HWMODs to create
the PMU device that is using by OMAP3.

Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

@@ -2223,7 +2223,7 @@ static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
 	.master		= &omap3xxx_l3_main_hwmod,
 	.slave		= &omap3xxx_debugss_hwmod,
-	.addr		= &omap3xxx_l4_emu_hwmod,
+	.addr		= omap3xxx_l4_emu_addrs,
 	.user		= OCP_USER_MPU,
 };
 

arch/arm/mach-omap2/omap_hwmod_44xx_data.c

@@ -2615,6 +2615,8 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 
 /* mpu */
 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
+	{ .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
+	{ .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
 	{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
 	{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
 	{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },

arch/arm/mach-omap2/pmu.c

@@ -30,7 +30,7 @@ static struct platform_device *omap_pmu_dev;
  *
  * Uses OMAP HWMOD framework to create and register an ARM PMU device
  * from a list of HWMOD names passed. Currently supports OMAP2, OMAP3
- * and OMAP4430 devices.
+ * and OMAP4 devices.
  */
 static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
 {
@@ -74,21 +74,20 @@ static int __init omap_init_pmu(void)
 	 * OMAP24xx:	mpu
 	 * OMAP3xxx:	mpu, debugss
 	 * OMAP4430:	l3_main_3, l3_instr, debugss
+	 * OMAP4460/70:	mpu, debugss
 	 */
-	if (cpu_is_omap24xx()) {
-		oh_num = ARRAY_SIZE(omap2_pmu_oh_names);
-		oh_names = omap2_pmu_oh_names;
-	} else if (cpu_is_omap34xx()) {
-		oh_num = ARRAY_SIZE(omap3_pmu_oh_names);
-		oh_names = omap3_pmu_oh_names;
-	} else if (cpu_is_omap443x()) {
+	if (cpu_is_omap443x()) {
 		oh_num = ARRAY_SIZE(omap4430_pmu_oh_names);
 		oh_names = omap4430_pmu_oh_names;
 		/* XXX Remove the next two lines when CTI driver available */
 		pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n");
 		return 0;
+	} else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+		oh_num = ARRAY_SIZE(omap3_pmu_oh_names);
+		oh_names = omap3_pmu_oh_names;
 	} else {
-		return 0;
+		oh_num = ARRAY_SIZE(omap2_pmu_oh_names);
+		oh_names = omap2_pmu_oh_names;
 	}
 
 	return omap2_init_pmu(oh_num, oh_names);