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6e5a3275
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6e5a3275
编写于
6月 27, 2005
作者:
L
Linus Torvalds
浏览文件
操作
浏览文件
下载
差异文件
Merge
rsync://rsync.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
上级
b6d00f0d
63b61452
变更
21
隐藏空白更改
内联
并排
Showing
21 changed file
with
233 addition
and
357 deletion
+233
-357
arch/sparc64/kernel/auxio.c
arch/sparc64/kernel/auxio.c
+1
-1
arch/sparc64/kernel/entry.S
arch/sparc64/kernel/entry.S
+4
-112
arch/sparc64/kernel/irq.c
arch/sparc64/kernel/irq.c
+50
-121
arch/sparc64/kernel/semaphore.c
arch/sparc64/kernel/semaphore.c
+8
-4
arch/sparc64/kernel/sparc64_ksyms.c
arch/sparc64/kernel/sparc64_ksyms.c
+0
-1
arch/sparc64/kernel/trampoline.S
arch/sparc64/kernel/trampoline.S
+2
-1
arch/sparc64/lib/U1memcpy.S
arch/sparc64/lib/U1memcpy.S
+53
-50
arch/sparc64/lib/VISsave.S
arch/sparc64/lib/VISsave.S
+13
-2
arch/sparc64/lib/atomic.S
arch/sparc64/lib/atomic.S
+26
-16
arch/sparc64/lib/bitops.S
arch/sparc64/lib/bitops.S
+20
-11
arch/sparc64/lib/debuglocks.c
arch/sparc64/lib/debuglocks.c
+4
-2
arch/sparc64/lib/dec_and_lock.S
arch/sparc64/lib/dec_and_lock.S
+4
-2
arch/sparc64/lib/rwsem.S
arch/sparc64/lib/rwsem.S
+10
-5
arch/sparc64/mm/init.c
arch/sparc64/mm/init.c
+4
-2
arch/sparc64/mm/ultra.S
arch/sparc64/mm/ultra.S
+2
-1
include/asm-sparc64/auxio.h
include/asm-sparc64/auxio.h
+2
-0
include/asm-sparc64/floppy.h
include/asm-sparc64/floppy.h
+8
-8
include/asm-sparc64/irq.h
include/asm-sparc64/irq.h
+1
-6
include/asm-sparc64/rwsem.h
include/asm-sparc64/rwsem.h
+2
-1
include/asm-sparc64/spinlock.h
include/asm-sparc64/spinlock.h
+19
-10
include/asm-sparc64/spitfire.h
include/asm-sparc64/spitfire.h
+0
-1
未找到文件。
arch/sparc64/kernel/auxio.c
浏览文件 @
6e5a3275
...
...
@@ -16,7 +16,7 @@
#include <asm/ebus.h>
#include <asm/auxio.h>
/* This cannot be static, as it is referenced in
entry.S
*/
/* This cannot be static, as it is referenced in
irq.c
*/
void
__iomem
*
auxio_register
=
NULL
;
enum
auxio_type
{
...
...
arch/sparc64/kernel/entry.S
浏览文件 @
6e5a3275
...
...
@@ -271,8 +271,9 @@ cplus_fptrap_insn_1:
fmuld
%f0
,
%f2
,
%f26
faddd
%f0
,
%f2
,
%f28
fmuld
%f0
,
%f2
,
%f30
membar
#
Sync
b
,
pt
%
xcc
,
fpdis_exit
membar
#
Sync
nop
2
:
andcc
%
g5
,
FPRS_DU
,
%
g0
bne
,
pt
%
icc
,
3
f
fzero
%f32
...
...
@@ -301,8 +302,9 @@ cplus_fptrap_insn_2:
fmuld
%f32
,
%f34
,
%f58
faddd
%f32
,
%f34
,
%f60
fmuld
%f32
,
%f34
,
%f62
membar
#
Sync
ba
,
pt
%
xcc
,
fpdis_exit
membar
#
Sync
nop
3
:
mov
SECONDARY_CONTEXT
,
%
g3
add
%
g6
,
TI_FPREGS
,
%
g1
ldxa
[%
g3
]
ASI_DMMU
,
%
g5
...
...
@@ -699,116 +701,6 @@ utrap_ill:
ba
,
pt
%
xcc
,
rtrap
clr
%
l6
#ifdef CONFIG_BLK_DEV_FD
.
globl
floppy_hardint
floppy_hardint
:
wr
%
g0
,
(
1
<<
11
),
%
clear_softint
sethi
%
hi
(
doing_pdma
),
%
g1
ld
[%
g1
+
%
lo
(
doing_pdma
)],
%
g2
brz
,
pn
%
g2
,
floppy_dosoftint
sethi
%
hi
(
fdc_status
),
%
g3
ldx
[%
g3
+
%
lo
(
fdc_status
)],
%
g3
sethi
%
hi
(
pdma_vaddr
),
%
g5
ldx
[%
g5
+
%
lo
(
pdma_vaddr
)],
%
g4
sethi
%
hi
(
pdma_size
),
%
g5
ldx
[%
g5
+
%
lo
(
pdma_size
)],
%
g5
next_byte
:
lduba
[%
g3
]
ASI_PHYS_BYPASS_EC_E
,
%
g7
andcc
%
g7
,
0x80
,
%
g0
be
,
pn
%
icc
,
floppy_fifo_emptied
andcc
%
g7
,
0x20
,
%
g0
be
,
pn
%
icc
,
floppy_overrun
andcc
%
g7
,
0x40
,
%
g0
be
,
pn
%
icc
,
floppy_write
sub
%
g5
,
1
,
%
g5
inc
%
g3
lduba
[%
g3
]
ASI_PHYS_BYPASS_EC_E
,
%
g7
dec
%
g3
orcc
%
g0
,
%
g5
,
%
g0
stb
%
g7
,
[%
g4
]
bne
,
pn
%
xcc
,
next_byte
add
%
g4
,
1
,
%
g4
b
,
pt
%
xcc
,
floppy_tdone
nop
floppy_write
:
ldub
[%
g4
],
%
g7
orcc
%
g0
,
%
g5
,
%
g0
inc
%
g3
stba
%
g7
,
[%
g3
]
ASI_PHYS_BYPASS_EC_E
dec
%
g3
bne
,
pn
%
xcc
,
next_byte
add
%
g4
,
1
,
%
g4
floppy_tdone
:
sethi
%
hi
(
pdma_vaddr
),
%
g1
stx
%
g4
,
[%
g1
+
%
lo
(
pdma_vaddr
)]
sethi
%
hi
(
pdma_size
),
%
g1
stx
%
g5
,
[%
g1
+
%
lo
(
pdma_size
)]
sethi
%
hi
(
auxio_register
),
%
g1
ldx
[%
g1
+
%
lo
(
auxio_register
)],
%
g7
lduba
[%
g7
]
ASI_PHYS_BYPASS_EC_E
,
%
g5
or
%
g5
,
AUXIO_AUX1_FTCNT
,
%
g5
/*
andn
%
g5
,
AUXIO_AUX1_MASK
,
%
g5
*/
stba
%
g5
,
[%
g7
]
ASI_PHYS_BYPASS_EC_E
andn
%
g5
,
AUXIO_AUX1_FTCNT
,
%
g5
/*
andn
%
g5
,
AUXIO_AUX1_MASK
,
%
g5
*/
nop
; nop; nop; nop; nop; nop;
nop
; nop; nop; nop; nop; nop;
stba
%
g5
,
[%
g7
]
ASI_PHYS_BYPASS_EC_E
sethi
%
hi
(
doing_pdma
),
%
g1
b
,
pt
%
xcc
,
floppy_dosoftint
st
%
g0
,
[%
g1
+
%
lo
(
doing_pdma
)]
floppy_fifo_emptied
:
sethi
%
hi
(
pdma_vaddr
),
%
g1
stx
%
g4
,
[%
g1
+
%
lo
(
pdma_vaddr
)]
sethi
%
hi
(
pdma_size
),
%
g1
stx
%
g5
,
[%
g1
+
%
lo
(
pdma_size
)]
sethi
%
hi
(
irq_action
),
%
g1
or
%
g1
,
%
lo
(
irq_action
),
%
g1
ldx
[%
g1
+
(
11
<<
3
)],
%
g3
!
irqaction
[
floppy_irq
]
ldx
[%
g3
+
0x08
],
%
g4
!
action
->
flags
>>
48
==
ino
sethi
%
hi
(
ivector_table
),
%
g3
srlx
%
g4
,
48
,
%
g4
or
%
g3
,
%
lo
(
ivector_table
),
%
g3
sllx
%
g4
,
5
,
%
g4
ldx
[%
g3
+
%
g4
],
%
g4
!
&
ivector_table
[
ino
]
ldx
[%
g4
+
0x10
],
%
g4
!
bucket
->
iclr
stwa
%
g0
,
[%
g4
]
ASI_PHYS_BYPASS_EC_E
!
ICLR_IDLE
membar
#
Sync
!
probably
not
needed
...
retry
floppy_overrun
:
sethi
%
hi
(
pdma_vaddr
),
%
g1
stx
%
g4
,
[%
g1
+
%
lo
(
pdma_vaddr
)]
sethi
%
hi
(
pdma_size
),
%
g1
stx
%
g5
,
[%
g1
+
%
lo
(
pdma_size
)]
sethi
%
hi
(
doing_pdma
),
%
g1
st
%
g0
,
[%
g1
+
%
lo
(
doing_pdma
)]
floppy_dosoftint
:
rdpr
%
pil
,
%
g2
wrpr
%
g0
,
15
,
%
pil
sethi
%
hi
(
109
f
),
%
g7
b
,
pt
%
xcc
,
etrap_irq
109
:
or
%
g7
,
%
lo
(
109
b
),
%
g7
mov
11
,
%
o0
mov
0
,
%
o1
call
sparc_floppy_irq
add
%
sp
,
PTREGS_OFF
,
%
o2
b
,
pt
%
xcc
,
rtrap_irq
nop
#endif /* CONFIG_BLK_DEV_FD */
/
*
XXX
Here
is
stuff
we
still
need
to
write
...
-
DaveM
XXX
*/
.
globl
netbsd_syscall
netbsd_syscall
:
...
...
arch/sparc64/kernel/irq.c
浏览文件 @
6e5a3275
...
...
@@ -37,6 +37,7 @@
#include <asm/uaccess.h>
#include <asm/cache.h>
#include <asm/cpudata.h>
#include <asm/auxio.h>
#ifdef CONFIG_SMP
static
void
distribute_irqs
(
void
);
...
...
@@ -834,137 +835,65 @@ void handler_irq(int irq, struct pt_regs *regs)
}
#ifdef CONFIG_BLK_DEV_FD
extern
void
floppy_interrupt
(
int
irq
,
void
*
dev_cookie
,
struct
pt_regs
*
regs
)
;
extern
irqreturn_t
floppy_interrupt
(
int
,
void
*
,
struct
pt_regs
*
);
;
void
sparc_floppy_irq
(
int
irq
,
void
*
dev_cookie
,
struct
pt_regs
*
regs
)
{
struct
irqaction
*
action
=
*
(
irq
+
irq_action
);
struct
ino_bucket
*
bucket
;
int
cpu
=
smp_processor_id
();
irq_enter
();
kstat_this_cpu
.
irqs
[
irq
]
++
;
*
(
irq_work
(
cpu
,
irq
))
=
0
;
bucket
=
get_ino_in_irqaction
(
action
)
+
ivector_table
;
bucket
->
flags
|=
IBF_INPROGRESS
;
floppy_interrupt
(
irq
,
dev_cookie
,
regs
);
upa_writel
(
ICLR_IDLE
,
bucket
->
iclr
);
bucket
->
flags
&=
~
IBF_INPROGRESS
;
irq_exit
();
}
#endif
/* The following assumes that the branch lies before the place we
* are branching to. This is the case for a trap vector...
* You have been warned.
*/
#define SPARC_BRANCH(dest_addr, inst_addr) \
(0x10800000 | ((((dest_addr)-(inst_addr))>>2)&0x3fffff))
#define SPARC_NOP (0x01000000)
/* XXX No easy way to include asm/floppy.h XXX */
extern
unsigned
char
*
pdma_vaddr
;
extern
unsigned
long
pdma_size
;
extern
volatile
int
doing_pdma
;
extern
unsigned
long
fdc_status
;
static
void
install_fast_irq
(
unsigned
int
cpu_irq
,
irqreturn_t
(
*
handler
)(
int
,
void
*
,
struct
pt_regs
*
))
irqreturn_t
sparc_floppy_irq
(
int
irq
,
void
*
dev_cookie
,
struct
pt_regs
*
regs
)
{
extern
unsigned
long
sparc64_ttable_tl0
;
unsigned
long
ttent
=
(
unsigned
long
)
&
sparc64_ttable_tl0
;
unsigned
int
*
insns
;
ttent
+=
0x820
;
ttent
+=
(
cpu_irq
-
1
)
<<
5
;
insns
=
(
unsigned
int
*
)
ttent
;
insns
[
0
]
=
SPARC_BRANCH
(((
unsigned
long
)
handler
),
((
unsigned
long
)
&
insns
[
0
]));
insns
[
1
]
=
SPARC_NOP
;
__asm__
__volatile__
(
"membar #StoreStore; flush %0"
:
:
"r"
(
ttent
));
}
int
request_fast_irq
(
unsigned
int
irq
,
irqreturn_t
(
*
handler
)(
int
,
void
*
,
struct
pt_regs
*
),
unsigned
long
irqflags
,
const
char
*
name
,
void
*
dev_id
)
{
struct
irqaction
*
action
;
struct
ino_bucket
*
bucket
=
__bucket
(
irq
);
unsigned
long
flags
;
/* No pil0 dummy buckets allowed here. */
if
(
bucket
<
&
ivector_table
[
0
]
||
bucket
>=
&
ivector_table
[
NUM_IVECS
])
{
unsigned
int
*
caller
;
__asm__
__volatile__
(
"mov %%i7, %0"
:
"=r"
(
caller
));
printk
(
KERN_CRIT
"request_fast_irq: Old style IRQ registry attempt "
"from %p, irq %08x.
\n
"
,
caller
,
irq
);
return
-
EINVAL
;
}
if
(
!
handler
)
return
-
EINVAL
;
if
(
likely
(
doing_pdma
))
{
void
__iomem
*
stat
=
(
void
__iomem
*
)
fdc_status
;
unsigned
char
*
vaddr
=
pdma_vaddr
;
unsigned
long
size
=
pdma_size
;
u8
val
;
while
(
size
)
{
val
=
readb
(
stat
);
if
(
unlikely
(
!
(
val
&
0x80
)))
{
pdma_vaddr
=
vaddr
;
pdma_size
=
size
;
return
IRQ_HANDLED
;
}
if
(
unlikely
(
!
(
val
&
0x20
)))
{
pdma_vaddr
=
vaddr
;
pdma_size
=
size
;
doing_pdma
=
0
;
goto
main_interrupt
;
}
if
(
val
&
0x40
)
{
/* read */
*
vaddr
++
=
readb
(
stat
+
1
);
}
else
{
unsigned
char
data
=
*
vaddr
++
;
if
((
bucket
->
pil
==
0
)
||
(
bucket
->
pil
==
14
))
{
printk
(
"request_fast_irq: Trying to register shared IRQ 0 or 14.
\n
"
);
return
-
EBUSY
;
}
/* write */
writeb
(
data
,
stat
+
1
);
}
size
--
;
}
spin_lock_irqsave
(
&
irq_action_lock
,
flags
);
pdma_vaddr
=
vaddr
;
pdma_size
=
size
;
action
=
*
(
bucket
->
pil
+
irq_action
);
if
(
action
)
{
if
(
action
->
flags
&
SA_SHIRQ
)
panic
(
"Trying to register fast irq when already shared.
\n
"
);
if
(
irqflags
&
SA_SHIRQ
)
panic
(
"Trying to register fast irq as shared.
\n
"
);
printk
(
"request_fast_irq: Trying to register yet already owned.
\n
"
);
spin_unlock_irqrestore
(
&
irq_action_lock
,
flags
);
return
-
EBUSY
;
}
/* Send Terminal Count pulse to floppy controller. */
val
=
readb
(
auxio_register
);
val
|=
AUXIO_AUX1_FTCNT
;
writeb
(
val
,
auxio_register
);
val
&=
AUXIO_AUX1_FTCNT
;
writeb
(
val
,
auxio_register
);
/*
* We do not check for SA_SAMPLE_RANDOM in this path. Neither do we
* support smp intr affinity in this path.
*/
if
(
irqflags
&
SA_STATIC_ALLOC
)
{
if
(
static_irq_count
<
MAX_STATIC_ALLOC
)
action
=
&
static_irqaction
[
static_irq_count
++
];
else
printk
(
"Request for IRQ%d (%s) SA_STATIC_ALLOC failed "
"using kmalloc
\n
"
,
bucket
->
pil
,
name
);
}
if
(
action
==
NULL
)
action
=
(
struct
irqaction
*
)
kmalloc
(
sizeof
(
struct
irqaction
),
GFP_ATOMIC
);
if
(
!
action
)
{
spin_unlock_irqrestore
(
&
irq_action_lock
,
flags
);
return
-
ENOMEM
;
doing_pdma
=
0
;
}
install_fast_irq
(
bucket
->
pil
,
handler
);
bucket
->
irq_info
=
action
;
bucket
->
flags
|=
IBF_ACTIVE
;
action
->
handler
=
handler
;
action
->
flags
=
irqflags
;
action
->
dev_id
=
NULL
;
action
->
name
=
name
;
action
->
next
=
NULL
;
put_ino_in_irqaction
(
action
,
irq
);
put_smpaff_in_irqaction
(
action
,
CPU_MASK_NONE
);
*
(
bucket
->
pil
+
irq_action
)
=
action
;
enable_irq
(
irq
);
spin_unlock_irqrestore
(
&
irq_action_lock
,
flags
);
#ifdef CONFIG_SMP
distribute_irqs
();
#endif
return
0
;
main_interrupt:
return
floppy_interrupt
(
irq
,
dev_cookie
,
regs
);
}
EXPORT_SYMBOL
(
sparc_floppy_irq
);
#endif
/* We really don't need these at all on the Sparc. We only have
* stubs here because they are exported to modules.
...
...
arch/sparc64/kernel/semaphore.c
浏览文件 @
6e5a3275
...
...
@@ -32,8 +32,9 @@ static __inline__ int __sem_update_count(struct semaphore *sem, int incr)
" add %1, %4, %1
\n
"
" cas [%3], %0, %1
\n
"
" cmp %0, %1
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" bne,pn %%icc, 1b
\n
"
"
membar #StoreLoad | #StoreStore
\n
"
"
nop
\n
"
:
"=&r"
(
old_count
),
"=&r"
(
tmp
),
"=m"
(
sem
->
count
)
:
"r"
(
&
sem
->
count
),
"r"
(
incr
),
"m"
(
sem
->
count
)
:
"cc"
);
...
...
@@ -71,8 +72,9 @@ void up(struct semaphore *sem)
" cmp %%g1, %%g7
\n
"
" bne,pn %%icc, 1b
\n
"
" addcc %%g7, 1, %%g0
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" ble,pn %%icc, 3f
\n
"
"
membar #StoreLoad | #StoreStore
\n
"
"
nop
\n
"
"2:
\n
"
" .subsection 2
\n
"
"3: mov %0, %%g1
\n
"
...
...
@@ -128,8 +130,9 @@ void __sched down(struct semaphore *sem)
" cmp %%g1, %%g7
\n
"
" bne,pn %%icc, 1b
\n
"
" cmp %%g7, 1
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" bl,pn %%icc, 3f
\n
"
"
membar #StoreLoad | #StoreStore
\n
"
"
nop
\n
"
"2:
\n
"
" .subsection 2
\n
"
"3: mov %0, %%g1
\n
"
...
...
@@ -233,8 +236,9 @@ int __sched down_interruptible(struct semaphore *sem)
" cmp %%g1, %%g7
\n
"
" bne,pn %%icc, 1b
\n
"
" cmp %%g7, 1
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" bl,pn %%icc, 3f
\n
"
"
membar #StoreLoad | #StoreStore
\n
"
"
nop
\n
"
"2:
\n
"
" .subsection 2
\n
"
"3: mov %2, %%g1
\n
"
...
...
arch/sparc64/kernel/sparc64_ksyms.c
浏览文件 @
6e5a3275
...
...
@@ -227,7 +227,6 @@ EXPORT_SYMBOL(__flush_dcache_range);
EXPORT_SYMBOL
(
mostek_lock
);
EXPORT_SYMBOL
(
mstk48t02_regs
);
EXPORT_SYMBOL
(
request_fast_irq
);
#ifdef CONFIG_SUN_AUXIO
EXPORT_SYMBOL
(
auxio_set_led
);
EXPORT_SYMBOL
(
auxio_set_lte
);
...
...
arch/sparc64/kernel/trampoline.S
浏览文件 @
6e5a3275
...
...
@@ -98,8 +98,9 @@ startup_continue:
sethi
%
hi
(
prom_entry_lock
),
%
g2
1
:
ldstub
[%
g2
+
%
lo
(
prom_entry_lock
)],
%
g1
membar
#
StoreLoad
|
#
StoreStore
brnz
,
pn
%
g1
,
1
b
membar
#
StoreLoad
|
#
StoreStore
nop
sethi
%
hi
(
p1275buf
),
%
g2
or
%
g2
,
%
lo
(
p1275buf
),
%
g2
...
...
arch/sparc64/lib/U1memcpy.S
浏览文件 @
6e5a3275
...
...
@@ -87,14 +87,17 @@
#define LOOP_CHUNK3(src, dest, len, branch_dest) \
MAIN_LOOP_CHUNK
(
src
,
dest
,
f32
,
f48
,
len
,
branch_dest
)
#define DO_SYNC membar #Sync;
#define STORE_SYNC(dest, fsrc) \
EX_ST
(
STORE_BLK
(%
fsrc
,
%
dest
))
; \
add
%
dest
,
0x40
,
%
dest
;
add
%
dest
,
0x40
,
%
dest
; \
DO_SYNC
#define STORE_JUMP(dest, fsrc, target) \
EX_ST
(
STORE_BLK
(%
fsrc
,
%
dest
))
; \
add
%
dest
,
0x40
,
%
dest
; \
ba
,
pt
%
xcc
,
target
;
ba
,
pt
%
xcc
,
target
; \
nop
;
#define FINISH_VISCHUNK(dest, f0, f1, left) \
subcc
%
left
,
8
,
%
left
;\
...
...
@@ -239,17 +242,17 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */
ba
,
pt
%
xcc
,
1
b
+
4
faligndata
%f0
,
%f2
,
%f48
1
:
FREG_FROB
(
f16
,
f18
,
f20
,
f22
,
f24
,
f26
,
f28
,
f30
,
f32
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f32
,
f34
,
f36
,
f38
,
f40
,
f42
,
f44
,
f46
,
f0
)
STORE_JUMP
(
o0
,
f48
,
40
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
40
f
)
2
:
FREG_FROB
(
f32
,
f34
,
f36
,
f38
,
f40
,
f42
,
f44
,
f46
,
f0
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f0
,
f2
,
f4
,
f6
,
f8
,
f10
,
f12
,
f14
,
f16
)
STORE_JUMP
(
o0
,
f48
,
48
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
48
f
)
3
:
FREG_FROB
(
f0
,
f2
,
f4
,
f6
,
f8
,
f10
,
f12
,
f14
,
f16
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f16
,
f18
,
f20
,
f22
,
f24
,
f26
,
f28
,
f30
,
f32
)
STORE_JUMP
(
o0
,
f48
,
56
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
56
f
)
1
:
FREG_FROB
(
f2
,
f4
,
f6
,
f8
,
f10
,
f12
,
f14
,
f16
,
f18
)
LOOP_CHUNK1
(
o1
,
o0
,
GLOBAL_SPARE
,
1
f
)
...
...
@@ -260,17 +263,17 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */
ba
,
pt
%
xcc
,
1
b
+
4
faligndata
%f2
,
%f4
,
%f48
1
:
FREG_FROB
(
f18
,
f20
,
f22
,
f24
,
f26
,
f28
,
f30
,
f32
,
f34
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f34
,
f36
,
f38
,
f40
,
f42
,
f44
,
f46
,
f0
,
f2
)
STORE_JUMP
(
o0
,
f48
,
41
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
41
f
)
2
:
FREG_FROB
(
f34
,
f36
,
f38
,
f40
,
f42
,
f44
,
f46
,
f0
,
f2
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f2
,
f4
,
f6
,
f8
,
f10
,
f12
,
f14
,
f16
,
f18
)
STORE_JUMP
(
o0
,
f48
,
49
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
49
f
)
3
:
FREG_FROB
(
f2
,
f4
,
f6
,
f8
,
f10
,
f12
,
f14
,
f16
,
f18
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f18
,
f20
,
f22
,
f24
,
f26
,
f28
,
f30
,
f32
,
f34
)
STORE_JUMP
(
o0
,
f48
,
57
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
57
f
)
1
:
FREG_FROB
(
f4
,
f6
,
f8
,
f10
,
f12
,
f14
,
f16
,
f18
,
f20
)
LOOP_CHUNK1
(
o1
,
o0
,
GLOBAL_SPARE
,
1
f
)
...
...
@@ -281,17 +284,17 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */
ba
,
pt
%
xcc
,
1
b
+
4
faligndata
%f4
,
%f6
,
%f48
1
:
FREG_FROB
(
f20
,
f22
,
f24
,
f26
,
f28
,
f30
,
f32
,
f34
,
f36
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f36
,
f38
,
f40
,
f42
,
f44
,
f46
,
f0
,
f2
,
f4
)
STORE_JUMP
(
o0
,
f48
,
42
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
42
f
)
2
:
FREG_FROB
(
f36
,
f38
,
f40
,
f42
,
f44
,
f46
,
f0
,
f2
,
f4
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f4
,
f6
,
f8
,
f10
,
f12
,
f14
,
f16
,
f18
,
f20
)
STORE_JUMP
(
o0
,
f48
,
50
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
50
f
)
3
:
FREG_FROB
(
f4
,
f6
,
f8
,
f10
,
f12
,
f14
,
f16
,
f18
,
f20
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f20
,
f22
,
f24
,
f26
,
f28
,
f30
,
f32
,
f34
,
f36
)
STORE_JUMP
(
o0
,
f48
,
58
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
58
f
)
1
:
FREG_FROB
(
f6
,
f8
,
f10
,
f12
,
f14
,
f16
,
f18
,
f20
,
f22
)
LOOP_CHUNK1
(
o1
,
o0
,
GLOBAL_SPARE
,
1
f
)
...
...
@@ -302,17 +305,17 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */
ba
,
pt
%
xcc
,
1
b
+
4
faligndata
%f6
,
%f8
,
%f48
1
:
FREG_FROB
(
f22
,
f24
,
f26
,
f28
,
f30
,
f32
,
f34
,
f36
,
f38
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f38
,
f40
,
f42
,
f44
,
f46
,
f0
,
f2
,
f4
,
f6
)
STORE_JUMP
(
o0
,
f48
,
43
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
43
f
)
2
:
FREG_FROB
(
f38
,
f40
,
f42
,
f44
,
f46
,
f0
,
f2
,
f4
,
f6
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f6
,
f8
,
f10
,
f12
,
f14
,
f16
,
f18
,
f20
,
f22
)
STORE_JUMP
(
o0
,
f48
,
51
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
51
f
)
3
:
FREG_FROB
(
f6
,
f8
,
f10
,
f12
,
f14
,
f16
,
f18
,
f20
,
f22
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f22
,
f24
,
f26
,
f28
,
f30
,
f32
,
f34
,
f36
,
f38
)
STORE_JUMP
(
o0
,
f48
,
59
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
59
f
)
1
:
FREG_FROB
(
f8
,
f10
,
f12
,
f14
,
f16
,
f18
,
f20
,
f22
,
f24
)
LOOP_CHUNK1
(
o1
,
o0
,
GLOBAL_SPARE
,
1
f
)
...
...
@@ -323,17 +326,17 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */
ba
,
pt
%
xcc
,
1
b
+
4
faligndata
%f8
,
%f10
,
%f48
1
:
FREG_FROB
(
f24
,
f26
,
f28
,
f30
,
f32
,
f34
,
f36
,
f38
,
f40
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f40
,
f42
,
f44
,
f46
,
f0
,
f2
,
f4
,
f6
,
f8
)
STORE_JUMP
(
o0
,
f48
,
44
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
44
f
)
2
:
FREG_FROB
(
f40
,
f42
,
f44
,
f46
,
f0
,
f2
,
f4
,
f6
,
f8
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f8
,
f10
,
f12
,
f14
,
f16
,
f18
,
f20
,
f22
,
f24
)
STORE_JUMP
(
o0
,
f48
,
52
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
52
f
)
3
:
FREG_FROB
(
f8
,
f10
,
f12
,
f14
,
f16
,
f18
,
f20
,
f22
,
f24
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f24
,
f26
,
f28
,
f30
,
f32
,
f34
,
f36
,
f38
,
f40
)
STORE_JUMP
(
o0
,
f48
,
60
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
60
f
)
1
:
FREG_FROB
(
f10
,
f12
,
f14
,
f16
,
f18
,
f20
,
f22
,
f24
,
f26
)
LOOP_CHUNK1
(
o1
,
o0
,
GLOBAL_SPARE
,
1
f
)
...
...
@@ -344,17 +347,17 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */
ba
,
pt
%
xcc
,
1
b
+
4
faligndata
%f10
,
%f12
,
%f48
1
:
FREG_FROB
(
f26
,
f28
,
f30
,
f32
,
f34
,
f36
,
f38
,
f40
,
f42
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f42
,
f44
,
f46
,
f0
,
f2
,
f4
,
f6
,
f8
,
f10
)
STORE_JUMP
(
o0
,
f48
,
45
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
45
f
)
2
:
FREG_FROB
(
f42
,
f44
,
f46
,
f0
,
f2
,
f4
,
f6
,
f8
,
f10
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f10
,
f12
,
f14
,
f16
,
f18
,
f20
,
f22
,
f24
,
f26
)
STORE_JUMP
(
o0
,
f48
,
53
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
53
f
)
3
:
FREG_FROB
(
f10
,
f12
,
f14
,
f16
,
f18
,
f20
,
f22
,
f24
,
f26
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f26
,
f28
,
f30
,
f32
,
f34
,
f36
,
f38
,
f40
,
f42
)
STORE_JUMP
(
o0
,
f48
,
61
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
61
f
)
1
:
FREG_FROB
(
f12
,
f14
,
f16
,
f18
,
f20
,
f22
,
f24
,
f26
,
f28
)
LOOP_CHUNK1
(
o1
,
o0
,
GLOBAL_SPARE
,
1
f
)
...
...
@@ -365,17 +368,17 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */
ba
,
pt
%
xcc
,
1
b
+
4
faligndata
%f12
,
%f14
,
%f48
1
:
FREG_FROB
(
f28
,
f30
,
f32
,
f34
,
f36
,
f38
,
f40
,
f42
,
f44
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f44
,
f46
,
f0
,
f2
,
f4
,
f6
,
f8
,
f10
,
f12
)
STORE_JUMP
(
o0
,
f48
,
46
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
46
f
)
2
:
FREG_FROB
(
f44
,
f46
,
f0
,
f2
,
f4
,
f6
,
f8
,
f10
,
f12
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f12
,
f14
,
f16
,
f18
,
f20
,
f22
,
f24
,
f26
,
f28
)
STORE_JUMP
(
o0
,
f48
,
54
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
54
f
)
3
:
FREG_FROB
(
f12
,
f14
,
f16
,
f18
,
f20
,
f22
,
f24
,
f26
,
f28
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f28
,
f30
,
f32
,
f34
,
f36
,
f38
,
f40
,
f42
,
f44
)
STORE_JUMP
(
o0
,
f48
,
62
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
62
f
)
1
:
FREG_FROB
(
f14
,
f16
,
f18
,
f20
,
f22
,
f24
,
f26
,
f28
,
f30
)
LOOP_CHUNK1
(
o1
,
o0
,
GLOBAL_SPARE
,
1
f
)
...
...
@@ -386,17 +389,17 @@ FUNC_NAME: /* %o0=dst, %o1=src, %o2=len */
ba
,
pt
%
xcc
,
1
b
+
4
faligndata
%f14
,
%f16
,
%f48
1
:
FREG_FROB
(
f30
,
f32
,
f34
,
f36
,
f38
,
f40
,
f42
,
f44
,
f46
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f46
,
f0
,
f2
,
f4
,
f6
,
f8
,
f10
,
f12
,
f14
)
STORE_JUMP
(
o0
,
f48
,
47
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
47
f
)
2
:
FREG_FROB
(
f46
,
f0
,
f2
,
f4
,
f6
,
f8
,
f10
,
f12
,
f14
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f14
,
f16
,
f18
,
f20
,
f22
,
f24
,
f26
,
f28
,
f30
)
STORE_JUMP
(
o0
,
f48
,
55
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
55
f
)
3
:
FREG_FROB
(
f14
,
f16
,
f18
,
f20
,
f22
,
f24
,
f26
,
f28
,
f30
)
STORE_SYNC
(
o0
,
f48
)
membar
#
Sync
STORE_SYNC
(
o0
,
f48
)
FREG_FROB
(
f30
,
f32
,
f34
,
f36
,
f38
,
f40
,
f42
,
f44
,
f46
)
STORE_JUMP
(
o0
,
f48
,
63
f
)
membar
#
Sync
STORE_JUMP
(
o0
,
f48
,
63
f
)
40
:
FINISH_VISCHUNK
(
o0
,
f0
,
f2
,
g3
)
41
:
FINISH_VISCHUNK
(
o0
,
f2
,
f4
,
g3
)
...
...
arch/sparc64/lib/VISsave.S
浏览文件 @
6e5a3275
...
...
@@ -72,7 +72,11 @@ vis1: ldub [%g6 + TI_FPSAVED], %g3
stda
%f48
,
[%
g3
+
%
g1
]
ASI_BLK_P
5
:
membar
#
Sync
jmpl
%
g7
+
%
g0
,
%
g0
ba
,
pt
%
xcc
,
80
f
nop
.
align
32
80
:
jmpl
%
g7
+
%
g0
,
%
g0
nop
6
:
ldub
[%
g3
+
TI_FPSAVED
],
%
o5
...
...
@@ -87,8 +91,11 @@ vis1: ldub [%g6 + TI_FPSAVED], %g3
stda
%f32
,
[%
g2
+
%
g1
]
ASI_BLK_P
stda
%f48
,
[%
g3
+
%
g1
]
ASI_BLK_P
membar
#
Sync
jmpl
%
g7
+
%
g0
,
%
g0
ba
,
pt
%
xcc
,
80
f
nop
.
align
32
80
:
jmpl
%
g7
+
%
g0
,
%
g0
nop
.
align
32
...
...
@@ -126,6 +133,10 @@ VISenterhalf:
stda
%f0
,
[%
g2
+
%
g1
]
ASI_BLK_P
stda
%f16
,
[%
g3
+
%
g1
]
ASI_BLK_P
membar
#
Sync
ba
,
pt
%
xcc
,
4
f
nop
.
align
32
4
:
and
%
o5
,
FPRS_DU
,
%
o5
jmpl
%
g7
+
%
g0
,
%
g0
wr
%
o5
,
FPRS_FEF
,
%
fprs
arch/sparc64/lib/atomic.S
浏览文件 @
6e5a3275
...
...
@@ -7,18 +7,6 @@
#include <linux/config.h>
#include <asm/asi.h>
/
*
On
SMP
we
need
to
use
memory
barriers
to
ensure
*
correct
memory
operation
ordering
,
nop
these
out
*
for
uniprocessor
.
*/
#ifdef CONFIG_SMP
#define ATOMIC_PRE_BARRIER membar #StoreLoad | #LoadLoad
#define ATOMIC_POST_BARRIER membar #StoreLoad | #StoreStore
#else
#define ATOMIC_PRE_BARRIER nop
#define ATOMIC_POST_BARRIER nop
#endif
.
text
/
*
Two
versions
of
the
atomic
routines
,
one
that
...
...
@@ -52,6 +40,24 @@ atomic_sub: /* %o0 = decrement, %o1 = atomic_ptr */
nop
.
size
atomic_sub
,
.
-
atomic_sub
/
*
On
SMP
we
need
to
use
memory
barriers
to
ensure
*
correct
memory
operation
ordering
,
nop
these
out
*
for
uniprocessor
.
*/
#ifdef CONFIG_SMP
#define ATOMIC_PRE_BARRIER membar #StoreLoad | #LoadLoad;
#define ATOMIC_POST_BARRIER \
ba
,
pt
%
xcc
,
80
b
; \
membar
#
StoreLoad
|
#
StoreStore
80
:
retl
nop
#else
#define ATOMIC_PRE_BARRIER
#define ATOMIC_POST_BARRIER
#endif
.
globl
atomic_add_ret
.
type
atomic_add_ret
,#
function
atomic_add_ret
:
/
*
%
o0
=
increment
,
%
o1
=
atomic_ptr
*/
...
...
@@ -62,9 +68,10 @@ atomic_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
cmp
%
g1
,
%
g7
bne
,
pn
%
icc
,
1
b
add
%
g7
,
%
o0
,
%
g7
sra
%
g7
,
0
,
%
o0
ATOMIC_POST_BARRIER
retl
sra
%
g7
,
0
,
%
o0
nop
.
size
atomic_add_ret
,
.
-
atomic_add_ret
.
globl
atomic_sub_ret
...
...
@@ -77,9 +84,10 @@ atomic_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
cmp
%
g1
,
%
g7
bne
,
pn
%
icc
,
1
b
sub
%
g7
,
%
o0
,
%
g7
sra
%
g7
,
0
,
%
o0
ATOMIC_POST_BARRIER
retl
sra
%
g7
,
0
,
%
o0
nop
.
size
atomic_sub_ret
,
.
-
atomic_sub_ret
.
globl
atomic64_add
...
...
@@ -118,9 +126,10 @@ atomic64_add_ret: /* %o0 = increment, %o1 = atomic_ptr */
cmp
%
g1
,
%
g7
bne
,
pn
%
xcc
,
1
b
add
%
g7
,
%
o0
,
%
g7
mov
%
g7
,
%
o0
ATOMIC_POST_BARRIER
retl
mov
%
g7
,
%
o0
nop
.
size
atomic64_add_ret
,
.
-
atomic64_add_ret
.
globl
atomic64_sub_ret
...
...
@@ -133,7 +142,8 @@ atomic64_sub_ret: /* %o0 = decrement, %o1 = atomic_ptr */
cmp
%
g1
,
%
g7
bne
,
pn
%
xcc
,
1
b
sub
%
g7
,
%
o0
,
%
g7
mov
%
g7
,
%
o0
ATOMIC_POST_BARRIER
retl
mov
%
g7
,
%
o0
nop
.
size
atomic64_sub_ret
,
.
-
atomic64_sub_ret
arch/sparc64/lib/bitops.S
浏览文件 @
6e5a3275
...
...
@@ -7,20 +7,26 @@
#include <linux/config.h>
#include <asm/asi.h>
.
text
/
*
On
SMP
we
need
to
use
memory
barriers
to
ensure
*
correct
memory
operation
ordering
,
nop
these
out
*
for
uniprocessor
.
*/
#ifdef CONFIG_SMP
#define BITOP_PRE_BARRIER membar #StoreLoad | #LoadLoad
#define BITOP_POST_BARRIER membar #StoreLoad | #StoreStore
#define BITOP_POST_BARRIER \
ba
,
pt
%
xcc
,
80
b
; \
membar
#
StoreLoad
|
#
StoreStore
80
:
retl
nop
#else
#define BITOP_PRE_BARRIER
nop
#define BITOP_POST_BARRIER
nop
#define BITOP_PRE_BARRIER
#define BITOP_POST_BARRIER
#endif
.
text
.
globl
test_and_set_bit
.
type
test_and_set_bit
,#
function
test_and_set_bit
:
/
*
%
o0
=
nr
,
%
o1
=
addr
*/
...
...
@@ -37,10 +43,11 @@ test_and_set_bit: /* %o0=nr, %o1=addr */
cmp
%
g7
,
%
g1
bne
,
pn
%
xcc
,
1
b
and
%
g7
,
%
o2
,
%
g2
BITOP_POST_BARRIER
clr
%
o0
movrne
%
g2
,
1
,
%
o0
BITOP_POST_BARRIER
retl
movrne
%
g2
,
1
,
%
o0
nop
.
size
test_and_set_bit
,
.
-
test_and_set_bit
.
globl
test_and_clear_bit
...
...
@@ -59,10 +66,11 @@ test_and_clear_bit: /* %o0=nr, %o1=addr */
cmp
%
g7
,
%
g1
bne
,
pn
%
xcc
,
1
b
and
%
g7
,
%
o2
,
%
g2
BITOP_POST_BARRIER
clr
%
o0
movrne
%
g2
,
1
,
%
o0
BITOP_POST_BARRIER
retl
movrne
%
g2
,
1
,
%
o0
nop
.
size
test_and_clear_bit
,
.
-
test_and_clear_bit
.
globl
test_and_change_bit
...
...
@@ -81,10 +89,11 @@ test_and_change_bit: /* %o0=nr, %o1=addr */
cmp
%
g7
,
%
g1
bne
,
pn
%
xcc
,
1
b
and
%
g7
,
%
o2
,
%
g2
BITOP_POST_BARRIER
clr
%
o0
movrne
%
g2
,
1
,
%
o0
BITOP_POST_BARRIER
retl
movrne
%
g2
,
1
,
%
o0
nop
.
size
test_and_change_bit
,
.
-
test_and_change_bit
.
globl
set_bit
...
...
arch/sparc64/lib/debuglocks.c
浏览文件 @
6e5a3275
...
...
@@ -252,8 +252,9 @@ void _do_write_lock (rwlock_t *rw, char *str)
" andn %%g1, %%g3, %%g7
\n
"
" casx [%0], %%g1, %%g7
\n
"
" cmp %%g1, %%g7
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" bne,pn %%xcc, 1b
\n
"
"
membar #StoreLoad | #StoreStore
"
"
nop
"
:
/* no outputs */
:
"r"
(
&
(
rw
->
lock
))
:
"g3"
,
"g1"
,
"g7"
,
"cc"
,
"memory"
);
...
...
@@ -351,8 +352,9 @@ int _do_write_trylock (rwlock_t *rw, char *str)
" andn %%g1, %%g3, %%g7
\n
"
" casx [%0], %%g1, %%g7
\n
"
" cmp %%g1, %%g7
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" bne,pn %%xcc, 1b
\n
"
"
membar #StoreLoad | #StoreStore
"
"
nop
"
:
/* no outputs */
:
"r"
(
&
(
rw
->
lock
))
:
"g3"
,
"g1"
,
"g7"
,
"cc"
,
"memory"
);
...
...
arch/sparc64/lib/dec_and_lock.S
浏览文件 @
6e5a3275
...
...
@@ -48,8 +48,9 @@ start_to_zero:
#endif
to_zero
:
ldstub
[%
o1
],
%
g3
membar
#
StoreLoad
|
#
StoreStore
brnz
,
pn
%
g3
,
spin_on_lock
membar
#
StoreLoad
|
#
StoreStore
nop
loop2
:
cas
[%
o0
],
%
g2
,
%
g7
/*
ASSERT
(
g7
==
0
)
*/
cmp
%
g2
,
%
g7
...
...
@@ -71,8 +72,9 @@ loop2: cas [%o0], %g2, %g7 /* ASSERT(g7 == 0) */
nop
spin_on_lock
:
ldub
[%
o1
],
%
g3
membar
#
LoadLoad
brnz
,
pt
%
g3
,
spin_on_lock
membar
#
LoadLoad
nop
ba
,
pt
%
xcc
,
to_zero
nop
nop
arch/sparc64/lib/rwsem.S
浏览文件 @
6e5a3275
...
...
@@ -17,8 +17,9 @@ __down_read:
bne
,
pn
%
icc
,
1
b
add
%
g7
,
1
,
%
g7
cmp
%
g7
,
0
membar
#
StoreLoad
|
#
StoreStore
bl
,
pn
%
icc
,
3
f
membar
#
StoreLoad
|
#
StoreStore
nop
2
:
retl
nop
...
...
@@ -57,8 +58,9 @@ __down_write:
cmp
%
g3
,
%
g7
bne
,
pn
%
icc
,
1
b
cmp
%
g7
,
0
membar
#
StoreLoad
|
#
StoreStore
bne
,
pn
%
icc
,
3
f
membar
#
StoreLoad
|
#
StoreStore
nop
2
:
retl
nop
3
:
...
...
@@ -97,8 +99,9 @@ __up_read:
cmp
%
g1
,
%
g7
bne
,
pn
%
icc
,
1
b
cmp
%
g7
,
0
membar
#
StoreLoad
|
#
StoreStore
bl
,
pn
%
icc
,
3
f
membar
#
StoreLoad
|
#
StoreStore
nop
2
:
retl
nop
3
:
sethi
%
hi
(
RWSEM_ACTIVE_MASK
),
%
g1
...
...
@@ -126,8 +129,9 @@ __up_write:
bne
,
pn
%
icc
,
1
b
sub
%
g7
,
%
g1
,
%
g7
cmp
%
g7
,
0
membar
#
StoreLoad
|
#
StoreStore
bl
,
pn
%
icc
,
3
f
membar
#
StoreLoad
|
#
StoreStore
nop
2
:
retl
nop
...
...
@@ -151,8 +155,9 @@ __downgrade_write:
bne
,
pn
%
icc
,
1
b
sub
%
g7
,
%
g1
,
%
g7
cmp
%
g7
,
0
membar
#
StoreLoad
|
#
StoreStore
bl
,
pn
%
icc
,
3
f
membar
#
StoreLoad
|
#
StoreStore
nop
2
:
retl
nop
...
...
arch/sparc64/mm/init.c
浏览文件 @
6e5a3275
...
...
@@ -136,8 +136,9 @@ static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
"or %%g1, %0, %%g1
\n\t
"
"casx [%2], %%g7, %%g1
\n\t
"
"cmp %%g7, %%g1
\n\t
"
"membar #StoreLoad | #StoreStore
\n\t
"
"bne,pn %%xcc, 1b
\n\t
"
"
membar #StoreLoad | #StoreStore
"
"
nop
"
:
/* no outputs */
:
"r"
(
mask
),
"r"
(
non_cpu_bits
),
"r"
(
&
page
->
flags
)
:
"g1"
,
"g7"
);
...
...
@@ -157,8 +158,9 @@ static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long c
" andn %%g7, %1, %%g1
\n\t
"
"casx [%2], %%g7, %%g1
\n\t
"
"cmp %%g7, %%g1
\n\t
"
"membar #StoreLoad | #StoreStore
\n\t
"
"bne,pn %%xcc, 1b
\n\t
"
"
membar #StoreLoad | #StoreStore
\n
"
"
nop
\n
"
"2:"
:
/* no outputs */
:
"r"
(
cpu
),
"r"
(
mask
),
"r"
(
&
page
->
flags
),
...
...
arch/sparc64/mm/ultra.S
浏览文件 @
6e5a3275
...
...
@@ -266,8 +266,9 @@ __cheetah_flush_tlb_pending: /* 22 insns */
andn
%
o3
,
1
,
%
o3
stxa
%
g0
,
[%
o3
]
ASI_IMMU_DEMAP
2
:
stxa
%
g0
,
[%
o3
]
ASI_DMMU_DEMAP
membar
#
Sync
brnz
,
pt
%
o1
,
1
b
membar
#
Sync
nop
stxa
%
g2
,
[%
o4
]
ASI_DMMU
flush
%
g6
wrpr
%
g0
,
0
,
%
tl
...
...
include/asm-sparc64/auxio.h
浏览文件 @
6e5a3275
...
...
@@ -75,6 +75,8 @@
#ifndef __ASSEMBLY__
extern
void
__iomem
*
auxio_register
;
#define AUXIO_LTE_ON 1
#define AUXIO_LTE_OFF 0
...
...
include/asm-sparc64/floppy.h
浏览文件 @
6e5a3275
...
...
@@ -159,7 +159,7 @@ static void sun_82077_fd_outb(unsigned char value, unsigned long port)
* underruns. If non-zero, doing_pdma encodes the direction of
* the transfer for debugging. 1=read 2=write
*/
char
*
pdma_vaddr
;
unsigned
char
*
pdma_vaddr
;
unsigned
long
pdma_size
;
volatile
int
doing_pdma
=
0
;
...
...
@@ -209,8 +209,7 @@ static void sun_fd_enable_dma(void)
pdma_areasize
=
pdma_size
;
}
/* Our low-level entry point in arch/sparc/kernel/entry.S */
extern
irqreturn_t
floppy_hardint
(
int
irq
,
void
*
unused
,
struct
pt_regs
*
regs
);
extern
irqreturn_t
sparc_floppy_irq
(
int
,
void
*
,
struct
pt_regs
*
);
static
int
sun_fd_request_irq
(
void
)
{
...
...
@@ -220,8 +219,8 @@ static int sun_fd_request_irq(void)
if
(
!
once
)
{
once
=
1
;
error
=
request_
fast_irq
(
FLOPPY_IRQ
,
floppy_hardint
,
SA_INTERRUPT
,
"floppy"
,
NULL
);
error
=
request_
irq
(
FLOPPY_IRQ
,
sparc_floppy_irq
,
SA_INTERRUPT
,
"floppy"
,
NULL
);
return
((
error
==
0
)
?
0
:
-
1
);
}
...
...
@@ -615,7 +614,7 @@ static unsigned long __init sun_floppy_init(void)
struct
linux_ebus
*
ebus
;
struct
linux_ebus_device
*
edev
=
NULL
;
unsigned
long
config
=
0
;
unsigned
long
auxio_reg
;
void
__iomem
*
auxio_reg
;
for_each_ebus
(
ebus
)
{
for_each_ebusdev
(
edev
,
ebus
)
{
...
...
@@ -642,7 +641,7 @@ static unsigned long __init sun_floppy_init(void)
/* Make sure the high density bit is set, some systems
* (most notably Ultra5/Ultra10) come up with it clear.
*/
auxio_reg
=
edev
->
resource
[
2
].
start
;
auxio_reg
=
(
void
__iomem
*
)
edev
->
resource
[
2
].
start
;
writel
(
readl
(
auxio_reg
)
|
0x2
,
auxio_reg
);
sun_pci_ebus_dev
=
ebus
->
self
;
...
...
@@ -650,7 +649,8 @@ static unsigned long __init sun_floppy_init(void)
spin_lock_init
(
&
sun_pci_fd_ebus_dma
.
lock
);
/* XXX ioremap */
sun_pci_fd_ebus_dma
.
regs
=
edev
->
resource
[
1
].
start
;
sun_pci_fd_ebus_dma
.
regs
=
(
void
__iomem
*
)
edev
->
resource
[
1
].
start
;
if
(
!
sun_pci_fd_ebus_dma
.
regs
)
return
0
;
...
...
include/asm-sparc64/irq.h
浏览文件 @
6e5a3275
...
...
@@ -19,7 +19,7 @@
/* You should not mess with this directly. That's the job of irq.c.
*
* If you make changes here, please update hand coded assembler of
*
SBUS/floppy interrupt
handler in entry.S -DaveM
*
the vectored interrupt trap
handler in entry.S -DaveM
*
* This is currently one DCACHE line, two buckets per L2 cache
* line. Keep this in mind please.
...
...
@@ -122,11 +122,6 @@ extern void enable_irq(unsigned int);
extern
unsigned
int
build_irq
(
int
pil
,
int
inofixup
,
unsigned
long
iclr
,
unsigned
long
imap
);
extern
unsigned
int
sbus_build_irq
(
void
*
sbus
,
unsigned
int
ino
);
extern
int
request_fast_irq
(
unsigned
int
irq
,
irqreturn_t
(
*
handler
)(
int
,
void
*
,
struct
pt_regs
*
),
unsigned
long
flags
,
__const__
char
*
devname
,
void
*
dev_id
);
static
__inline__
void
set_softint
(
unsigned
long
bits
)
{
__asm__
__volatile__
(
"wr %0, 0x0, %%set_softint"
...
...
include/asm-sparc64/rwsem.h
浏览文件 @
6e5a3275
...
...
@@ -55,8 +55,9 @@ static __inline__ int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
"add %%g1, %1, %%g7
\n\t
"
"cas [%2], %%g1, %%g7
\n\t
"
"cmp %%g1, %%g7
\n\t
"
"membar #StoreLoad | #StoreStore
\n\t
"
"bne,pn %%icc, 1b
\n\t
"
"
membar #StoreLoad | #StoreStore
\n\t
"
"
nop
\n\t
"
"mov %%g7, %0
\n\t
"
:
"=&r"
(
tmp
)
:
"0"
(
tmp
),
"r"
(
sem
)
...
...
include/asm-sparc64/spinlock.h
浏览文件 @
6e5a3275
...
...
@@ -52,12 +52,14 @@ static inline void _raw_spin_lock(spinlock_t *lock)
__asm__
__volatile__
(
"1: ldstub [%1], %0
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" brnz,pn %0, 2f
\n
"
"
membar #StoreLoad | #StoreStore
\n
"
"
nop
\n
"
" .subsection 2
\n
"
"2: ldub [%1], %0
\n
"
" membar #LoadLoad
\n
"
" brnz,pt %0, 2b
\n
"
"
membar #LoadLoad
\n
"
"
nop
\n
"
" ba,a,pt %%xcc, 1b
\n
"
" .previous"
:
"=&r"
(
tmp
)
...
...
@@ -95,16 +97,18 @@ static inline void _raw_spin_lock_flags(spinlock_t *lock, unsigned long flags)
__asm__
__volatile__
(
"1: ldstub [%2], %0
\n
"
" brnz,pn %0, 2f
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" brnz,pn %0, 2f
\n
"
" nop
\n
"
" .subsection 2
\n
"
"2: rdpr %%pil, %1
\n
"
" wrpr %3, %%pil
\n
"
"3: ldub [%2], %0
\n
"
" brnz,pt %0, 3b
\n
"
" membar #LoadLoad
\n
"
" brnz,pt %0, 3b
\n
"
" nop
\n
"
" ba,pt %%xcc, 1b
\n
"
" wrpr %1, %%pil
\n
"
"
wrpr %1, %%pil
\n
"
" .previous"
:
"=&r"
(
tmp1
),
"=&r"
(
tmp2
)
:
"r"
(
lock
),
"r"
(
flags
)
...
...
@@ -162,12 +166,14 @@ static void inline __read_lock(rwlock_t *lock)
"4: add %0, 1, %1
\n
"
" cas [%2], %0, %1
\n
"
" cmp %0, %1
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" bne,pn %%icc, 1b
\n
"
"
membar #StoreLoad | #StoreStore
\n
"
"
nop
\n
"
" .subsection 2
\n
"
"2: ldsw [%2], %0
\n
"
" membar #LoadLoad
\n
"
" brlz,pt %0, 2b
\n
"
"
membar #LoadLoad
\n
"
"
nop
\n
"
" ba,a,pt %%xcc, 4b
\n
"
" .previous"
:
"=&r"
(
tmp1
),
"=&r"
(
tmp2
)
...
...
@@ -204,12 +210,14 @@ static void inline __write_lock(rwlock_t *lock)
"4: or %0, %3, %1
\n
"
" cas [%2], %0, %1
\n
"
" cmp %0, %1
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" bne,pn %%icc, 1b
\n
"
"
membar #StoreLoad | #StoreStore
\n
"
"
nop
\n
"
" .subsection 2
\n
"
"2: lduw [%2], %0
\n
"
" membar #LoadLoad
\n
"
" brnz,pt %0, 2b
\n
"
"
membar #LoadLoad
\n
"
"
nop
\n
"
" ba,a,pt %%xcc, 4b
\n
"
" .previous"
:
"=&r"
(
tmp1
),
"=&r"
(
tmp2
)
...
...
@@ -240,8 +248,9 @@ static int inline __write_trylock(rwlock_t *lock)
" or %0, %4, %1
\n
"
" cas [%3], %0, %1
\n
"
" cmp %0, %1
\n
"
" membar #StoreLoad | #StoreStore
\n
"
" bne,pn %%icc, 1b
\n
"
"
membar #StoreLoad | #StoreStore
\n
"
"
nop
\n
"
" mov 1, %2
\n
"
"2:"
:
"=&r"
(
tmp1
),
"=&r"
(
tmp2
),
"=&r"
(
result
)
...
...
include/asm-sparc64/spitfire.h
浏览文件 @
6e5a3275
...
...
@@ -111,7 +111,6 @@ static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long
"membar #Sync"
:
/* No outputs */
:
"r"
(
tag
),
"r"
(
addr
),
"i"
(
ASI_DCACHE_TAG
));
__asm__
__volatile__
(
"membar #Sync"
:
:
:
"memory"
);
}
/* The instruction cache lines are flushed with this, but note that
...
...
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