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raspberrypi-kernel
提交 66cbd3ab 编写于 作者: G Greg Kroah-Hartman
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Staging: brcm80211: s/uint32/u32/ 

Use the kernel types, don't invent your own.

Cc: Brett Rudley <brudley@broadcom.com>
Cc: Henry Ptasinski <henryp@broadcom.com>
Cc: Nohee Ko <noheek@broadcom.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>
上级 370adc7c
展开全部 隐藏空白更改
内联 并排
Showing with 2299 addition and 2304 deletion
drivers/staging/brcm80211/brcmfmac/bcmsdh.c
浏览文件 @ 66cbd3ab
...@@ -36,11 +36,11 @@ const uint bcmsdh_msglevel = BCMSDH_ERROR_VAL; ...@@ -36,11 +36,11 @@ const uint bcmsdh_msglevel = BCMSDH_ERROR_VAL;
struct bcmsdh_info { struct bcmsdh_info {
bool init_success; /* underlying driver successfully attached */ bool init_success; /* underlying driver successfully attached */
void *sdioh; /* handler for sdioh */ void *sdioh; /* handler for sdioh */
uint32 vendevid; /* Target Vendor and Device ID on SD bus */ u32 vendevid; /* Target Vendor and Device ID on SD bus */
osl_t *osh; osl_t *osh;
bool regfail; /* Save status of last bool regfail; /* Save status of last
reg_read/reg_write call */ reg_read/reg_write call */
uint32 sbwad; /* Save backplane window address */ u32 sbwad; /* Save backplane window address */
}; };
/* local copy of bcm sd handler */ /* local copy of bcm sd handler */
bcmsdh_info_t *l_bcmsdh; bcmsdh_info_t *l_bcmsdh;
...@@ -78,7 +78,7 @@ bcmsdh_info_t *bcmsdh_attach(osl_t *osh, void *cfghdl, void **regsva, uint irq) ...@@ -78,7 +78,7 @@ bcmsdh_info_t *bcmsdh_attach(osl_t *osh, void *cfghdl, void **regsva, uint irq)
bcmsdh->osh = osh; bcmsdh->osh = osh;
bcmsdh->init_success = TRUE; bcmsdh->init_success = TRUE;
*regsva = (uint32 *) SI_ENUM_BASE; *regsva = (u32 *) SI_ENUM_BASE;
/* Report the BAR, to fix if needed */ /* Report the BAR, to fix if needed */
bcmsdh->sbwad = SI_ENUM_BASE; bcmsdh->sbwad = SI_ENUM_BASE;
...@@ -181,7 +181,7 @@ int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh) ...@@ -181,7 +181,7 @@ int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh)
return BCME_UNSUPPORTED; return BCME_UNSUPPORTED;
} }
u8 bcmsdh_cfg_read(void *sdh, uint fnc_num, uint32 addr, int *err) u8 bcmsdh_cfg_read(void *sdh, uint fnc_num, u32 addr, int *err)
{ {
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
SDIOH_API_RC status; SDIOH_API_RC status;
...@@ -217,7 +217,7 @@ u8 bcmsdh_cfg_read(void *sdh, uint fnc_num, uint32 addr, int *err) ...@@ -217,7 +217,7 @@ u8 bcmsdh_cfg_read(void *sdh, uint fnc_num, uint32 addr, int *err)
} }
void void
bcmsdh_cfg_write(void *sdh, uint fnc_num, uint32 addr, u8 data, int *err) bcmsdh_cfg_write(void *sdh, uint fnc_num, u32 addr, u8 data, int *err)
{ {
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
SDIOH_API_RC status; SDIOH_API_RC status;
...@@ -249,11 +249,11 @@ bcmsdh_cfg_write(void *sdh, uint fnc_num, uint32 addr, u8 data, int *err) ...@@ -249,11 +249,11 @@ bcmsdh_cfg_write(void *sdh, uint fnc_num, uint32 addr, u8 data, int *err)
__func__, fnc_num, addr, data)); __func__, fnc_num, addr, data));
} }
uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err) u32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, u32 addr, int *err)
{ {
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
SDIOH_API_RC status; SDIOH_API_RC status;
uint32 data = 0; u32 data = 0;
if (!bcmsdh) if (!bcmsdh)
bcmsdh = l_bcmsdh; bcmsdh = l_bcmsdh;
...@@ -267,14 +267,14 @@ uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err) ...@@ -267,14 +267,14 @@ uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err)
if (err) if (err)
*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR); *err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint32data = 0x%x\n", BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, u32data = 0x%x\n",
__func__, fnc_num, addr, data)); __func__, fnc_num, addr, data));
return data; return data;
} }
void void
bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, bcmsdh_cfg_write_word(void *sdh, uint fnc_num, u32 addr, u32 data,
int *err) int *err)
{ {
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
...@@ -292,7 +292,7 @@ bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, ...@@ -292,7 +292,7 @@ bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data,
if (err) if (err)
*err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR); *err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, uint32data = 0x%x\n", BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, u32data = 0x%x\n",
__func__, fnc_num, addr, data)); __func__, fnc_num, addr, data));
} }
...@@ -336,7 +336,7 @@ int bcmsdh_cis_read(void *sdh, uint func, u8 * cis, uint length) ...@@ -336,7 +336,7 @@ int bcmsdh_cis_read(void *sdh, uint func, u8 * cis, uint length)
return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR; return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
} }
static int bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address) static int bcmsdhsdio_set_sbaddr_window(void *sdh, u32 address)
{ {
int err = 0; int err = 0;
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
...@@ -353,11 +353,11 @@ static int bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address) ...@@ -353,11 +353,11 @@ static int bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address)
return err; return err;
} }
uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size) u32 bcmsdh_reg_read(void *sdh, u32 addr, uint size)
{ {
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
SDIOH_API_RC status; SDIOH_API_RC status;
uint32 word = 0; u32 word = 0;
uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK; uint bar0 = addr & ~SBSDIO_SB_OFT_ADDR_MASK;
BCMSDH_INFO(("%s:fun = 1, addr = 0x%x, ", __func__, addr)); BCMSDH_INFO(("%s:fun = 1, addr = 0x%x, ", __func__, addr));
...@@ -383,7 +383,7 @@ uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size) ...@@ -383,7 +383,7 @@ uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size)
bcmsdh->regfail = !(SDIOH_API_SUCCESS(status)); bcmsdh->regfail = !(SDIOH_API_SUCCESS(status));
BCMSDH_INFO(("uint32data = 0x%x\n", word)); BCMSDH_INFO(("u32data = 0x%x\n", word));
/* if ok, return appropriately masked word */ /* if ok, return appropriately masked word */
if (SDIOH_API_SUCCESS(status)) { if (SDIOH_API_SUCCESS(status)) {
...@@ -392,7 +392,7 @@ uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size) ...@@ -392,7 +392,7 @@ uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size)
return word & 0xff; return word & 0xff;
case sizeof(u16): case sizeof(u16):
return word & 0xffff; return word & 0xffff;
case sizeof(uint32): case sizeof(u32):
return word; return word;
default: default:
bcmsdh->regfail = TRUE; bcmsdh->regfail = TRUE;
...@@ -406,7 +406,7 @@ uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size) ...@@ -406,7 +406,7 @@ uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size)
return 0xFFFFFFFF; return 0xFFFFFFFF;
} }
uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data) u32 bcmsdh_reg_write(void *sdh, u32 addr, uint size, u32 data)
{ {
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
SDIOH_API_RC status; SDIOH_API_RC status;
...@@ -451,7 +451,7 @@ bool bcmsdh_regfail(void *sdh) ...@@ -451,7 +451,7 @@ bool bcmsdh_regfail(void *sdh)
} }
int int
bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags, bcmsdh_recv_buf(void *sdh, u32 addr, uint fn, uint flags,
u8 *buf, uint nbytes, void *pkt, u8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle) bcmsdh_cmplt_fn_t complete, void *handle)
{ {
...@@ -496,7 +496,7 @@ bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags, ...@@ -496,7 +496,7 @@ bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
} }
int int
bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags, bcmsdh_send_buf(void *sdh, u32 addr, uint fn, uint flags,
u8 *buf, uint nbytes, void *pkt, u8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle) bcmsdh_cmplt_fn_t complete, void *handle)
{ {
...@@ -540,7 +540,7 @@ bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags, ...@@ -540,7 +540,7 @@ bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR; return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
} }
int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, u8 *buf, uint nbytes) int bcmsdh_rwdata(void *sdh, uint rw, u32 addr, u8 *buf, uint nbytes)
{ {
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
SDIOH_API_RC status; SDIOH_API_RC status;
...@@ -612,12 +612,12 @@ void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh) ...@@ -612,12 +612,12 @@ void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh)
} }
/* Function to pass device-status bits to DHD. */ /* Function to pass device-status bits to DHD. */
uint32 bcmsdh_get_dstatus(void *sdh) u32 bcmsdh_get_dstatus(void *sdh)
{ {
return 0; return 0;
} }
uint32 bcmsdh_cur_sbwad(void *sdh) u32 bcmsdh_cur_sbwad(void *sdh)
{ {
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh; bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
...@@ -627,7 +627,7 @@ uint32 bcmsdh_cur_sbwad(void *sdh) ...@@ -627,7 +627,7 @@ uint32 bcmsdh_cur_sbwad(void *sdh)
return bcmsdh->sbwad; return bcmsdh->sbwad;
} }
void bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev) void bcmsdh_chipinfo(void *sdh, u32 chip, u32 chiprev)
{ {
return; return;
} }
drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c
浏览文件 @ 66cbd3ab
...@@ -164,7 +164,7 @@ int bcmsdh_probe(struct device *dev) ...@@ -164,7 +164,7 @@ int bcmsdh_probe(struct device *dev)
struct resource *r; struct resource *r;
#endif /* BCMLXSDMMC */ #endif /* BCMLXSDMMC */
int irq = 0; int irq = 0;
uint32 vendevid; u32 vendevid;
unsigned long irq_flags = 0; unsigned long irq_flags = 0;
#if !defined(BCMLXSDMMC) && defined(BCMPLATFORM_BUS) #if !defined(BCMLXSDMMC) && defined(BCMPLATFORM_BUS)
...@@ -384,7 +384,7 @@ bcmsdh_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -384,7 +384,7 @@ bcmsdh_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
if ((pdev->vendor == VENDOR_TI) if ((pdev->vendor == VENDOR_TI)
&& ((pdev->device == PCIXX21_FLASHMEDIA_ID) && ((pdev->device == PCIXX21_FLASHMEDIA_ID)
|| (pdev->device == PCIXX21_FLASHMEDIA0_ID))) { || (pdev->device == PCIXX21_FLASHMEDIA0_ID))) {
uint32 config_reg; u32 config_reg;
SDLX_MSG(("%s: Disabling TI FlashMedia Controller.\n", SDLX_MSG(("%s: Disabling TI FlashMedia Controller.\n",
__func__)); __func__));
......
drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c
浏览文件 @ 66cbd3ab
...@@ -44,7 +44,7 @@ extern void sdio_function_cleanup(void); ...@@ -44,7 +44,7 @@ extern void sdio_function_cleanup(void);
static void IRQHandler(struct sdio_func *func); static void IRQHandler(struct sdio_func *func);
static void IRQHandlerF2(struct sdio_func *func); static void IRQHandlerF2(struct sdio_func *func);
#endif /* !defined(OOB_INTR_ONLY) */ #endif /* !defined(OOB_INTR_ONLY) */
static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr); static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, u32 regaddr);
extern int sdio_reset_comm(struct mmc_card *card); extern int sdio_reset_comm(struct mmc_card *card);
extern PBCMSDH_SDMMC_INSTANCE gInstance; extern PBCMSDH_SDMMC_INSTANCE gInstance;
...@@ -66,13 +66,13 @@ DHD_PM_RESUME_WAIT_INIT(sdioh_request_buffer_wait); ...@@ -66,13 +66,13 @@ DHD_PM_RESUME_WAIT_INIT(sdioh_request_buffer_wait);
#define DMA_ALIGN_MASK 0x03 #define DMA_ALIGN_MASK 0x03
int sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, int sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
int regsize, uint32 *data); int regsize, u32 *data);
static int sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd) static int sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd)
{ {
int err_ret; int err_ret;
uint32 fbraddr; u32 fbraddr;
u8 func; u8 func;
sd_trace(("%s\n", __func__)); sd_trace(("%s\n", __func__));
...@@ -406,7 +406,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name, ...@@ -406,7 +406,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
int val_size; int val_size;
int32 int_val = 0; int32 int_val = 0;
bool bool_val; bool bool_val;
uint32 actionid; u32 actionid;
ASSERT(name); ASSERT(name);
ASSERT(len >= 0); ASSERT(len >= 0);
...@@ -468,7 +468,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name, ...@@ -468,7 +468,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
break; break;
case IOV_GVAL(IOV_BLOCKSIZE): case IOV_GVAL(IOV_BLOCKSIZE):
if ((uint32) int_val > si->num_funcs) { if ((u32) int_val > si->num_funcs) {
bcmerror = BCME_BADARG; bcmerror = BCME_BADARG;
break; break;
} }
...@@ -478,7 +478,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name, ...@@ -478,7 +478,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
case IOV_SVAL(IOV_BLOCKSIZE): case IOV_SVAL(IOV_BLOCKSIZE):
{ {
uint func = ((uint32) int_val >> 16); uint func = ((u32) int_val >> 16);
uint blksize = (u16) int_val; uint blksize = (u16) int_val;
uint maxsize; uint maxsize;
...@@ -542,7 +542,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name, ...@@ -542,7 +542,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
break; break;
case IOV_GVAL(IOV_DIVISOR): case IOV_GVAL(IOV_DIVISOR):
int_val = (uint32) sd_divisor; int_val = (u32) sd_divisor;
bcopy(&int_val, arg, val_size); bcopy(&int_val, arg, val_size);
break; break;
...@@ -551,7 +551,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name, ...@@ -551,7 +551,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
break; break;
case IOV_GVAL(IOV_POWER): case IOV_GVAL(IOV_POWER):
int_val = (uint32) sd_power; int_val = (u32) sd_power;
bcopy(&int_val, arg, val_size); bcopy(&int_val, arg, val_size);
break; break;
...@@ -560,7 +560,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name, ...@@ -560,7 +560,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
break; break;
case IOV_GVAL(IOV_CLOCK): case IOV_GVAL(IOV_CLOCK):
int_val = (uint32) sd_clock; int_val = (u32) sd_clock;
bcopy(&int_val, arg, val_size); bcopy(&int_val, arg, val_size);
break; break;
...@@ -569,7 +569,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name, ...@@ -569,7 +569,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
break; break;
case IOV_GVAL(IOV_SDMODE): case IOV_GVAL(IOV_SDMODE):
int_val = (uint32) sd_sdmode; int_val = (u32) sd_sdmode;
bcopy(&int_val, arg, val_size); bcopy(&int_val, arg, val_size);
break; break;
...@@ -578,7 +578,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name, ...@@ -578,7 +578,7 @@ sdioh_iovar_op(sdioh_info_t *si, const char *name,
break; break;
case IOV_GVAL(IOV_HISPEED): case IOV_GVAL(IOV_HISPEED):
int_val = (uint32) sd_hiok; int_val = (u32) sd_hiok;
bcopy(&int_val, arg, val_size); bcopy(&int_val, arg, val_size);
break; break;
...@@ -703,7 +703,7 @@ SDIOH_API_RC sdioh_enable_hw_oob_intr(sdioh_info_t *sd, bool enable) ...@@ -703,7 +703,7 @@ SDIOH_API_RC sdioh_enable_hw_oob_intr(sdioh_info_t *sd, bool enable)
#endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */ #endif /* defined(OOB_INTR_ONLY) && defined(HW_OOB) */
extern SDIOH_API_RC extern SDIOH_API_RC
sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, u8 *data) sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, u32 addr, u8 *data)
{ {
SDIOH_API_RC status; SDIOH_API_RC status;
/* No lock needed since sdioh_request_byte does locking */ /* No lock needed since sdioh_request_byte does locking */
...@@ -712,7 +712,7 @@ sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, u8 *data) ...@@ -712,7 +712,7 @@ sdioh_cfg_read(sdioh_info_t *sd, uint fnc_num, uint32 addr, u8 *data)
} }
extern SDIOH_API_RC extern SDIOH_API_RC
sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, u8 *data) sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, u32 addr, u8 *data)
{ {
/* No lock needed since sdioh_request_byte does locking */ /* No lock needed since sdioh_request_byte does locking */
SDIOH_API_RC status; SDIOH_API_RC status;
...@@ -720,11 +720,11 @@ sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, u8 *data) ...@@ -720,11 +720,11 @@ sdioh_cfg_write(sdioh_info_t *sd, uint fnc_num, uint32 addr, u8 *data)
return status; return status;
} }
static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr) static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, u32 regaddr)
{ {
/* read 24 bits and return valid 17 bit addr */ /* read 24 bits and return valid 17 bit addr */
int i; int i;
uint32 scratch, regdata; u32 scratch, regdata;
u8 *ptr = (u8 *)&scratch; u8 *ptr = (u8 *)&scratch;
for (i = 0; i < 3; i++) { for (i = 0; i < 3; i++) {
if ((sdioh_sdmmc_card_regread(sd, 0, regaddr, 1, &regdata)) != if ((sdioh_sdmmc_card_regread(sd, 0, regaddr, 1, &regdata)) !=
...@@ -742,11 +742,11 @@ static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr) ...@@ -742,11 +742,11 @@ static int sdioh_sdmmc_get_cisaddr(sdioh_info_t *sd, uint32 regaddr)
} }
extern SDIOH_API_RC extern SDIOH_API_RC
sdioh_cis_read(sdioh_info_t *sd, uint func, u8 *cisd, uint32 length) sdioh_cis_read(sdioh_info_t *sd, uint func, u8 *cisd, u32 length)
{ {
uint32 count; u32 count;
int offset; int offset;
uint32 foo; u32 foo;
u8 *cis = cisd; u8 *cis = cisd;
sd_trace(("%s: Func = %d\n", __func__, func)); sd_trace(("%s: Func = %d\n", __func__, func));
...@@ -876,7 +876,7 @@ sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr, ...@@ -876,7 +876,7 @@ sdioh_request_byte(sdioh_info_t *sd, uint rw, uint func, uint regaddr,
extern SDIOH_API_RC extern SDIOH_API_RC
sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func, sdioh_request_word(sdioh_info_t *sd, uint cmd_type, uint rw, uint func,
uint addr, uint32 *word, uint nbytes) uint addr, u32 *word, uint nbytes)
{ {
int err_ret = SDIOH_API_RC_FAIL; int err_ret = SDIOH_API_RC_FAIL;
...@@ -932,7 +932,7 @@ sdioh_request_packet(sdioh_info_t *sd, uint fix_inc, uint write, uint func, ...@@ -932,7 +932,7 @@ sdioh_request_packet(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
uint addr, void *pkt) uint addr, void *pkt)
{ {
bool fifo = (fix_inc == SDIOH_DATA_FIX); bool fifo = (fix_inc == SDIOH_DATA_FIX);
uint32 SGCount = 0; u32 SGCount = 0;
int err_ret = 0; int err_ret = 0;
void *pnext; void *pnext;
...@@ -963,7 +963,7 @@ sdioh_request_packet(sdioh_info_t *sd, uint fix_inc, uint write, uint func, ...@@ -963,7 +963,7 @@ sdioh_request_packet(sdioh_info_t *sd, uint fix_inc, uint write, uint func,
* is supposed to give * is supposed to give
* us something we can work with. * us something we can work with.
*/ */
ASSERT(((uint32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) == 0); ASSERT(((u32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) == 0);
if ((write) && (!fifo)) { if ((write) && (!fifo)) {
err_ret = sdio_memcpy_toio(gInstance->func[func], addr, err_ret = sdio_memcpy_toio(gInstance->func[func], addr,
...@@ -1067,7 +1067,7 @@ sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write, ...@@ -1067,7 +1067,7 @@ sdioh_request_buffer(sdioh_info_t *sd, uint pio_dma, uint fix_inc, uint write,
#else #else
PKTFREE(sd->osh, mypkt, write ? TRUE : FALSE); PKTFREE(sd->osh, mypkt, write ? TRUE : FALSE);
#endif /* DHD_USE_STATIC_BUF */ #endif /* DHD_USE_STATIC_BUF */
} else if (((uint32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) != 0) { } else if (((u32) (PKTDATA(pkt)) & DMA_ALIGN_MASK) != 0) {
/* Case 2: We have a packet, but it is unaligned. */ /* Case 2: We have a packet, but it is unaligned. */
/* In this case, we cannot have a chain. */ /* In this case, we cannot have a chain. */
...@@ -1156,8 +1156,8 @@ void sdioh_sdmmc_devintr_on(sdioh_info_t *sd) ...@@ -1156,8 +1156,8 @@ void sdioh_sdmmc_devintr_on(sdioh_info_t *sd)
/* Read client card reg */ /* Read client card reg */
int int
sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, uint32 regaddr, sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
int regsize, uint32 *data) int regsize, u32 *data)
{ {
if ((func == 0) || (regsize == 1)) { if ((func == 0) || (regsize == 1)) {
...@@ -1222,8 +1222,8 @@ static void IRQHandlerF2(struct sdio_func *func) ...@@ -1222,8 +1222,8 @@ static void IRQHandlerF2(struct sdio_func *func)
#ifdef NOTUSED #ifdef NOTUSED
/* Write client card reg */ /* Write client card reg */
static int static int
sdioh_sdmmc_card_regwrite(sdioh_info_t *sd, int func, uint32 regaddr, sdioh_sdmmc_card_regwrite(sdioh_info_t *sd, int func, u32 regaddr,
int regsize, uint32 data) int regsize, u32 data)
{ {
if ((func == 0) || (regsize == 1)) { if ((func == 0) || (regsize == 1)) {
......
drivers/staging/brcm80211/brcmfmac/bcmutils.c
浏览文件 @ 66cbd3ab
...@@ -1170,7 +1170,7 @@ u16 hndcrc16(u8 *pdata, /* pointer to array of data to process */ ...@@ -1170,7 +1170,7 @@ u16 hndcrc16(u8 *pdata, /* pointer to array of data to process */
return crc; return crc;
} }
static const uint32 crc32_table[256] = { static const u32 crc32_table[256] = {
0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
...@@ -1237,9 +1237,9 @@ static const uint32 crc32_table[256] = { ...@@ -1237,9 +1237,9 @@ static const uint32 crc32_table[256] = {
0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
}; };
uint32 hndcrc32(u8 *pdata, /* pointer to array of data to process */ u32 hndcrc32(u8 *pdata, /* pointer to array of data to process */
uint nbytes, /* number of input data bytes to process */ uint nbytes, /* number of input data bytes to process */
uint32 crc /* either CRC32_INIT_VALUE or previous u32 crc /* either CRC32_INIT_VALUE or previous
return value */ return value */
) )
{ {
...@@ -1288,8 +1288,8 @@ void testcrc32(void) ...@@ -1288,8 +1288,8 @@ void testcrc32(void)
uint j, k, l; uint j, k, l;
u8 *buf; u8 *buf;
uint len[CNBUFS]; uint len[CNBUFS];
uint32 crcr; u32 crcr;
uint32 crc32tv[CNBUFS] = { u32 crc32tv[CNBUFS] = {
0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110}; 0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
ASSERT((buf = MALLOC(CBUFSIZ * CNBUFS)) != NULL); ASSERT((buf = MALLOC(CBUFSIZ * CNBUFS)) != NULL);
...@@ -1408,13 +1408,13 @@ bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key) ...@@ -1408,13 +1408,13 @@ bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
#if defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || defined(WLMSG_ASSOC) || \ #if defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) || defined(WLMSG_ASSOC) || \
defined(DHD_DEBUG) defined(DHD_DEBUG)
int int
bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char *buf, int len) bcm_format_flags(const bcm_bit_desc_t *bd, u32 flags, char *buf, int len)
{ {
int i; int i;
char *p = buf; char *p = buf;
char hexstr[16]; char hexstr[16];
int slen = 0; int slen = 0;
uint32 bit; u32 bit;
const char *name; const char *name;
if (len < 2 || !buf) if (len < 2 || !buf)
...@@ -1500,7 +1500,7 @@ void prhex(const char *msg, unsigned char *buf, uint nbytes) ...@@ -1500,7 +1500,7 @@ void prhex(const char *msg, unsigned char *buf, uint nbytes)
#endif /* defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) */ #endif /* defined(WLMSG_PRHDRS) || defined(WLMSG_PRPKT) */
/* Produce a human-readable string for boardrev */ /* Produce a human-readable string for boardrev */
char *bcm_brev_str(uint32 brev, char *buf) char *bcm_brev_str(u32 brev, char *buf)
{ {
if (brev < 0x100) if (brev < 0x100)
snprintf(buf, 8, "%d.%d", (brev & 0xf0) >> 4, brev & 0xf); snprintf(buf, 8, "%d.%d", (brev & 0xf0) >> 4, brev & 0xf);
...@@ -1540,7 +1540,7 @@ void printbig(char *buf) ...@@ -1540,7 +1540,7 @@ void printbig(char *buf)
/* routine to dump fields in a fileddesc structure */ /* routine to dump fields in a fileddesc structure */
uint uint
bcmdumpfields(bcmutl_rdreg_rtn read_rtn, void *arg0, uint arg1, bcmdumpfields(bcmutl_rdreg_rtn read_rtn, void *arg0, uint arg1,
struct fielddesc *fielddesc_array, char *buf, uint32 bufsize) struct fielddesc *fielddesc_array, char *buf, u32 bufsize)
{ {
uint filled_len; uint filled_len;
int len; int len;
...@@ -1555,7 +1555,7 @@ bcmdumpfields(bcmutl_rdreg_rtn read_rtn, void *arg0, uint arg1, ...@@ -1555,7 +1555,7 @@ bcmdumpfields(bcmutl_rdreg_rtn read_rtn, void *arg0, uint arg1,
len = snprintf(buf, bufsize, cur_ptr->nameandfmt, len = snprintf(buf, bufsize, cur_ptr->nameandfmt,
read_rtn(arg0, arg1, cur_ptr->offset)); read_rtn(arg0, arg1, cur_ptr->offset));
/* check for snprintf overflow or error */ /* check for snprintf overflow or error */
if (len < 0 || (uint32) len >= bufsize) if (len < 0 || (u32) len >= bufsize)
len = bufsize - 1; len = bufsize - 1;
buf += len; buf += len;
bufsize -= len; bufsize -= len;
......
drivers/staging/brcm80211/brcmfmac/dhd.h
浏览文件 @ 66cbd3ab
...@@ -359,10 +359,10 @@ extern void dhd_os_sdtxunlock(dhd_pub_t *pub); ...@@ -359,10 +359,10 @@ extern void dhd_os_sdtxunlock(dhd_pub_t *pub);
int setScheduler(struct task_struct *p, int policy, struct sched_param *param); int setScheduler(struct task_struct *p, int policy, struct sched_param *param);
typedef struct { typedef struct {
uint32 limit; /* Expiration time (usec) */ u32 limit; /* Expiration time (usec) */
uint32 increment; /* Current expiration increment (usec) */ u32 increment; /* Current expiration increment (usec) */
uint32 elapsed; /* Current elapsed time (usec) */ u32 elapsed; /* Current elapsed time (usec) */
uint32 tick; /* O/S tick time (usec) */ u32 tick; /* O/S tick time (usec) */
} dhd_timeout_t; } dhd_timeout_t;
extern void dhd_timeout_start(dhd_timeout_t *tmo, uint usec); extern void dhd_timeout_start(dhd_timeout_t *tmo, uint usec);
...@@ -377,7 +377,7 @@ extern void wl_event_to_host_order(wl_event_msg_t *evt); ...@@ -377,7 +377,7 @@ extern void wl_event_to_host_order(wl_event_msg_t *evt);
extern void dhd_common_init(void); extern void dhd_common_init(void);
extern int dhd_add_if(struct dhd_info *dhd, int ifidx, void *handle, extern int dhd_add_if(struct dhd_info *dhd, int ifidx, void *handle,
char *name, u8 *mac_addr, uint32 flags, u8 bssidx); char *name, u8 *mac_addr, u32 flags, u8 bssidx);
extern void dhd_del_if(struct dhd_info *dhd, int ifidx); extern void dhd_del_if(struct dhd_info *dhd, int ifidx);
extern void dhd_vif_add(struct dhd_info *dhd, int ifidx, char *name); extern void dhd_vif_add(struct dhd_info *dhd, int ifidx, char *name);
......
drivers/staging/brcm80211/brcmfmac/dhd_cdc.c
浏览文件 @ 66cbd3ab
...@@ -54,7 +54,7 @@ extern int dhd_preinit_ioctls(dhd_pub_t *dhd); ...@@ -54,7 +54,7 @@ extern int dhd_preinit_ioctls(dhd_pub_t *dhd);
typedef struct dhd_prot { typedef struct dhd_prot {
u16 reqid; u16 reqid;
u8 pending; u8 pending;
uint32 lastcmd; u32 lastcmd;
u8 bus_header[BUS_HEADER_LEN]; u8 bus_header[BUS_HEADER_LEN];
cdc_ioctl_t msg; cdc_ioctl_t msg;
unsigned char buf[WLC_IOCTL_MAXLEN + ROUND_UP_MARGIN]; unsigned char buf[WLC_IOCTL_MAXLEN + ROUND_UP_MARGIN];
...@@ -78,7 +78,7 @@ static int dhdcdc_msg(dhd_pub_t *dhd) ...@@ -78,7 +78,7 @@ static int dhdcdc_msg(dhd_pub_t *dhd)
return dhd_bus_txctl(dhd->bus, (unsigned char *)&prot->msg, len); return dhd_bus_txctl(dhd->bus, (unsigned char *)&prot->msg, len);
} }
static int dhdcdc_cmplt(dhd_pub_t *dhd, uint32 id, uint32 len) static int dhdcdc_cmplt(dhd_pub_t *dhd, u32 id, u32 len)
{ {
int ret; int ret;
dhd_prot_t *prot = dhd->prot; dhd_prot_t *prot = dhd->prot;
...@@ -103,7 +103,7 @@ dhdcdc_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len) ...@@ -103,7 +103,7 @@ dhdcdc_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len)
cdc_ioctl_t *msg = &prot->msg; cdc_ioctl_t *msg = &prot->msg;
void *info; void *info;
int ret = 0, retries = 0; int ret = 0, retries = 0;
uint32 id, flags = 0; u32 id, flags = 0;
DHD_TRACE(("%s: Enter\n", __func__)); DHD_TRACE(("%s: Enter\n", __func__));
DHD_CTL(("%s: cmd %d len %d\n", __func__, cmd, len)); DHD_CTL(("%s: cmd %d len %d\n", __func__, cmd, len));
...@@ -182,7 +182,7 @@ int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len) ...@@ -182,7 +182,7 @@ int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len)
dhd_prot_t *prot = dhd->prot; dhd_prot_t *prot = dhd->prot;
cdc_ioctl_t *msg = &prot->msg; cdc_ioctl_t *msg = &prot->msg;
int ret = 0; int ret = 0;
uint32 flags, id; u32 flags, id;
DHD_TRACE(("%s: Enter\n", __func__)); DHD_TRACE(("%s: Enter\n", __func__));
DHD_CTL(("%s: cmd %d len %d\n", __func__, cmd, len)); DHD_CTL(("%s: cmd %d len %d\n", __func__, cmd, len));
......
drivers/staging/brcm80211/brcmfmac/dhd_common.c
浏览文件 @ 66cbd3ab
...@@ -30,9 +30,9 @@ char fw_path[MOD_PARAM_PATHLEN]; ...@@ -30,9 +30,9 @@ char fw_path[MOD_PARAM_PATHLEN];
char nv_path[MOD_PARAM_PATHLEN]; char nv_path[MOD_PARAM_PATHLEN];
/* Last connection success/failure status */ /* Last connection success/failure status */
uint32 dhd_conn_event; u32 dhd_conn_event;
uint32 dhd_conn_status; u32 dhd_conn_status;
uint32 dhd_conn_reason; u32 dhd_conn_reason;
#define htod32(i) i #define htod32(i) i
#define htod16(i) i #define htod16(i) i
...@@ -200,7 +200,7 @@ static int dhd_dump(dhd_pub_t *dhdp, char *buf, int buflen) ...@@ -200,7 +200,7 @@ static int dhd_dump(dhd_pub_t *dhdp, char *buf, int buflen)
} }
static int static int
dhd_doiovar(dhd_pub_t *dhd_pub, const bcm_iovar_t *vi, uint32 actionid, dhd_doiovar(dhd_pub_t *dhd_pub, const bcm_iovar_t *vi, u32 actionid,
const char *name, void *params, int plen, void *arg, int len, const char *name, void *params, int plen, void *arg, int len,
int val_size) int val_size)
{ {
...@@ -313,7 +313,7 @@ dhd_doiovar(dhd_pub_t *dhd_pub, const bcm_iovar_t *vi, uint32 actionid, ...@@ -313,7 +313,7 @@ dhd_doiovar(dhd_pub_t *dhd_pub, const bcm_iovar_t *vi, uint32 actionid,
} }
/* Store the status of a connection attempt for later retrieval by an iovar */ /* Store the status of a connection attempt for later retrieval by an iovar */
void dhd_store_conn_status(uint32 event, uint32 status, uint32 reason) void dhd_store_conn_status(u32 event, u32 status, u32 reason)
{ {
/* Do not overwrite a WLC_E_PRUNE with a WLC_E_SET_SSID /* Do not overwrite a WLC_E_PRUNE with a WLC_E_SET_SSID
* because an encryption/rsn mismatch results in both events, and * because an encryption/rsn mismatch results in both events, and
...@@ -387,7 +387,7 @@ dhd_iovar_op(dhd_pub_t *dhd_pub, const char *name, ...@@ -387,7 +387,7 @@ dhd_iovar_op(dhd_pub_t *dhd_pub, const char *name,
int bcmerror = 0; int bcmerror = 0;
int val_size; int val_size;
const bcm_iovar_t *vi = NULL; const bcm_iovar_t *vi = NULL;
uint32 actionid; u32 actionid;
DHD_TRACE(("%s: Enter\n", __func__)); DHD_TRACE(("%s: Enter\n", __func__));
...@@ -750,9 +750,9 @@ static void wl_show_host_event(wl_event_msg_t *event, void *event_data) ...@@ -750,9 +750,9 @@ static void wl_show_host_event(wl_event_msg_t *event, void *event_data)
case WLC_E_TRACE: case WLC_E_TRACE:
{ {
static uint32 seqnum_prev; static u32 seqnum_prev;
msgtrace_hdr_t hdr; msgtrace_hdr_t hdr;
uint32 nblost; u32 nblost;
char *s, *p; char *s, *p;
buf = (unsigned char *) event_data; buf = (unsigned char *) event_data;
...@@ -835,7 +835,7 @@ wl_host_event(struct dhd_info *dhd, int *ifidx, void *pktdata, ...@@ -835,7 +835,7 @@ wl_host_event(struct dhd_info *dhd, int *ifidx, void *pktdata,
/* check whether packet is a BRCM event pkt */ /* check whether packet is a BRCM event pkt */
bcm_event_t *pvt_data = (bcm_event_t *) pktdata; bcm_event_t *pvt_data = (bcm_event_t *) pktdata;
char *event_data; char *event_data;
uint32 type, status; u32 type, status;
u16 flags; u16 flags;
int evlen; int evlen;
...@@ -912,7 +912,7 @@ wl_host_event(struct dhd_info *dhd, int *ifidx, void *pktdata, ...@@ -912,7 +912,7 @@ wl_host_event(struct dhd_info *dhd, int *ifidx, void *pktdata,
/* put it back to WLC_E_NDIS_LINK */ /* put it back to WLC_E_NDIS_LINK */
if (type == WLC_E_NDIS_LINK) { if (type == WLC_E_NDIS_LINK) {
uint32 temp; u32 temp;
temp = ntoh32_ua((void *)&event->event_type); temp = ntoh32_ua((void *)&event->event_type);
DHD_TRACE(("Converted to WLC_E_LINK type %d\n", temp)); DHD_TRACE(("Converted to WLC_E_LINK type %d\n", temp));
...@@ -1072,8 +1072,8 @@ void dhd_pktfilter_offload_set(dhd_pub_t *dhd, char *arg) ...@@ -1072,8 +1072,8 @@ void dhd_pktfilter_offload_set(dhd_pub_t *dhd, char *arg)
int buf_len; int buf_len;
int str_len; int str_len;
int rc; int rc;
uint32 mask_size; u32 mask_size;
uint32 pattern_size; u32 pattern_size;
char *argv[8], *buf = 0; char *argv[8], *buf = 0;
int i = 0; int i = 0;
char *arg_save = 0, *arg_org = 0; char *arg_save = 0, *arg_org = 0;
...@@ -1242,8 +1242,8 @@ int dhd_preinit_ioctls(dhd_pub_t *dhd) ...@@ -1242,8 +1242,8 @@ int dhd_preinit_ioctls(dhd_pub_t *dhd)
uint up = 0; uint up = 0;
char buf[128], *ptr; char buf[128], *ptr;
uint power_mode = PM_FAST; uint power_mode = PM_FAST;
uint32 dongle_align = DHD_SDALIGN; u32 dongle_align = DHD_SDALIGN;
uint32 glom = 0; u32 glom = 0;
uint bcn_timeout = 3; uint bcn_timeout = 3;
int scan_assoc_time = 40; int scan_assoc_time = 40;
int scan_unassoc_time = 40; int scan_unassoc_time = 40;
......
drivers/staging/brcm80211/brcmfmac/dhd_linux.c
浏览文件 @ 66cbd3ab
...@@ -425,8 +425,8 @@ extern int dhd_wait_pend8021x(struct net_device *dev); ...@@ -425,8 +425,8 @@ extern int dhd_wait_pend8021x(struct net_device *dev);
#ifndef BDC #ifndef BDC
#error TOE requires BDC #error TOE requires BDC
#endif /* !BDC */ #endif /* !BDC */
static int dhd_toe_get(dhd_info_t *dhd, int idx, uint32 *toe_ol); static int dhd_toe_get(dhd_info_t *dhd, int idx, u32 *toe_ol);
static int dhd_toe_set(dhd_info_t *dhd, int idx, uint32 toe_ol); static int dhd_toe_set(dhd_info_t *dhd, int idx, u32 toe_ol);
#endif /* TOE */ #endif /* TOE */
static int dhd_wl_host_event(dhd_info_t *dhd, int *ifidx, void *pktdata, static int dhd_wl_host_event(dhd_info_t *dhd, int *ifidx, void *pktdata,
...@@ -712,7 +712,7 @@ static void _dhd_set_multicast_list(dhd_info_t *dhd, int ifidx) ...@@ -712,7 +712,7 @@ static void _dhd_set_multicast_list(dhd_info_t *dhd, int ifidx)
{ {
struct net_device *dev; struct net_device *dev;
struct netdev_hw_addr *ha; struct netdev_hw_addr *ha;
uint32 allmulti, cnt; u32 allmulti, cnt;
wl_ioctl_t ioc; wl_ioctl_t ioc;
char *buf, *bufp; char *buf, *bufp;
...@@ -1434,7 +1434,7 @@ void dhd_sched_dpc(dhd_pub_t *dhdp) ...@@ -1434,7 +1434,7 @@ void dhd_sched_dpc(dhd_pub_t *dhdp)
#ifdef TOE #ifdef TOE
/* Retrieve current toe component enables, which are kept /* Retrieve current toe component enables, which are kept
as a bitmap in toe_ol iovar */ as a bitmap in toe_ol iovar */
static int dhd_toe_get(dhd_info_t *dhd, int ifidx, uint32 *toe_ol) static int dhd_toe_get(dhd_info_t *dhd, int ifidx, u32 *toe_ol)
{ {
wl_ioctl_t ioc; wl_ioctl_t ioc;
char buf[32]; char buf[32];
...@@ -1462,13 +1462,13 @@ static int dhd_toe_get(dhd_info_t *dhd, int ifidx, uint32 *toe_ol) ...@@ -1462,13 +1462,13 @@ static int dhd_toe_get(dhd_info_t *dhd, int ifidx, uint32 *toe_ol)
return ret; return ret;
} }
memcpy(toe_ol, buf, sizeof(uint32)); memcpy(toe_ol, buf, sizeof(u32));
return 0; return 0;
} }
/* Set current toe component enables in toe_ol iovar, /* Set current toe component enables in toe_ol iovar,
and set toe global enable iovar */ and set toe global enable iovar */
static int dhd_toe_set(dhd_info_t *dhd, int ifidx, uint32 toe_ol) static int dhd_toe_set(dhd_info_t *dhd, int ifidx, u32 toe_ol)
{ {
wl_ioctl_t ioc; wl_ioctl_t ioc;
char buf[32]; char buf[32];
...@@ -1484,7 +1484,7 @@ static int dhd_toe_set(dhd_info_t *dhd, int ifidx, uint32 toe_ol) ...@@ -1484,7 +1484,7 @@ static int dhd_toe_set(dhd_info_t *dhd, int ifidx, uint32 toe_ol)
/* Set toe_ol as requested */ /* Set toe_ol as requested */
strcpy(buf, "toe_ol"); strcpy(buf, "toe_ol");
memcpy(&buf[sizeof("toe_ol")], &toe_ol, sizeof(uint32)); memcpy(&buf[sizeof("toe_ol")], &toe_ol, sizeof(u32));
ret = dhd_prot_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len); ret = dhd_prot_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len);
if (ret < 0) { if (ret < 0) {
...@@ -1498,7 +1498,7 @@ static int dhd_toe_set(dhd_info_t *dhd, int ifidx, uint32 toe_ol) ...@@ -1498,7 +1498,7 @@ static int dhd_toe_set(dhd_info_t *dhd, int ifidx, uint32 toe_ol)
toe = (toe_ol != 0); toe = (toe_ol != 0);
strcpy(buf, "toe"); strcpy(buf, "toe");
memcpy(&buf[sizeof("toe")], &toe, sizeof(uint32)); memcpy(&buf[sizeof("toe")], &toe, sizeof(u32));
ret = dhd_prot_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len); ret = dhd_prot_ioctl(&dhd->pub, ifidx, &ioc, ioc.buf, ioc.len);
if (ret < 0) { if (ret < 0) {
...@@ -1530,17 +1530,17 @@ static int dhd_ethtool(dhd_info_t *dhd, void *uaddr) ...@@ -1530,17 +1530,17 @@ static int dhd_ethtool(dhd_info_t *dhd, void *uaddr)
{ {
struct ethtool_drvinfo info; struct ethtool_drvinfo info;
char drvname[sizeof(info.driver)]; char drvname[sizeof(info.driver)];
uint32 cmd; u32 cmd;
#ifdef TOE #ifdef TOE
struct ethtool_value edata; struct ethtool_value edata;
uint32 toe_cmpnt, csum_dir; u32 toe_cmpnt, csum_dir;
int ret; int ret;
#endif #endif
DHD_TRACE(("%s: Enter\n", __func__)); DHD_TRACE(("%s: Enter\n", __func__));
/* all ethtool calls start with a cmd word */ /* all ethtool calls start with a cmd word */
if (copy_from_user(&cmd, uaddr, sizeof(uint32))) if (copy_from_user(&cmd, uaddr, sizeof(u32)))
return -EFAULT; return -EFAULT;
switch (cmd) { switch (cmd) {
...@@ -1794,7 +1794,7 @@ static int dhd_open(struct net_device *net) ...@@ -1794,7 +1794,7 @@ static int dhd_open(struct net_device *net)
{ {
dhd_info_t *dhd = *(dhd_info_t **) netdev_priv(net); dhd_info_t *dhd = *(dhd_info_t **) netdev_priv(net);
#ifdef TOE #ifdef TOE
uint32 toe_ol; u32 toe_ol;
#endif #endif
int ifidx = dhd_net2idx(dhd, net); int ifidx = dhd_net2idx(dhd, net);
int32 ret = 0; int32 ret = 0;
...@@ -1854,7 +1854,7 @@ void dhd_osl_detach(osl_t *osh) ...@@ -1854,7 +1854,7 @@ void dhd_osl_detach(osl_t *osh)
int int
dhd_add_if(dhd_info_t *dhd, int ifidx, void *handle, char *name, dhd_add_if(dhd_info_t *dhd, int ifidx, void *handle, char *name,
u8 *mac_addr, uint32 flags, u8 bssidx) u8 *mac_addr, u32 flags, u8 bssidx)
{ {
dhd_if_t *ifp; dhd_if_t *ifp;
......
drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
浏览文件 @ 66cbd3ab
...@@ -167,18 +167,18 @@ typedef struct dhd_bus { ...@@ -167,18 +167,18 @@ typedef struct dhd_bus {
si_t *sih; /* Handle for SI calls */ si_t *sih; /* Handle for SI calls */
char *vars; /* Variables (from CIS and/or other) */ char *vars; /* Variables (from CIS and/or other) */
uint varsz; /* Size of variables buffer */ uint varsz; /* Size of variables buffer */
uint32 sbaddr; /* Current SB window pointer (-1, invalid) */ u32 sbaddr; /* Current SB window pointer (-1, invalid) */
sdpcmd_regs_t *regs; /* Registers for SDIO core */ sdpcmd_regs_t *regs; /* Registers for SDIO core */
uint sdpcmrev; /* SDIO core revision */ uint sdpcmrev; /* SDIO core revision */
uint armrev; /* CPU core revision */ uint armrev; /* CPU core revision */
uint ramrev; /* SOCRAM core revision */ uint ramrev; /* SOCRAM core revision */
uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */ u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */ u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
uint32 bus; /* gSPI or SDIO bus */ u32 bus; /* gSPI or SDIO bus */
uint32 hostintmask; /* Copy of Host Interrupt Mask */ u32 hostintmask; /* Copy of Host Interrupt Mask */
uint32 intstatus; /* Intstatus bits (events) pending */ u32 intstatus; /* Intstatus bits (events) pending */
bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */ bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
bool fcstate; /* State of dongle flow-control */ bool fcstate; /* State of dongle flow-control */
...@@ -295,7 +295,7 @@ typedef struct dhd_bus { ...@@ -295,7 +295,7 @@ typedef struct dhd_bus {
uint f1regdata; /* Number of f1 register accesses */ uint f1regdata; /* Number of f1 register accesses */
u8 *ctrl_frame_buf; u8 *ctrl_frame_buf;
uint32 ctrl_frame_len; u32 ctrl_frame_len;
bool ctrl_frame_stat; bool ctrl_frame_stat;
} dhd_bus_t; } dhd_bus_t;
...@@ -442,10 +442,10 @@ static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t * osh); ...@@ -442,10 +442,10 @@ static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t * osh);
static uint process_nvram_vars(char *varbuf, uint len); static uint process_nvram_vars(char *varbuf, uint len);
static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size); static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
uint flags, u8 *buf, uint nbytes, void *pkt, uint flags, u8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle); bcmsdh_cmplt_fn_t complete, void *handle);
static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
uint flags, u8 *buf, uint nbytes, void *pkt, uint flags, u8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle); bcmsdh_cmplt_fn_t complete, void *handle);
...@@ -470,7 +470,7 @@ static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size) ...@@ -470,7 +470,7 @@ static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
bus->ramsize = dhd_dongle_memsize; bus->ramsize = dhd_dongle_memsize;
} }
static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, uint32 address) static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
{ {
int err = 0; int err = 0;
bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW, bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
...@@ -519,7 +519,7 @@ static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok) ...@@ -519,7 +519,7 @@ static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID) if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
&& (bus->sih->buscorerev == 9))) { && (bus->sih->buscorerev == 9))) {
uint32 dummy, retries; u32 dummy, retries;
R_SDREG(dummy, &bus->regs->clockctlstatus, retries); R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
} }
...@@ -905,7 +905,7 @@ static int dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt) ...@@ -905,7 +905,7 @@ static int dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt)
osl_t *osh; osl_t *osh;
u8 *frame; u8 *frame;
u16 len, pad = 0; u16 len, pad = 0;
uint32 swheader; u32 swheader;
uint retries = 0; uint retries = 0;
bcmsdh_info_t *sdh; bcmsdh_info_t *sdh;
void *new; void *new;
...@@ -1162,7 +1162,7 @@ int dhd_bus_txdata(struct dhd_bus *bus, void *pkt) ...@@ -1162,7 +1162,7 @@ int dhd_bus_txdata(struct dhd_bus *bus, void *pkt)
static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes) static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
{ {
void *pkt; void *pkt;
uint32 intstatus = 0; u32 intstatus = 0;
uint retries = 0; uint retries = 0;
int ret = 0, prec_out; int ret = 0, prec_out;
uint cnt = 0; uint cnt = 0;
...@@ -1223,7 +1223,7 @@ int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen) ...@@ -1223,7 +1223,7 @@ int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
{ {
u8 *frame; u8 *frame;
u16 len; u16 len;
uint32 swheader; u32 swheader;
uint retries = 0; uint retries = 0;
bcmsdh_info_t *sdh = bus->sdh; bcmsdh_info_t *sdh = bus->sdh;
u8 doff = 0; u8 doff = 0;
...@@ -1692,11 +1692,11 @@ static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg) ...@@ -1692,11 +1692,11 @@ static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
#endif /* SDTEST */ #endif /* SDTEST */
static int static int
dhdsdio_membytes(dhd_bus_t *bus, bool write, uint32 address, u8 *data, dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
uint size) uint size)
{ {
int bcmerror = 0; int bcmerror = 0;
uint32 sdaddr; u32 sdaddr;
uint dsize; uint dsize;
/* Determine initial transfer parameters */ /* Determine initial transfer parameters */
...@@ -1754,7 +1754,7 @@ dhdsdio_membytes(dhd_bus_t *bus, bool write, uint32 address, u8 *data, ...@@ -1754,7 +1754,7 @@ dhdsdio_membytes(dhd_bus_t *bus, bool write, uint32 address, u8 *data,
#ifdef DHD_DEBUG #ifdef DHD_DEBUG
static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh) static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
{ {
uint32 addr; u32 addr;
int rv; int rv;
/* Read last word in memory to determine address of /* Read last word in memory to determine address of
...@@ -1987,7 +1987,7 @@ static int dhdsdio_readconsole(dhd_bus_t *bus) ...@@ -1987,7 +1987,7 @@ static int dhdsdio_readconsole(dhd_bus_t *bus)
{ {
dhd_console_t *c = &bus->console; dhd_console_t *c = &bus->console;
u8 line[CONSOLE_LINE_MAX], ch; u8 line[CONSOLE_LINE_MAX], ch;
uint32 n, idx, addr; u32 n, idx, addr;
int rv; int rv;
/* Don't do anything until FWREADY updates console address */ /* Don't do anything until FWREADY updates console address */
...@@ -2095,7 +2095,7 @@ int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len) ...@@ -2095,7 +2095,7 @@ int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
} }
static int static int
dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
const char *name, void *params, int plen, void *arg, int len, const char *name, void *params, int plen, void *arg, int len,
int val_size) int val_size)
{ {
...@@ -2208,7 +2208,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, ...@@ -2208,7 +2208,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
case IOV_SVAL(IOV_MEMBYTES): case IOV_SVAL(IOV_MEMBYTES):
case IOV_GVAL(IOV_MEMBYTES): case IOV_GVAL(IOV_MEMBYTES):
{ {
uint32 address; u32 address;
uint size, dsize; uint size, dsize;
u8 *data; u8 *data;
...@@ -2216,7 +2216,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, ...@@ -2216,7 +2216,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
ASSERT(plen >= 2 * sizeof(int)); ASSERT(plen >= 2 * sizeof(int));
address = (uint32) int_val; address = (u32) int_val;
bcopy((char *)params + sizeof(int_val), &int_val, bcopy((char *)params + sizeof(int_val), &int_val,
sizeof(int_val)); sizeof(int_val));
size = (uint) int_val; size = (uint) int_val;
...@@ -2332,7 +2332,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, ...@@ -2332,7 +2332,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
case IOV_GVAL(IOV_SDREG): case IOV_GVAL(IOV_SDREG):
{ {
sdreg_t *sd_ptr; sdreg_t *sd_ptr;
uint32 addr, size; u32 addr, size;
sd_ptr = (sdreg_t *) params; sd_ptr = (sdreg_t *) params;
...@@ -2348,7 +2348,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, ...@@ -2348,7 +2348,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
case IOV_SVAL(IOV_SDREG): case IOV_SVAL(IOV_SDREG):
{ {
sdreg_t *sd_ptr; sdreg_t *sd_ptr;
uint32 addr, size; u32 addr, size;
sd_ptr = (sdreg_t *) params; sd_ptr = (sdreg_t *) params;
...@@ -2365,7 +2365,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, ...@@ -2365,7 +2365,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
case IOV_GVAL(IOV_SBREG): case IOV_GVAL(IOV_SBREG):
{ {
sdreg_t sdreg; sdreg_t sdreg;
uint32 addr, size; u32 addr, size;
bcopy(params, &sdreg, sizeof(sdreg)); bcopy(params, &sdreg, sizeof(sdreg));
...@@ -2381,7 +2381,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, ...@@ -2381,7 +2381,7 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
case IOV_SVAL(IOV_SBREG): case IOV_SVAL(IOV_SBREG):
{ {
sdreg_t sdreg; sdreg_t sdreg;
uint32 addr, size; u32 addr, size;
bcopy(params, &sdreg, sizeof(sdreg)); bcopy(params, &sdreg, sizeof(sdreg));
...@@ -2512,10 +2512,10 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, ...@@ -2512,10 +2512,10 @@ dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid,
static int dhdsdio_write_vars(dhd_bus_t *bus) static int dhdsdio_write_vars(dhd_bus_t *bus)
{ {
int bcmerror = 0; int bcmerror = 0;
uint32 varsize; u32 varsize;
uint32 varaddr; u32 varaddr;
u8 *vbuffer; u8 *vbuffer;
uint32 varsizew; u32 varsizew;
#ifdef DHD_DEBUG #ifdef DHD_DEBUG
char *nvram_ularray; char *nvram_ularray;
#endif /* DHD_DEBUG */ #endif /* DHD_DEBUG */
...@@ -2639,7 +2639,7 @@ static int dhdsdio_download_state(dhd_bus_t *bus, bool enter) ...@@ -2639,7 +2639,7 @@ static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
/* Clear the top bit of memory */ /* Clear the top bit of memory */
if (bus->ramsize) { if (bus->ramsize) {
uint32 zeros = 0; u32 zeros = 0;
dhdsdio_membytes(bus, TRUE, bus->ramsize - 4, dhdsdio_membytes(bus, TRUE, bus->ramsize - 4,
(u8 *)&zeros, 4); (u8 *)&zeros, 4);
} }
...@@ -2710,7 +2710,7 @@ dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name, ...@@ -2710,7 +2710,7 @@ dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
const bcm_iovar_t *vi = NULL; const bcm_iovar_t *vi = NULL;
int bcmerror = 0; int bcmerror = 0;
int val_size; int val_size;
uint32 actionid; u32 actionid;
DHD_TRACE(("%s: Enter\n", __func__)); DHD_TRACE(("%s: Enter\n", __func__));
...@@ -2823,7 +2823,7 @@ dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name, ...@@ -2823,7 +2823,7 @@ dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex) void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
{ {
osl_t *osh = bus->dhd->osh; osl_t *osh = bus->dhd->osh;
uint32 local_hostintmask; u32 local_hostintmask;
u8 saveclk; u8 saveclk;
uint retries; uint retries;
int err; int err;
...@@ -4208,11 +4208,11 @@ static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished) ...@@ -4208,11 +4208,11 @@ static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
return rxcount; return rxcount;
} }
static uint32 dhdsdio_hostmail(dhd_bus_t *bus) static u32 dhdsdio_hostmail(dhd_bus_t *bus)
{ {
sdpcmd_regs_t *regs = bus->regs; sdpcmd_regs_t *regs = bus->regs;
uint32 intstatus = 0; u32 intstatus = 0;
uint32 hmb_data; u32 hmb_data;
u8 fcbits; u8 fcbits;
uint retries = 0; uint retries = 0;
...@@ -4286,7 +4286,7 @@ bool dhdsdio_dpc(dhd_bus_t *bus) ...@@ -4286,7 +4286,7 @@ bool dhdsdio_dpc(dhd_bus_t *bus)
{ {
bcmsdh_info_t *sdh = bus->sdh; bcmsdh_info_t *sdh = bus->sdh;
sdpcmd_regs_t *regs = bus->regs; sdpcmd_regs_t *regs = bus->regs;
uint32 intstatus, newstatus = 0; u32 intstatus, newstatus = 0;
uint retries = 0; uint retries = 0;
uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */ uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
uint txlimit = dhd_txbound; /* Tx frames to send before resched */ uint txlimit = dhd_txbound; /* Tx frames to send before resched */
...@@ -4460,7 +4460,7 @@ bool dhdsdio_dpc(dhd_bus_t *bus) ...@@ -4460,7 +4460,7 @@ bool dhdsdio_dpc(dhd_bus_t *bus)
ret = ret =
dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
F2SYNC, (u8 *) bus->ctrl_frame_buf, F2SYNC, (u8 *) bus->ctrl_frame_buf,
(uint32) bus->ctrl_frame_len, NULL, (u32) bus->ctrl_frame_len, NULL,
NULL, NULL); NULL, NULL);
ASSERT(ret != BCME_PENDING); ASSERT(ret != BCME_PENDING);
...@@ -4875,7 +4875,7 @@ extern bool dhd_bus_watchdog(dhd_pub_t *dhdp) ...@@ -4875,7 +4875,7 @@ extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
/* Poll period: check device if appropriate. */ /* Poll period: check device if appropriate. */
if (bus->poll && (++bus->polltick >= bus->pollrate)) { if (bus->poll && (++bus->polltick >= bus->pollrate)) {
uint32 intstatus = 0; u32 intstatus = 0;
/* Reset poll tick */ /* Reset poll tick */
bus->polltick = 0; bus->polltick = 0;
...@@ -4957,7 +4957,7 @@ extern bool dhd_bus_watchdog(dhd_pub_t *dhdp) ...@@ -4957,7 +4957,7 @@ extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen) extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
{ {
dhd_bus_t *bus = dhdp->bus; dhd_bus_t *bus = dhdp->bus;
uint32 addr, val; u32 addr, val;
int rv; int rv;
void *pkt; void *pkt;
...@@ -5765,9 +5765,9 @@ static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path) ...@@ -5765,9 +5765,9 @@ static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
__func__, MEMBLOCK)); __func__, MEMBLOCK));
goto err; goto err;
} }
if ((uint32) (uintptr) memblock % DHD_SDALIGN) if ((u32) (uintptr) memblock % DHD_SDALIGN)
memptr += memptr +=
(DHD_SDALIGN - ((uint32) (uintptr) memblock % DHD_SDALIGN)); (DHD_SDALIGN - ((u32) (uintptr) memblock % DHD_SDALIGN));
/* Download image */ /* Download image */
while ((len = while ((len =
...@@ -6010,7 +6010,7 @@ static int _dhdsdio_download_firmware(struct dhd_bus *bus) ...@@ -6010,7 +6010,7 @@ static int _dhdsdio_download_firmware(struct dhd_bus *bus)
} }
static int static int
dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
u8 *buf, uint nbytes, void *pkt, u8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle) bcmsdh_cmplt_fn_t complete, void *handle)
{ {
...@@ -6024,7 +6024,7 @@ dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, ...@@ -6024,7 +6024,7 @@ dhd_bcmsdh_recv_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags,
} }
static int static int
dhd_bcmsdh_send_buf(dhd_bus_t *bus, uint32 addr, uint fn, uint flags, dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
u8 *buf, uint nbytes, void *pkt, u8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle) bcmsdh_cmplt_fn_t complete, void *handle)
{ {
...@@ -6091,7 +6091,7 @@ int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag) ...@@ -6091,7 +6091,7 @@ int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
/* Attempt to re-attach & download */ /* Attempt to re-attach & download */
if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh, if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
(uint32 *) SI_ENUM_BASE, (u32 *) SI_ENUM_BASE,
bus->cl_devid)) { bus->cl_devid)) {
/* Attempt to download binary to the dongle */ /* Attempt to download binary to the dongle */
if (dhdsdio_probe_init if (dhdsdio_probe_init
......
drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
浏览文件 @ 66cbd3ab
...@@ -50,7 +50,7 @@ ...@@ -50,7 +50,7 @@
static struct sdio_func *cfg80211_sdio_func; static struct sdio_func *cfg80211_sdio_func;
static struct wl_dev *wl_cfg80211_dev; static struct wl_dev *wl_cfg80211_dev;
uint32 wl_dbg_level = WL_DBG_ERR | WL_DBG_INFO; u32 wl_dbg_level = WL_DBG_ERR | WL_DBG_INFO;
#define WL_4329_FW_FILE "brcm/bcm4329-fullmac-4-218-248-5.bin" #define WL_4329_FW_FILE "brcm/bcm4329-fullmac-4-218-248-5.bin"
#define WL_4329_NVRAM_FILE "brcm/bcm4329-fullmac-4-218-248-5.txt" #define WL_4329_NVRAM_FILE "brcm/bcm4329-fullmac-4-218-248-5.txt"
...@@ -60,14 +60,14 @@ uint32 wl_dbg_level = WL_DBG_ERR | WL_DBG_INFO; ...@@ -60,14 +60,14 @@ uint32 wl_dbg_level = WL_DBG_ERR | WL_DBG_INFO;
*/ */
static int32 wl_cfg80211_change_iface(struct wiphy *wiphy, static int32 wl_cfg80211_change_iface(struct wiphy *wiphy,
struct net_device *ndev, struct net_device *ndev,
enum nl80211_iftype type, uint32 *flags, enum nl80211_iftype type, u32 *flags,
struct vif_params *params); struct vif_params *params);
static int32 __wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev, static int32 __wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
struct cfg80211_scan_request *request, struct cfg80211_scan_request *request,
struct cfg80211_ssid *this_ssid); struct cfg80211_ssid *this_ssid);
static int32 wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev, static int32 wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
struct cfg80211_scan_request *request); struct cfg80211_scan_request *request);
static int32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, uint32 changed); static int32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed);
static int32 wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev, static int32 wl_cfg80211_join_ibss(struct wiphy *wiphy, struct net_device *dev,
struct cfg80211_ibss_params *params); struct cfg80211_ibss_params *params);
static int32 wl_cfg80211_leave_ibss(struct wiphy *wiphy, static int32 wl_cfg80211_leave_ibss(struct wiphy *wiphy,
...@@ -129,7 +129,7 @@ static void wl_unlock_eq(struct wl_priv *wl); ...@@ -129,7 +129,7 @@ static void wl_unlock_eq(struct wl_priv *wl);
static void wl_init_eq_lock(struct wl_priv *wl); static void wl_init_eq_lock(struct wl_priv *wl);
static void wl_init_eloop_handler(struct wl_event_loop *el); static void wl_init_eloop_handler(struct wl_event_loop *el);
static struct wl_event_q *wl_deq_event(struct wl_priv *wl); static struct wl_event_q *wl_deq_event(struct wl_priv *wl);
static int32 wl_enq_event(struct wl_priv *wl, uint32 type, static int32 wl_enq_event(struct wl_priv *wl, u32 type,
const wl_event_msg_t *msg, void *data); const wl_event_msg_t *msg, void *data);
static void wl_put_event(struct wl_event_q *e); static void wl_put_event(struct wl_event_q *e);
static void wl_wakeup_event(struct wl_priv *wl); static void wl_wakeup_event(struct wl_priv *wl);
...@@ -165,15 +165,15 @@ static __used int32 wl_dev_bufvar_set(struct net_device *dev, s8 *name, ...@@ -165,15 +165,15 @@ static __used int32 wl_dev_bufvar_set(struct net_device *dev, s8 *name,
static int32 wl_dev_intvar_set(struct net_device *dev, s8 *name, int32 val); static int32 wl_dev_intvar_set(struct net_device *dev, s8 *name, int32 val);
static int32 wl_dev_intvar_get(struct net_device *dev, s8 *name, static int32 wl_dev_intvar_get(struct net_device *dev, s8 *name,
int32 *retval); int32 *retval);
static int32 wl_dev_ioctl(struct net_device *dev, uint32 cmd, void *arg, static int32 wl_dev_ioctl(struct net_device *dev, u32 cmd, void *arg,
uint32 len); u32 len);
/* /*
** cfg80211 set_wiphy_params utilities ** cfg80211 set_wiphy_params utilities
*/ */
static int32 wl_set_frag(struct net_device *dev, uint32 frag_threshold); static int32 wl_set_frag(struct net_device *dev, u32 frag_threshold);
static int32 wl_set_rts(struct net_device *dev, uint32 frag_threshold); static int32 wl_set_rts(struct net_device *dev, u32 frag_threshold);
static int32 wl_set_retry(struct net_device *dev, uint32 retry, bool l); static int32 wl_set_retry(struct net_device *dev, u32 retry, bool l);
/* /*
** wl profile utilities ** wl profile utilities
...@@ -205,7 +205,7 @@ static void wl_rst_ie(struct wl_priv *wl); ...@@ -205,7 +205,7 @@ static void wl_rst_ie(struct wl_priv *wl);
static int32 wl_add_ie(struct wl_priv *wl, u8 t, u8 l, u8 *v); static int32 wl_add_ie(struct wl_priv *wl, u8 t, u8 l, u8 *v);
static int32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, u16 ie_size); static int32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, u16 ie_size);
static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size); static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size);
static uint32 wl_get_ielen(struct wl_priv *wl); static u32 wl_get_ielen(struct wl_priv *wl);
static int32 wl_mode_to_nl80211_iftype(int32 mode); static int32 wl_mode_to_nl80211_iftype(int32 mode);
...@@ -233,7 +233,7 @@ static void swap_key_to_BE(struct wl_wsec_key *key); ...@@ -233,7 +233,7 @@ static void swap_key_to_BE(struct wl_wsec_key *key);
static int32 wl_init_priv_mem(struct wl_priv *wl); static int32 wl_init_priv_mem(struct wl_priv *wl);
static void wl_deinit_priv_mem(struct wl_priv *wl); static void wl_deinit_priv_mem(struct wl_priv *wl);
static void wl_delay(uint32 ms); static void wl_delay(u32 ms);
/* /*
** store/restore cfg80211 instance data ** store/restore cfg80211 instance data
...@@ -267,19 +267,19 @@ static void wl_init_conf(struct wl_conf *conf); ...@@ -267,19 +267,19 @@ static void wl_init_conf(struct wl_conf *conf);
#ifndef EMBEDDED_PLATFORM #ifndef EMBEDDED_PLATFORM
static int32 wl_dongle_mode(struct net_device *ndev, int32 iftype); static int32 wl_dongle_mode(struct net_device *ndev, int32 iftype);
static int32 wl_dongle_country(struct net_device *ndev, u8 ccode); static int32 wl_dongle_country(struct net_device *ndev, u8 ccode);
static int32 wl_dongle_up(struct net_device *ndev, uint32 up); static int32 wl_dongle_up(struct net_device *ndev, u32 up);
static int32 wl_dongle_power(struct net_device *ndev, uint32 power_mode); static int32 wl_dongle_power(struct net_device *ndev, u32 power_mode);
static int32 wl_dongle_glom(struct net_device *ndev, uint32 glom, static int32 wl_dongle_glom(struct net_device *ndev, u32 glom,
uint32 dongle_align); u32 dongle_align);
static int32 wl_dongle_roam(struct net_device *ndev, uint32 roamvar, static int32 wl_dongle_roam(struct net_device *ndev, u32 roamvar,
uint32 bcn_timeout); u32 bcn_timeout);
static int32 wl_dongle_eventmsg(struct net_device *ndev); static int32 wl_dongle_eventmsg(struct net_device *ndev);
static int32 wl_dongle_scantime(struct net_device *ndev, int32 scan_assoc_time, static int32 wl_dongle_scantime(struct net_device *ndev, int32 scan_assoc_time,
int32 scan_unassoc_time); int32 scan_unassoc_time);
static int32 wl_dongle_offload(struct net_device *ndev, int32 arpoe, static int32 wl_dongle_offload(struct net_device *ndev, int32 arpoe,
int32 arp_ol); int32 arp_ol);
static int32 wl_pattern_atoh(s8 *src, s8 *dst); static int32 wl_pattern_atoh(s8 *src, s8 *dst);
static int32 wl_dongle_filter(struct net_device *ndev, uint32 filter_mode); static int32 wl_dongle_filter(struct net_device *ndev, u32 filter_mode);
static int32 wl_update_wiphybands(struct wl_priv *wl); static int32 wl_update_wiphybands(struct wl_priv *wl);
#endif /* !EMBEDDED_PLATFORM */ #endif /* !EMBEDDED_PLATFORM */
static int32 wl_config_dongle(struct wl_priv *wl, bool need_lock); static int32 wl_config_dongle(struct wl_priv *wl, bool need_lock);
...@@ -302,7 +302,7 @@ static int32 wl_run_iscan(struct wl_iscan_ctrl *iscan, struct wlc_ssid *ssid, ...@@ -302,7 +302,7 @@ static int32 wl_run_iscan(struct wl_iscan_ctrl *iscan, struct wlc_ssid *ssid,
static int32 wl_do_iscan(struct wl_priv *wl); static int32 wl_do_iscan(struct wl_priv *wl);
static int32 wl_wakeup_iscan(struct wl_iscan_ctrl *iscan); static int32 wl_wakeup_iscan(struct wl_iscan_ctrl *iscan);
static int32 wl_invoke_iscan(struct wl_priv *wl); static int32 wl_invoke_iscan(struct wl_priv *wl);
static int32 wl_get_iscan_results(struct wl_iscan_ctrl *iscan, uint32 *status, static int32 wl_get_iscan_results(struct wl_iscan_ctrl *iscan, u32 *status,
struct wl_scan_results **bss_list); struct wl_scan_results **bss_list);
static void wl_notify_iscan_complete(struct wl_iscan_ctrl *iscan, bool aborted); static void wl_notify_iscan_complete(struct wl_iscan_ctrl *iscan, bool aborted);
static void wl_init_iscan_eloop(struct wl_iscan_eloop *el); static void wl_init_iscan_eloop(struct wl_iscan_eloop *el);
...@@ -319,7 +319,7 @@ static void wl_init_fw(struct wl_fw_ctrl *fw); ...@@ -319,7 +319,7 @@ static void wl_init_fw(struct wl_fw_ctrl *fw);
/* /*
* find most significant bit set * find most significant bit set
*/ */
static __used uint32 wl_find_msb(u16 bit16); static __used u32 wl_find_msb(u16 bit16);
/* /*
* update pmklist to dongle * update pmklist to dongle
...@@ -540,7 +540,7 @@ static struct ieee80211_supported_band __wl_band_5ghz_n = { ...@@ -540,7 +540,7 @@ static struct ieee80211_supported_band __wl_band_5ghz_n = {
.n_bitrates = wl_a_rates_size, .n_bitrates = wl_a_rates_size,
}; };
static const uint32 __wl_cipher_suites[] = { static const u32 __wl_cipher_suites[] = {
WLAN_CIPHER_SUITE_WEP40, WLAN_CIPHER_SUITE_WEP40,
WLAN_CIPHER_SUITE_WEP104, WLAN_CIPHER_SUITE_WEP104,
WLAN_CIPHER_SUITE_TKIP, WLAN_CIPHER_SUITE_TKIP,
...@@ -571,7 +571,7 @@ static void swap_key_to_BE(struct wl_wsec_key *key) ...@@ -571,7 +571,7 @@ static void swap_key_to_BE(struct wl_wsec_key *key)
} }
static int32 static int32
wl_dev_ioctl(struct net_device *dev, uint32 cmd, void *arg, uint32 len) wl_dev_ioctl(struct net_device *dev, u32 cmd, void *arg, u32 len)
{ {
struct ifreq ifr; struct ifreq ifr;
struct wl_ioctl ioc; struct wl_ioctl ioc;
...@@ -595,7 +595,7 @@ wl_dev_ioctl(struct net_device *dev, uint32 cmd, void *arg, uint32 len) ...@@ -595,7 +595,7 @@ wl_dev_ioctl(struct net_device *dev, uint32 cmd, void *arg, uint32 len)
static int32 static int32
wl_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev, wl_cfg80211_change_iface(struct wiphy *wiphy, struct net_device *ndev,
enum nl80211_iftype type, uint32 *flags, enum nl80211_iftype type, u32 *flags,
struct vif_params *params) struct vif_params *params)
{ {
struct wl_priv *wl = wiphy_to_wl(wiphy); struct wl_priv *wl = wiphy_to_wl(wiphy);
...@@ -866,7 +866,7 @@ wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev, ...@@ -866,7 +866,7 @@ wl_cfg80211_scan(struct wiphy *wiphy, struct net_device *ndev,
static int32 wl_dev_intvar_set(struct net_device *dev, s8 *name, int32 val) static int32 wl_dev_intvar_set(struct net_device *dev, s8 *name, int32 val)
{ {
s8 buf[WLC_IOCTL_SMLEN]; s8 buf[WLC_IOCTL_SMLEN];
uint32 len; u32 len;
int32 err = 0; int32 err = 0;
val = htod32(val); val = htod32(val);
...@@ -888,8 +888,8 @@ wl_dev_intvar_get(struct net_device *dev, s8 *name, int32 *retval) ...@@ -888,8 +888,8 @@ wl_dev_intvar_get(struct net_device *dev, s8 *name, int32 *retval)
s8 buf[WLC_IOCTL_SMLEN]; s8 buf[WLC_IOCTL_SMLEN];
int32 val; int32 val;
} var; } var;
uint32 len; u32 len;
uint32 data_null; u32 data_null;
int32 err = 0; int32 err = 0;
len = len =
...@@ -905,7 +905,7 @@ wl_dev_intvar_get(struct net_device *dev, s8 *name, int32 *retval) ...@@ -905,7 +905,7 @@ wl_dev_intvar_get(struct net_device *dev, s8 *name, int32 *retval)
return err; return err;
} }
static int32 wl_set_rts(struct net_device *dev, uint32 rts_threshold) static int32 wl_set_rts(struct net_device *dev, u32 rts_threshold)
{ {
int32 err = 0; int32 err = 0;
...@@ -917,7 +917,7 @@ static int32 wl_set_rts(struct net_device *dev, uint32 rts_threshold) ...@@ -917,7 +917,7 @@ static int32 wl_set_rts(struct net_device *dev, uint32 rts_threshold)
return err; return err;
} }
static int32 wl_set_frag(struct net_device *dev, uint32 frag_threshold) static int32 wl_set_frag(struct net_device *dev, u32 frag_threshold)
{ {
int32 err = 0; int32 err = 0;
...@@ -929,10 +929,10 @@ static int32 wl_set_frag(struct net_device *dev, uint32 frag_threshold) ...@@ -929,10 +929,10 @@ static int32 wl_set_frag(struct net_device *dev, uint32 frag_threshold)
return err; return err;
} }
static int32 wl_set_retry(struct net_device *dev, uint32 retry, bool l) static int32 wl_set_retry(struct net_device *dev, u32 retry, bool l)
{ {
int32 err = 0; int32 err = 0;
uint32 cmd = (l ? WLC_SET_LRL : WLC_SET_SRL); u32 cmd = (l ? WLC_SET_LRL : WLC_SET_SRL);
retry = htod32(retry); retry = htod32(retry);
err = wl_dev_ioctl(dev, cmd, &retry, sizeof(retry)); err = wl_dev_ioctl(dev, cmd, &retry, sizeof(retry));
...@@ -943,7 +943,7 @@ static int32 wl_set_retry(struct net_device *dev, uint32 retry, bool l) ...@@ -943,7 +943,7 @@ static int32 wl_set_retry(struct net_device *dev, uint32 retry, bool l)
return err; return err;
} }
static int32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, uint32 changed) static int32 wl_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed)
{ {
struct wl_priv *wl = wiphy_to_wl(wiphy); struct wl_priv *wl = wiphy_to_wl(wiphy);
struct net_device *ndev = wl_to_ndev(wl); struct net_device *ndev = wl_to_ndev(wl);
...@@ -1270,8 +1270,8 @@ wl_set_set_sharedkey(struct net_device *dev, ...@@ -1270,8 +1270,8 @@ wl_set_set_sharedkey(struct net_device *dev,
&& (sec->cipher_pairwise & (WLAN_CIPHER_SUITE_WEP40 | && (sec->cipher_pairwise & (WLAN_CIPHER_SUITE_WEP40 |
WLAN_CIPHER_SUITE_WEP104))) { WLAN_CIPHER_SUITE_WEP104))) {
memset(&key, 0, sizeof(key)); memset(&key, 0, sizeof(key));
key.len = (uint32) sme->key_len; key.len = (u32) sme->key_len;
key.index = (uint32) sme->key_idx; key.index = (u32) sme->key_idx;
if (unlikely(key.len > sizeof(key.data))) { if (unlikely(key.len > sizeof(key.data))) {
WL_ERR(("Too long key length (%u)\n", key.len)); WL_ERR(("Too long key length (%u)\n", key.len));
return -EINVAL; return -EINVAL;
...@@ -1481,7 +1481,7 @@ static int32 ...@@ -1481,7 +1481,7 @@ static int32
wl_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *dev, wl_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *dev,
u8 key_idx) u8 key_idx)
{ {
uint32 index; u32 index;
int32 wsec; int32 wsec;
int32 err = 0; int32 err = 0;
...@@ -1496,7 +1496,7 @@ wl_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *dev, ...@@ -1496,7 +1496,7 @@ wl_cfg80211_config_default_key(struct wiphy *wiphy, struct net_device *dev,
wsec = dtoh32(wsec); wsec = dtoh32(wsec);
if (wsec & WEP_ENABLED) { if (wsec & WEP_ENABLED) {
/* Just select a new current key */ /* Just select a new current key */
index = (uint32) key_idx; index = (u32) key_idx;
index = htod32(index); index = htod32(index);
err = wl_dev_ioctl(dev, WLC_SET_KEY_PRIMARY, &index, err = wl_dev_ioctl(dev, WLC_SET_KEY_PRIMARY, &index,
sizeof(index)); sizeof(index));
...@@ -1515,12 +1515,12 @@ wl_add_keyext(struct wiphy *wiphy, struct net_device *dev, ...@@ -1515,12 +1515,12 @@ wl_add_keyext(struct wiphy *wiphy, struct net_device *dev,
int32 err = 0; int32 err = 0;
memset(&key, 0, sizeof(key)); memset(&key, 0, sizeof(key));
key.index = (uint32) key_idx; key.index = (u32) key_idx;
/* Instead of bcast for ea address for default wep keys, /* Instead of bcast for ea address for default wep keys,
driver needs it to be Null */ driver needs it to be Null */
if (!ETHER_ISMULTI(mac_addr)) if (!ETHER_ISMULTI(mac_addr))
memcpy((char *)&key.ea, (void *)mac_addr, ETHER_ADDR_LEN); memcpy((char *)&key.ea, (void *)mac_addr, ETHER_ADDR_LEN);
key.len = (uint32) params->key_len; key.len = (u32) params->key_len;
/* check for key index change */ /* check for key index change */
if (key.len == 0) { if (key.len == 0) {
/* key delete */ /* key delete */
...@@ -1611,8 +1611,8 @@ wl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *dev, ...@@ -1611,8 +1611,8 @@ wl_cfg80211_add_key(struct wiphy *wiphy, struct net_device *dev,
return wl_add_keyext(wiphy, dev, key_idx, mac_addr, params); return wl_add_keyext(wiphy, dev, key_idx, mac_addr, params);
memset(&key, 0, sizeof(key)); memset(&key, 0, sizeof(key));
key.len = (uint32) params->key_len; key.len = (u32) params->key_len;
key.index = (uint32) key_idx; key.index = (u32) key_idx;
if (unlikely(key.len > sizeof(key.data))) { if (unlikely(key.len > sizeof(key.data))) {
WL_ERR(("Too long key length (%u)\n", key.len)); WL_ERR(("Too long key length (%u)\n", key.len));
...@@ -1691,7 +1691,7 @@ wl_cfg80211_del_key(struct wiphy *wiphy, struct net_device *dev, ...@@ -1691,7 +1691,7 @@ wl_cfg80211_del_key(struct wiphy *wiphy, struct net_device *dev,
CHECK_SYS_UP(); CHECK_SYS_UP();
memset(&key, 0, sizeof(key)); memset(&key, 0, sizeof(key));
key.index = (uint32) key_idx; key.index = (u32) key_idx;
key.flags = WL_PRIMARY_KEY; key.flags = WL_PRIMARY_KEY;
key.algo = CRYPTO_ALGO_OFF; key.algo = CRYPTO_ALGO_OFF;
...@@ -1867,9 +1867,9 @@ wl_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *dev, ...@@ -1867,9 +1867,9 @@ wl_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *dev,
return err; return err;
} }
static __used uint32 wl_find_msb(u16 bit16) static __used u32 wl_find_msb(u16 bit16)
{ {
uint32 ret = 0; u32 ret = 0;
if (bit16 & 0xff00) { if (bit16 & 0xff00) {
ret += 8; ret += 8;
...@@ -1904,7 +1904,7 @@ wl_cfg80211_set_bitrate_mask(struct wiphy *wiphy, struct net_device *dev, ...@@ -1904,7 +1904,7 @@ wl_cfg80211_set_bitrate_mask(struct wiphy *wiphy, struct net_device *dev,
int32 val; int32 val;
int32 err_bg; int32 err_bg;
int32 err_a; int32 err_a;
uint32 legacy; u32 legacy;
int32 err = 0; int32 err = 0;
CHECK_SYS_UP(); CHECK_SYS_UP();
...@@ -2252,8 +2252,8 @@ static int32 wl_inform_single_bss(struct wl_priv *wl, struct wl_bss_info *bi) ...@@ -2252,8 +2252,8 @@ static int32 wl_inform_single_bss(struct wl_priv *wl, struct wl_bss_info *bi)
struct ieee80211_supported_band *band; struct ieee80211_supported_band *band;
struct wl_cfg80211_bss_info *notif_bss_info; struct wl_cfg80211_bss_info *notif_bss_info;
struct wl_scan_req *sr = wl_to_sr(wl); struct wl_scan_req *sr = wl_to_sr(wl);
uint32 signal; u32 signal;
uint32 freq; u32 freq;
int32 err = 0; int32 err = 0;
if (unlikely(dtoh32(bi->length) > WL_BSS_INFO_MAX)) { if (unlikely(dtoh32(bi->length) > WL_BSS_INFO_MAX)) {
...@@ -2316,7 +2316,7 @@ static int32 wl_inform_single_bss(struct wl_priv *wl, struct wl_bss_info *bi) ...@@ -2316,7 +2316,7 @@ static int32 wl_inform_single_bss(struct wl_priv *wl, struct wl_bss_info *bi)
static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e) static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e)
{ {
uint32 event = ntoh32(e->event_type); u32 event = ntoh32(e->event_type);
u16 flags = ntoh16(e->flags); u16 flags = ntoh16(e->flags);
if (event == WLC_E_JOIN || event == WLC_E_ASSOC_IND if (event == WLC_E_JOIN || event == WLC_E_ASSOC_IND
...@@ -2338,7 +2338,7 @@ static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e) ...@@ -2338,7 +2338,7 @@ static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e)
static bool wl_is_linkdown(struct wl_priv *wl, const wl_event_msg_t *e) static bool wl_is_linkdown(struct wl_priv *wl, const wl_event_msg_t *e)
{ {
uint32 event = ntoh32(e->event_type); u32 event = ntoh32(e->event_type);
u16 flags = ntoh16(e->flags); u16 flags = ntoh16(e->flags);
if (event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND) { if (event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND) {
...@@ -2353,8 +2353,8 @@ static bool wl_is_linkdown(struct wl_priv *wl, const wl_event_msg_t *e) ...@@ -2353,8 +2353,8 @@ static bool wl_is_linkdown(struct wl_priv *wl, const wl_event_msg_t *e)
static bool wl_is_nonetwork(struct wl_priv *wl, const wl_event_msg_t *e) static bool wl_is_nonetwork(struct wl_priv *wl, const wl_event_msg_t *e)
{ {
uint32 event = ntoh32(e->event_type); u32 event = ntoh32(e->event_type);
uint32 status = ntoh32(e->status); u32 status = ntoh32(e->status);
if (event == WLC_E_SET_SSID || event == WLC_E_LINK) { if (event == WLC_E_SET_SSID || event == WLC_E_LINK) {
if (status == WLC_E_STATUS_NO_NETWORKS) if (status == WLC_E_STATUS_NO_NETWORKS)
...@@ -2415,7 +2415,7 @@ static __used int32 ...@@ -2415,7 +2415,7 @@ static __used int32
wl_dev_bufvar_set(struct net_device *dev, s8 *name, s8 *buf, int32 len) wl_dev_bufvar_set(struct net_device *dev, s8 *name, s8 *buf, int32 len)
{ {
struct wl_priv *wl = ndev_to_wl(dev); struct wl_priv *wl = ndev_to_wl(dev);
uint32 buflen; u32 buflen;
buflen = bcm_mkiovar(name, buf, len, wl->ioctl_buf, WL_IOCTL_LEN_MAX); buflen = bcm_mkiovar(name, buf, len, wl->ioctl_buf, WL_IOCTL_LEN_MAX);
BUG_ON(unlikely(!buflen)); BUG_ON(unlikely(!buflen));
...@@ -2428,7 +2428,7 @@ wl_dev_bufvar_get(struct net_device *dev, s8 *name, s8 *buf, ...@@ -2428,7 +2428,7 @@ wl_dev_bufvar_get(struct net_device *dev, s8 *name, s8 *buf,
int32 buf_len) int32 buf_len)
{ {
struct wl_priv *wl = ndev_to_wl(dev); struct wl_priv *wl = ndev_to_wl(dev);
uint32 len; u32 len;
int32 err = 0; int32 err = 0;
len = bcm_mkiovar(name, NULL, 0, wl->ioctl_buf, WL_IOCTL_LEN_MAX); len = bcm_mkiovar(name, NULL, 0, wl->ioctl_buf, WL_IOCTL_LEN_MAX);
...@@ -2449,8 +2449,8 @@ static int32 wl_get_assoc_ies(struct wl_priv *wl) ...@@ -2449,8 +2449,8 @@ static int32 wl_get_assoc_ies(struct wl_priv *wl)
struct net_device *ndev = wl_to_ndev(wl); struct net_device *ndev = wl_to_ndev(wl);
struct wl_assoc_ielen *assoc_info; struct wl_assoc_ielen *assoc_info;
struct wl_connect_info *conn_info = wl_to_conn(wl); struct wl_connect_info *conn_info = wl_to_conn(wl);
uint32 req_len; u32 req_len;
uint32 resp_len; u32 resp_len;
int32 err = 0; int32 err = 0;
err = wl_dev_bufvar_get(ndev, "assoc_info", wl->extra_buf, err = wl_dev_bufvar_get(ndev, "assoc_info", wl->extra_buf,
...@@ -2515,7 +2515,7 @@ static int32 wl_update_bss_info(struct wl_priv *wl) ...@@ -2515,7 +2515,7 @@ static int32 wl_update_bss_info(struct wl_priv *wl)
rtnl_lock(); rtnl_lock();
if (unlikely(!bss)) { if (unlikely(!bss)) {
WL_DBG(("Could not find the AP\n")); WL_DBG(("Could not find the AP\n"));
*(uint32 *) wl->extra_buf = htod32(WL_EXTRA_BUF_MAX); *(u32 *) wl->extra_buf = htod32(WL_EXTRA_BUF_MAX);
err = wl_dev_ioctl(wl_to_ndev(wl), WLC_GET_BSS_INFO, err = wl_dev_ioctl(wl_to_ndev(wl), WLC_GET_BSS_INFO,
wl->extra_buf, WL_EXTRA_BUF_MAX); wl->extra_buf, WL_EXTRA_BUF_MAX);
if (unlikely(err)) { if (unlikely(err)) {
...@@ -2624,7 +2624,7 @@ wl_notify_scan_status(struct wl_priv *wl, struct net_device *ndev, ...@@ -2624,7 +2624,7 @@ wl_notify_scan_status(struct wl_priv *wl, struct net_device *ndev,
{ {
struct channel_info channel_inform; struct channel_info channel_inform;
struct wl_scan_results *bss_list; struct wl_scan_results *bss_list;
uint32 len = WL_SCAN_BUF_MAX; u32 len = WL_SCAN_BUF_MAX;
int32 err = 0; int32 err = 0;
if (wl->iscan_on && wl->iscan_kickstart) if (wl->iscan_on && wl->iscan_kickstart)
...@@ -2678,11 +2678,11 @@ wl_notify_scan_status(struct wl_priv *wl, struct net_device *ndev, ...@@ -2678,11 +2678,11 @@ wl_notify_scan_status(struct wl_priv *wl, struct net_device *ndev,
static void wl_init_conf(struct wl_conf *conf) static void wl_init_conf(struct wl_conf *conf)
{ {
conf->mode = (uint32)-1; conf->mode = (u32)-1;
conf->frag_threshold = (uint32)-1; conf->frag_threshold = (u32)-1;
conf->rts_threshold = (uint32)-1; conf->rts_threshold = (u32)-1;
conf->retry_short = (uint32)-1; conf->retry_short = (u32)-1;
conf->retry_long = (uint32)-1; conf->retry_long = (u32)-1;
conf->tx_power = -1; conf->tx_power = -1;
} }
...@@ -2852,7 +2852,7 @@ static int32 wl_wakeup_iscan(struct wl_iscan_ctrl *iscan) ...@@ -2852,7 +2852,7 @@ static int32 wl_wakeup_iscan(struct wl_iscan_ctrl *iscan)
} }
static int32 static int32
wl_get_iscan_results(struct wl_iscan_ctrl *iscan, uint32 *status, wl_get_iscan_results(struct wl_iscan_ctrl *iscan, u32 *status,
struct wl_scan_results **bss_list) struct wl_scan_results **bss_list)
{ {
struct wl_iscan_results list; struct wl_iscan_results list;
...@@ -2948,7 +2948,7 @@ static int32 wl_iscan_thread(void *data) ...@@ -2948,7 +2948,7 @@ static int32 wl_iscan_thread(void *data)
struct wl_iscan_ctrl *iscan = (struct wl_iscan_ctrl *)data; struct wl_iscan_ctrl *iscan = (struct wl_iscan_ctrl *)data;
struct wl_priv *wl = iscan_to_wl(iscan); struct wl_priv *wl = iscan_to_wl(iscan);
struct wl_iscan_eloop *el = &iscan->el; struct wl_iscan_eloop *el = &iscan->el;
uint32 status; u32 status;
int err = 0; int err = 0;
sched_setscheduler(current, SCHED_FIFO, &param); sched_setscheduler(current, SCHED_FIFO, &param);
...@@ -3192,7 +3192,7 @@ static int32 wl_event_handler(void *data) ...@@ -3192,7 +3192,7 @@ static int32 wl_event_handler(void *data)
void void
wl_cfg80211_event(struct net_device *ndev, const wl_event_msg_t * e, void *data) wl_cfg80211_event(struct net_device *ndev, const wl_event_msg_t * e, void *data)
{ {
uint32 event_type = ntoh32(e->event_type); u32 event_type = ntoh32(e->event_type);
struct wl_priv *wl = ndev_to_wl(ndev); struct wl_priv *wl = ndev_to_wl(ndev);
#if (WL_DBG_LEVEL > 0) #if (WL_DBG_LEVEL > 0)
s8 *estr = (event_type <= sizeof(wl_dbg_estr) / WL_DBG_ESTR_MAX - 1) ? s8 *estr = (event_type <= sizeof(wl_dbg_estr) / WL_DBG_ESTR_MAX - 1) ?
...@@ -3245,7 +3245,7 @@ static struct wl_event_q *wl_deq_event(struct wl_priv *wl) ...@@ -3245,7 +3245,7 @@ static struct wl_event_q *wl_deq_event(struct wl_priv *wl)
*/ */
static int32 static int32
wl_enq_event(struct wl_priv *wl, uint32 event, const wl_event_msg_t *msg, wl_enq_event(struct wl_priv *wl, u32 event, const wl_event_msg_t *msg,
void *data) void *data)
{ {
struct wl_event_q *e; struct wl_event_q *e;
...@@ -3337,7 +3337,7 @@ static int32 wl_dongle_country(struct net_device *ndev, u8 ccode) ...@@ -3337,7 +3337,7 @@ static int32 wl_dongle_country(struct net_device *ndev, u8 ccode)
return err; return err;
} }
static int32 wl_dongle_up(struct net_device *ndev, uint32 up) static int32 wl_dongle_up(struct net_device *ndev, u32 up)
{ {
int32 err = 0; int32 err = 0;
...@@ -3348,7 +3348,7 @@ static int32 wl_dongle_up(struct net_device *ndev, uint32 up) ...@@ -3348,7 +3348,7 @@ static int32 wl_dongle_up(struct net_device *ndev, uint32 up)
return err; return err;
} }
static int32 wl_dongle_power(struct net_device *ndev, uint32 power_mode) static int32 wl_dongle_power(struct net_device *ndev, u32 power_mode)
{ {
int32 err = 0; int32 err = 0;
...@@ -3360,7 +3360,7 @@ static int32 wl_dongle_power(struct net_device *ndev, uint32 power_mode) ...@@ -3360,7 +3360,7 @@ static int32 wl_dongle_power(struct net_device *ndev, uint32 power_mode)
} }
static int32 static int32
wl_dongle_glom(struct net_device *ndev, uint32 glom, uint32 dongle_align) wl_dongle_glom(struct net_device *ndev, u32 glom, u32 dongle_align)
{ {
s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" + s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" +
'\0' + bitvec */ '\0' + bitvec */
...@@ -3386,7 +3386,7 @@ wl_dongle_glom(struct net_device *ndev, uint32 glom, uint32 dongle_align) ...@@ -3386,7 +3386,7 @@ wl_dongle_glom(struct net_device *ndev, uint32 glom, uint32 dongle_align)
} }
static int32 static int32
wl_dongle_roam(struct net_device *ndev, uint32 roamvar, uint32 bcn_timeout) wl_dongle_roam(struct net_device *ndev, u32 roamvar, u32 bcn_timeout)
{ {
s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" + s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" +
'\0' + bitvec */ '\0' + bitvec */
...@@ -3551,7 +3551,7 @@ static int32 wl_pattern_atoh(s8 *src, s8 *dst) ...@@ -3551,7 +3551,7 @@ static int32 wl_pattern_atoh(s8 *src, s8 *dst)
return i; return i;
} }
static int32 wl_dongle_filter(struct net_device *ndev, uint32 filter_mode) static int32 wl_dongle_filter(struct net_device *ndev, u32 filter_mode)
{ {
s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" + s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" +
'\0' + bitvec */ '\0' + bitvec */
...@@ -3560,8 +3560,8 @@ static int32 wl_dongle_filter(struct net_device *ndev, uint32 filter_mode) ...@@ -3560,8 +3560,8 @@ static int32 wl_dongle_filter(struct net_device *ndev, uint32 filter_mode)
struct wl_pkt_filter *pkt_filterp; struct wl_pkt_filter *pkt_filterp;
int32 buf_len; int32 buf_len;
int32 str_len; int32 str_len;
uint32 mask_size; u32 mask_size;
uint32 pattern_size; u32 pattern_size;
s8 buf[256]; s8 buf[256];
int32 err = 0; int32 err = 0;
...@@ -3852,7 +3852,7 @@ wl_update_prof(struct wl_priv *wl, const wl_event_msg_t *e, void *data, ...@@ -3852,7 +3852,7 @@ wl_update_prof(struct wl_priv *wl, const wl_event_msg_t *e, void *data,
return err; return err;
} }
void wl_cfg80211_dbg_level(uint32 level) void wl_cfg80211_dbg_level(u32 level)
{ {
/* /*
* prohibit to change debug level * prohibit to change debug level
...@@ -3926,7 +3926,7 @@ static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size) ...@@ -3926,7 +3926,7 @@ static int32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size)
return err; return err;
} }
static uint32 wl_get_ielen(struct wl_priv *wl) static u32 wl_get_ielen(struct wl_priv *wl)
{ {
struct wl_ie *ie = wl_to_ie(wl); struct wl_ie *ie = wl_to_ie(wl);
...@@ -3966,7 +3966,7 @@ static void wl_init_eq_lock(struct wl_priv *wl) ...@@ -3966,7 +3966,7 @@ static void wl_init_eq_lock(struct wl_priv *wl)
spin_lock_init(&wl->eq_lock); spin_lock_init(&wl->eq_lock);
} }
static void wl_delay(uint32 ms) static void wl_delay(u32 ms)
{ {
if (ms < 1000 / HZ) { if (ms < 1000 / HZ) {
cond_resched(); cond_resched();
...@@ -3986,7 +3986,7 @@ static void *wl_get_drvdata(struct wl_dev *dev) ...@@ -3986,7 +3986,7 @@ static void *wl_get_drvdata(struct wl_dev *dev)
return dev->driver_data; return dev->driver_data;
} }
int32 wl_cfg80211_read_fw(s8 *buf, uint32 size) int32 wl_cfg80211_read_fw(s8 *buf, u32 size)
{ {
const struct firmware *fw_entry; const struct firmware *fw_entry;
struct wl_priv *wl; struct wl_priv *wl;
......
drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h
浏览文件 @ 66cbd3ab
...@@ -153,11 +153,11 @@ enum wl_fw_status { ...@@ -153,11 +153,11 @@ enum wl_fw_status {
/* dongle configuration */ /* dongle configuration */
struct wl_conf { struct wl_conf {
uint32 mode; /* adhoc , infrastructure or ap */ u32 mode; /* adhoc , infrastructure or ap */
uint32 frag_threshold; u32 frag_threshold;
uint32 rts_threshold; u32 rts_threshold;
uint32 retry_short; u32 retry_short;
uint32 retry_long; u32 retry_long;
int32 tx_power; int32 tx_power;
struct ieee80211_channel channel; struct ieee80211_channel channel;
}; };
...@@ -201,18 +201,18 @@ struct wl_ie { ...@@ -201,18 +201,18 @@ struct wl_ie {
/* event queue for cfg80211 main event */ /* event queue for cfg80211 main event */
struct wl_event_q { struct wl_event_q {
struct list_head eq_list; struct list_head eq_list;
uint32 etype; u32 etype;
wl_event_msg_t emsg; wl_event_msg_t emsg;
s8 edata[1]; s8 edata[1];
}; };
/* security information with currently associated ap */ /* security information with currently associated ap */
struct wl_security { struct wl_security {
uint32 wpa_versions; u32 wpa_versions;
uint32 auth_type; u32 auth_type;
uint32 cipher_pairwise; u32 cipher_pairwise;
uint32 cipher_group; u32 cipher_group;
uint32 wpa_auth; u32 wpa_auth;
}; };
/* ibss information for currently joined ibss network */ /* ibss information for currently joined ibss network */
...@@ -226,7 +226,7 @@ struct wl_ibss { ...@@ -226,7 +226,7 @@ struct wl_ibss {
/* dongle profile */ /* dongle profile */
struct wl_profile { struct wl_profile {
uint32 mode; u32 mode;
struct wlc_ssid ssid; struct wlc_ssid ssid;
u8 bssid[ETHER_ADDR_LEN]; u8 bssid[ETHER_ADDR_LEN];
struct wl_security sec; struct wl_security sec;
...@@ -244,8 +244,8 @@ struct wl_iscan_eloop { ...@@ -244,8 +244,8 @@ struct wl_iscan_eloop {
struct wl_iscan_ctrl { struct wl_iscan_ctrl {
struct net_device *dev; struct net_device *dev;
struct timer_list timer; struct timer_list timer;
uint32 timer_ms; u32 timer_ms;
uint32 timer_on; u32 timer_on;
int32 state; int32 state;
int32 pid; int32 pid;
struct semaphore sync; struct semaphore sync;
...@@ -268,15 +268,15 @@ struct wl_connect_info { ...@@ -268,15 +268,15 @@ struct wl_connect_info {
struct wl_fw_ctrl { struct wl_fw_ctrl {
const struct firmware *fw_entry; const struct firmware *fw_entry;
unsigned long status; unsigned long status;
uint32 ptr; u32 ptr;
s8 fw_name[WL_FILE_NAME_MAX]; s8 fw_name[WL_FILE_NAME_MAX];
s8 nvram_name[WL_FILE_NAME_MAX]; s8 nvram_name[WL_FILE_NAME_MAX];
}; };
/* assoc ie length */ /* assoc ie length */
struct wl_assoc_ielen { struct wl_assoc_ielen {
uint32 req_len; u32 req_len;
uint32 resp_len; u32 resp_len;
}; };
/* wpa2 pmk list */ /* wpa2 pmk list */
...@@ -318,7 +318,7 @@ struct wl_priv { ...@@ -318,7 +318,7 @@ struct wl_priv {
int32 event_pid; /* pid of main event handler thread */ int32 event_pid; /* pid of main event handler thread */
unsigned long status; /* current dongle status */ unsigned long status; /* current dongle status */
void *pub; void *pub;
uint32 channel; /* current channel */ u32 channel; /* current channel */
bool iscan_on; /* iscan on/off switch */ bool iscan_on; /* iscan on/off switch */
bool iscan_kickstart; /* indicate iscan already started */ bool iscan_kickstart; /* indicate iscan already started */
bool active_scan; /* current scan mode */ bool active_scan; /* current scan mode */
...@@ -369,11 +369,11 @@ extern void wl_cfg80211_sdio_func(void *func); /* set sdio function info */ ...@@ -369,11 +369,11 @@ extern void wl_cfg80211_sdio_func(void *func); /* set sdio function info */
extern struct sdio_func *wl_cfg80211_get_sdio_func(void); /* set sdio function info */ extern struct sdio_func *wl_cfg80211_get_sdio_func(void); /* set sdio function info */
extern int32 wl_cfg80211_up(void); /* dongle up */ extern int32 wl_cfg80211_up(void); /* dongle up */
extern int32 wl_cfg80211_down(void); /* dongle down */ extern int32 wl_cfg80211_down(void); /* dongle down */
extern void wl_cfg80211_dbg_level(uint32 level); /* set dongle extern void wl_cfg80211_dbg_level(u32 level); /* set dongle
debugging level */ debugging level */
extern void *wl_cfg80211_request_fw(s8 *file_name); /* request fw /nvram extern void *wl_cfg80211_request_fw(s8 *file_name); /* request fw /nvram
downloading */ downloading */
extern int32 wl_cfg80211_read_fw(s8 *buf, uint32 size); /* read fw extern int32 wl_cfg80211_read_fw(s8 *buf, u32 size); /* read fw
image */ image */
extern void wl_cfg80211_release_fw(void); /* release fw */ extern void wl_cfg80211_release_fw(void); /* release fw */
extern s8 *wl_cfg80211_get_fwname(void); /* get firmware name for extern s8 *wl_cfg80211_get_fwname(void); /* get firmware name for
......
drivers/staging/brcm80211/brcmfmac/wl_iw.c
浏览文件 @ 66cbd3ab
...@@ -66,8 +66,8 @@ bool g_set_essid_before_scan = TRUE; ...@@ -66,8 +66,8 @@ bool g_set_essid_before_scan = TRUE;
static int g_onoff = G_WLAN_SET_ON; static int g_onoff = G_WLAN_SET_ON;
wl_iw_extra_params_t g_wl_iw_params; wl_iw_extra_params_t g_wl_iw_params;
extern bool wl_iw_conn_status_str(uint32 event_type, uint32 status, extern bool wl_iw_conn_status_str(u32 event_type, u32 status,
uint32 reason, char *stringBuf, uint buflen); u32 reason, char *stringBuf, uint buflen);
uint wl_msg_level = WL_ERROR_VAL; uint wl_msg_level = WL_ERROR_VAL;
...@@ -127,8 +127,8 @@ typedef struct iscan_buf { ...@@ -127,8 +127,8 @@ typedef struct iscan_buf {
typedef struct iscan_info { typedef struct iscan_info {
struct net_device *dev; struct net_device *dev;
struct timer_list timer; struct timer_list timer;
uint32 timer_ms; u32 timer_ms;
uint32 timer_on; u32 timer_on;
int iscan_state; int iscan_state;
iscan_buf_t *list_hdr; iscan_buf_t *list_hdr;
iscan_buf_t *list_cur; iscan_buf_t *list_cur;
...@@ -493,7 +493,7 @@ wl_iw_get_range(struct net_device *dev, ...@@ -493,7 +493,7 @@ wl_iw_get_range(struct net_device *dev,
struct iw_point *dwrq, char *extra) struct iw_point *dwrq, char *extra)
{ {
struct iw_range *range = (struct iw_range *)extra; struct iw_range *range = (struct iw_range *)extra;
wl_uint32_list_t *list; wl_u32_list_t *list;
wl_rateset_t rateset; wl_rateset_t rateset;
s8 *channels; s8 *channels;
int error, i, k; int error, i, k;
...@@ -519,7 +519,7 @@ wl_iw_get_range(struct net_device *dev, ...@@ -519,7 +519,7 @@ wl_iw_get_range(struct net_device *dev,
WL_ERROR(("Could not alloc channels\n")); WL_ERROR(("Could not alloc channels\n"));
return -ENOMEM; return -ENOMEM;
} }
list = (wl_uint32_list_t *) channels; list = (wl_u32_list_t *) channels;
dwrq->length = sizeof(struct iw_range); dwrq->length = sizeof(struct iw_range);
memset(range, 0, sizeof(range)); memset(range, 0, sizeof(range));
...@@ -1097,14 +1097,14 @@ static void wl_iw_set_event_mask(struct net_device *dev) ...@@ -1097,14 +1097,14 @@ static void wl_iw_set_event_mask(struct net_device *dev)
iovbuf, sizeof(iovbuf)); iovbuf, sizeof(iovbuf));
} }
static uint32 wl_iw_iscan_get(iscan_info_t *iscan) static u32 wl_iw_iscan_get(iscan_info_t *iscan)
{ {
iscan_buf_t *buf; iscan_buf_t *buf;
iscan_buf_t *ptr; iscan_buf_t *ptr;
wl_iscan_results_t *list_buf; wl_iscan_results_t *list_buf;
wl_iscan_results_t list; wl_iscan_results_t list;
wl_scan_results_t *results; wl_scan_results_t *results;
uint32 status; u32 status;
int res = 0; int res = 0;
MUTEX_LOCK_WL_SCAN_SET(); MUTEX_LOCK_WL_SCAN_SET();
...@@ -1185,7 +1185,7 @@ static void wl_iw_send_scan_complete(iscan_info_t *iscan) ...@@ -1185,7 +1185,7 @@ static void wl_iw_send_scan_complete(iscan_info_t *iscan)
static int _iscan_sysioc_thread(void *data) static int _iscan_sysioc_thread(void *data)
{ {
uint32 status; u32 status;
iscan_info_t *iscan = (iscan_info_t *) data; iscan_info_t *iscan = (iscan_info_t *) data;
static bool iscan_pass_abort = FALSE; static bool iscan_pass_abort = FALSE;
DAEMONIZE("iscan_sysioc"); DAEMONIZE("iscan_sysioc");
...@@ -1745,7 +1745,7 @@ wl_iw_iscan_get_scan(struct net_device *dev, ...@@ -1745,7 +1745,7 @@ wl_iw_iscan_get_scan(struct net_device *dev,
char *event = extra, *end = extra + dwrq->length, *value; char *event = extra, *end = extra + dwrq->length, *value;
iscan_info_t *iscan = g_iscan; iscan_info_t *iscan = g_iscan;
iscan_buf_t *p_buf; iscan_buf_t *p_buf;
uint32 counter = 0; u32 counter = 0;
u8 channel; u8 channel;
WL_TRACE(("%s %s buflen_from_user %d:\n", dev->name, __func__, WL_TRACE(("%s %s buflen_from_user %d:\n", dev->name, __func__,
...@@ -3300,13 +3300,13 @@ int wl_iw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) ...@@ -3300,13 +3300,13 @@ int wl_iw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
} }
bool bool
wl_iw_conn_status_str(uint32 event_type, uint32 status, uint32 reason, wl_iw_conn_status_str(u32 event_type, u32 status, u32 reason,
char *stringBuf, uint buflen) char *stringBuf, uint buflen)
{ {
typedef struct conn_fail_event_map_t { typedef struct conn_fail_event_map_t {
uint32 inEvent; u32 inEvent;
uint32 inStatus; u32 inStatus;
uint32 inReason; u32 inReason;
const char *outName; const char *outName;
const char *outCause; const char *outCause;
} conn_fail_event_map_t; } conn_fail_event_map_t;
...@@ -3380,9 +3380,9 @@ wl_iw_conn_status_str(uint32 event_type, uint32 status, uint32 reason, ...@@ -3380,9 +3380,9 @@ wl_iw_conn_status_str(uint32 event_type, uint32 status, uint32 reason,
static bool static bool
wl_iw_check_conn_fail(wl_event_msg_t *e, char *stringBuf, uint buflen) wl_iw_check_conn_fail(wl_event_msg_t *e, char *stringBuf, uint buflen)
{ {
uint32 event = ntoh32(e->event_type); u32 event = ntoh32(e->event_type);
uint32 status = ntoh32(e->status); u32 status = ntoh32(e->status);
uint32 reason = ntoh32(e->reason); u32 reason = ntoh32(e->reason);
if (wl_iw_conn_status_str(event, status, reason, stringBuf, buflen)) { if (wl_iw_conn_status_str(event, status, reason, stringBuf, buflen)) {
return TRUE; return TRUE;
...@@ -3401,12 +3401,12 @@ void wl_iw_event(struct net_device *dev, wl_event_msg_t *e, void *data) ...@@ -3401,12 +3401,12 @@ void wl_iw_event(struct net_device *dev, wl_event_msg_t *e, void *data)
union iwreq_data wrqu; union iwreq_data wrqu;
char extra[IW_CUSTOM_MAX + 1]; char extra[IW_CUSTOM_MAX + 1];
int cmd = 0; int cmd = 0;
uint32 event_type = ntoh32(e->event_type); u32 event_type = ntoh32(e->event_type);
u16 flags = ntoh16(e->flags); u16 flags = ntoh16(e->flags);
uint32 datalen = ntoh32(e->datalen); u32 datalen = ntoh32(e->datalen);
uint32 status = ntoh32(e->status); u32 status = ntoh32(e->status);
wl_iw_t *iw; wl_iw_t *iw;
uint32 toto; u32 toto;
memset(&wrqu, 0, sizeof(wrqu)); memset(&wrqu, 0, sizeof(wrqu));
memset(extra, 0, sizeof(extra)); memset(extra, 0, sizeof(extra));
iw = 0; iw = 0;
......
drivers/staging/brcm80211/brcmfmac/wl_iw.h
浏览文件 @ 66cbd3ab
...@@ -93,8 +93,8 @@ typedef struct wl_iw { ...@@ -93,8 +93,8 @@ typedef struct wl_iw {
struct iw_statistics wstats; struct iw_statistics wstats;
int spy_num; int spy_num;
uint32 pwsec; u32 pwsec;
uint32 gwsec; u32 gwsec;
bool privacy_invoked; bool privacy_invoked;
struct ether_addr spy_addr[IW_MAX_SPY]; struct ether_addr spy_addr[IW_MAX_SPY];
......
drivers/staging/brcm80211/include/aidmp.h
浏览文件 @ 66cbd3ab
...@@ -103,121 +103,121 @@ ...@@ -103,121 +103,121 @@
#ifndef _LANGUAGE_ASSEMBLY #ifndef _LANGUAGE_ASSEMBLY
typedef volatile struct _aidmp { typedef volatile struct _aidmp {
uint32 oobselina30; /* 0x000 */ u32 oobselina30; /* 0x000 */
uint32 oobselina74; /* 0x004 */ u32 oobselina74; /* 0x004 */
uint32 PAD[6]; u32 PAD[6];
uint32 oobselinb30; /* 0x020 */ u32 oobselinb30; /* 0x020 */
uint32 oobselinb74; /* 0x024 */ u32 oobselinb74; /* 0x024 */
uint32 PAD[6]; u32 PAD[6];
uint32 oobselinc30; /* 0x040 */ u32 oobselinc30; /* 0x040 */
uint32 oobselinc74; /* 0x044 */ u32 oobselinc74; /* 0x044 */
uint32 PAD[6]; u32 PAD[6];
uint32 oobselind30; /* 0x060 */ u32 oobselind30; /* 0x060 */
uint32 oobselind74; /* 0x064 */ u32 oobselind74; /* 0x064 */
uint32 PAD[38]; u32 PAD[38];
uint32 oobselouta30; /* 0x100 */ u32 oobselouta30; /* 0x100 */
uint32 oobselouta74; /* 0x104 */ u32 oobselouta74; /* 0x104 */
uint32 PAD[6]; u32 PAD[6];
uint32 oobseloutb30; /* 0x120 */ u32 oobseloutb30; /* 0x120 */
uint32 oobseloutb74; /* 0x124 */ u32 oobseloutb74; /* 0x124 */
uint32 PAD[6]; u32 PAD[6];
uint32 oobseloutc30; /* 0x140 */ u32 oobseloutc30; /* 0x140 */
uint32 oobseloutc74; /* 0x144 */ u32 oobseloutc74; /* 0x144 */
uint32 PAD[6]; u32 PAD[6];
uint32 oobseloutd30; /* 0x160 */ u32 oobseloutd30; /* 0x160 */
uint32 oobseloutd74; /* 0x164 */ u32 oobseloutd74; /* 0x164 */
uint32 PAD[38]; u32 PAD[38];
uint32 oobsynca; /* 0x200 */ u32 oobsynca; /* 0x200 */
uint32 oobseloutaen; /* 0x204 */ u32 oobseloutaen; /* 0x204 */
uint32 PAD[6]; u32 PAD[6];
uint32 oobsyncb; /* 0x220 */ u32 oobsyncb; /* 0x220 */
uint32 oobseloutben; /* 0x224 */ u32 oobseloutben; /* 0x224 */
uint32 PAD[6]; u32 PAD[6];
uint32 oobsyncc; /* 0x240 */ u32 oobsyncc; /* 0x240 */
uint32 oobseloutcen; /* 0x244 */ u32 oobseloutcen; /* 0x244 */
uint32 PAD[6]; u32 PAD[6];
uint32 oobsyncd; /* 0x260 */ u32 oobsyncd; /* 0x260 */
uint32 oobseloutden; /* 0x264 */ u32 oobseloutden; /* 0x264 */
uint32 PAD[38]; u32 PAD[38];
uint32 oobaextwidth; /* 0x300 */ u32 oobaextwidth; /* 0x300 */
uint32 oobainwidth; /* 0x304 */ u32 oobainwidth; /* 0x304 */
uint32 oobaoutwidth; /* 0x308 */ u32 oobaoutwidth; /* 0x308 */
uint32 PAD[5]; u32 PAD[5];
uint32 oobbextwidth; /* 0x320 */ u32 oobbextwidth; /* 0x320 */
uint32 oobbinwidth; /* 0x324 */ u32 oobbinwidth; /* 0x324 */
uint32 oobboutwidth; /* 0x328 */ u32 oobboutwidth; /* 0x328 */
uint32 PAD[5]; u32 PAD[5];
uint32 oobcextwidth; /* 0x340 */ u32 oobcextwidth; /* 0x340 */
uint32 oobcinwidth; /* 0x344 */ u32 oobcinwidth; /* 0x344 */
uint32 oobcoutwidth; /* 0x348 */ u32 oobcoutwidth; /* 0x348 */
uint32 PAD[5]; u32 PAD[5];
uint32 oobdextwidth; /* 0x360 */ u32 oobdextwidth; /* 0x360 */
uint32 oobdinwidth; /* 0x364 */ u32 oobdinwidth; /* 0x364 */
uint32 oobdoutwidth; /* 0x368 */ u32 oobdoutwidth; /* 0x368 */
uint32 PAD[37]; u32 PAD[37];
uint32 ioctrlset; /* 0x400 */ u32 ioctrlset; /* 0x400 */
uint32 ioctrlclear; /* 0x404 */ u32 ioctrlclear; /* 0x404 */
uint32 ioctrl; /* 0x408 */ u32 ioctrl; /* 0x408 */
uint32 PAD[61]; u32 PAD[61];
uint32 iostatus; /* 0x500 */ u32 iostatus; /* 0x500 */
uint32 PAD[127]; u32 PAD[127];
uint32 ioctrlwidth; /* 0x700 */ u32 ioctrlwidth; /* 0x700 */
uint32 iostatuswidth; /* 0x704 */ u32 iostatuswidth; /* 0x704 */
uint32 PAD[62]; u32 PAD[62];
uint32 resetctrl; /* 0x800 */ u32 resetctrl; /* 0x800 */
uint32 resetstatus; /* 0x804 */ u32 resetstatus; /* 0x804 */
uint32 resetreadid; /* 0x808 */ u32 resetreadid; /* 0x808 */
uint32 resetwriteid; /* 0x80c */ u32 resetwriteid; /* 0x80c */
uint32 PAD[60]; u32 PAD[60];
uint32 errlogctrl; /* 0x900 */ u32 errlogctrl; /* 0x900 */
uint32 errlogdone; /* 0x904 */ u32 errlogdone; /* 0x904 */
uint32 errlogstatus; /* 0x908 */ u32 errlogstatus; /* 0x908 */
uint32 errlogaddrlo; /* 0x90c */ u32 errlogaddrlo; /* 0x90c */
uint32 errlogaddrhi; /* 0x910 */ u32 errlogaddrhi; /* 0x910 */
uint32 errlogid; /* 0x914 */ u32 errlogid; /* 0x914 */
uint32 errloguser; /* 0x918 */ u32 errloguser; /* 0x918 */
uint32 errlogflags; /* 0x91c */ u32 errlogflags; /* 0x91c */
uint32 PAD[56]; u32 PAD[56];
uint32 intstatus; /* 0xa00 */ u32 intstatus; /* 0xa00 */
uint32 PAD[127]; u32 PAD[127];
uint32 config; /* 0xe00 */ u32 config; /* 0xe00 */
uint32 PAD[63]; u32 PAD[63];
uint32 itcr; /* 0xf00 */ u32 itcr; /* 0xf00 */
uint32 PAD[3]; u32 PAD[3];
uint32 itipooba; /* 0xf10 */ u32 itipooba; /* 0xf10 */
uint32 itipoobb; /* 0xf14 */ u32 itipoobb; /* 0xf14 */
uint32 itipoobc; /* 0xf18 */ u32 itipoobc; /* 0xf18 */
uint32 itipoobd; /* 0xf1c */ u32 itipoobd; /* 0xf1c */
uint32 PAD[4]; u32 PAD[4];
uint32 itipoobaout; /* 0xf30 */ u32 itipoobaout; /* 0xf30 */
uint32 itipoobbout; /* 0xf34 */ u32 itipoobbout; /* 0xf34 */
uint32 itipoobcout; /* 0xf38 */ u32 itipoobcout; /* 0xf38 */
uint32 itipoobdout; /* 0xf3c */ u32 itipoobdout; /* 0xf3c */
uint32 PAD[4]; u32 PAD[4];
uint32 itopooba; /* 0xf50 */ u32 itopooba; /* 0xf50 */
uint32 itopoobb; /* 0xf54 */ u32 itopoobb; /* 0xf54 */
uint32 itopoobc; /* 0xf58 */ u32 itopoobc; /* 0xf58 */
uint32 itopoobd; /* 0xf5c */ u32 itopoobd; /* 0xf5c */
uint32 PAD[4]; u32 PAD[4];
uint32 itopoobain; /* 0xf70 */ u32 itopoobain; /* 0xf70 */
uint32 itopoobbin; /* 0xf74 */ u32 itopoobbin; /* 0xf74 */
uint32 itopoobcin; /* 0xf78 */ u32 itopoobcin; /* 0xf78 */
uint32 itopoobdin; /* 0xf7c */ u32 itopoobdin; /* 0xf7c */
uint32 PAD[4]; u32 PAD[4];
uint32 itopreset; /* 0xf90 */ u32 itopreset; /* 0xf90 */
uint32 PAD[15]; u32 PAD[15];
uint32 peripherialid4; /* 0xfd0 */ u32 peripherialid4; /* 0xfd0 */
uint32 peripherialid5; /* 0xfd4 */ u32 peripherialid5; /* 0xfd4 */
uint32 peripherialid6; /* 0xfd8 */ u32 peripherialid6; /* 0xfd8 */
uint32 peripherialid7; /* 0xfdc */ u32 peripherialid7; /* 0xfdc */
uint32 peripherialid0; /* 0xfe0 */ u32 peripherialid0; /* 0xfe0 */
uint32 peripherialid1; /* 0xfe4 */ u32 peripherialid1; /* 0xfe4 */
uint32 peripherialid2; /* 0xfe8 */ u32 peripherialid2; /* 0xfe8 */
uint32 peripherialid3; /* 0xfec */ u32 peripherialid3; /* 0xfec */
uint32 componentid0; /* 0xff0 */ u32 componentid0; /* 0xff0 */
uint32 componentid1; /* 0xff4 */ u32 componentid1; /* 0xff4 */
uint32 componentid2; /* 0xff8 */ u32 componentid2; /* 0xff8 */
uint32 componentid3; /* 0xffc */ u32 componentid3; /* 0xffc */
} aidmp_t; } aidmp_t;
#endif /* _LANGUAGE_ASSEMBLY */ #endif /* _LANGUAGE_ASSEMBLY */
......
drivers/staging/brcm80211/include/bcm_rpc.h
浏览文件 @ 66cbd3ab
...@@ -65,7 +65,7 @@ extern uint bcm_rpc_buf_header_len(struct rpc_info *rpci); ...@@ -65,7 +65,7 @@ extern uint bcm_rpc_buf_header_len(struct rpc_info *rpci);
#define RPC_PKTLOG_SIZE 50 /* Depth of the history */ #define RPC_PKTLOG_SIZE 50 /* Depth of the history */
#define RPC_PKTLOG_RD_LEN 3 #define RPC_PKTLOG_RD_LEN 3
#define RPC_PKTLOG_DUMP_SIZE 150 /* dump size should be more than the product of above two */ #define RPC_PKTLOG_DUMP_SIZE 150 /* dump size should be more than the product of above two */
extern int bcm_rpc_pktlog_get(struct rpc_info *rpci, uint32 *buf, extern int bcm_rpc_pktlog_get(struct rpc_info *rpci, u32 *buf,
uint buf_size, bool send); uint buf_size, bool send);
extern int bcm_rpc_dump(rpc_info_t *rpci, struct bcmstrbuf *b); extern int bcm_rpc_dump(rpc_info_t *rpci, struct bcmstrbuf *b);
......
drivers/staging/brcm80211/include/bcm_rpc_tp.h
浏览文件 @ 66cbd3ab
...@@ -112,7 +112,7 @@ extern void bcm_rpc_tp_txq_wm_get(rpc_tp_info_t *rpc_th, u8 *hiwm, ...@@ -112,7 +112,7 @@ extern void bcm_rpc_tp_txq_wm_get(rpc_tp_info_t *rpc_th, u8 *hiwm,
u8 *lowm); u8 *lowm);
#endif /* WLC_LOW */ #endif /* WLC_LOW */
extern void bcm_rpc_tp_agg_set(rpc_tp_info_t *rpcb, uint32 reason, bool set); extern void bcm_rpc_tp_agg_set(rpc_tp_info_t *rpcb, u32 reason, bool set);
extern void bcm_rpc_tp_agg_limit_set(rpc_tp_info_t *rpc_th, u8 sf, extern void bcm_rpc_tp_agg_limit_set(rpc_tp_info_t *rpc_th, u8 sf,
u16 bytes); u16 bytes);
extern void bcm_rpc_tp_agg_limit_get(rpc_tp_info_t *rpc_th, u8 *sf, extern void bcm_rpc_tp_agg_limit_get(rpc_tp_info_t *rpc_th, u8 *sf,
......
drivers/staging/brcm80211/include/bcm_xdr.h
浏览文件 @ 66cbd3ab
...@@ -33,8 +33,8 @@ typedef struct { ...@@ -33,8 +33,8 @@ typedef struct {
void bcm_xdr_buf_init(bcm_xdr_buf_t *b, void *buf, size_t len); void bcm_xdr_buf_init(bcm_xdr_buf_t *b, void *buf, size_t len);
int bcm_xdr_pack_uint32(bcm_xdr_buf_t *b, uint32 val); int bcm_xdr_pack_u32(bcm_xdr_buf_t *b, u32 val);
int bcm_xdr_unpack_uint32(bcm_xdr_buf_t *b, uint32 *pval); int bcm_xdr_unpack_u32(bcm_xdr_buf_t *b, u32 *pval);
int bcm_xdr_pack_int32(bcm_xdr_buf_t *b, int32 val); int bcm_xdr_pack_int32(bcm_xdr_buf_t *b, int32 val);
int bcm_xdr_unpack_int32(bcm_xdr_buf_t *b, int32 *pval); int bcm_xdr_unpack_int32(bcm_xdr_buf_t *b, int32 *pval);
int bcm_xdr_pack_s8(bcm_xdr_buf_t *b, s8 val); int bcm_xdr_pack_s8(bcm_xdr_buf_t *b, s8 val);
...@@ -47,12 +47,12 @@ int bcm_xdr_unpack_opaque_varlen(bcm_xdr_buf_t *b, uint *plen, void **pdata); ...@@ -47,12 +47,12 @@ int bcm_xdr_unpack_opaque_varlen(bcm_xdr_buf_t *b, uint *plen, void **pdata);
int bcm_xdr_pack_string(bcm_xdr_buf_t *b, char *str); int bcm_xdr_pack_string(bcm_xdr_buf_t *b, char *str);
int bcm_xdr_unpack_string(bcm_xdr_buf_t *b, uint *plen, char **pstr); int bcm_xdr_unpack_string(bcm_xdr_buf_t *b, uint *plen, char **pstr);
int bcm_xdr_pack_u8_vec(bcm_xdr_buf_t *, u8 *vec, uint32 elems); int bcm_xdr_pack_u8_vec(bcm_xdr_buf_t *, u8 *vec, u32 elems);
int bcm_xdr_unpack_u8_vec(bcm_xdr_buf_t *, u8 *vec, uint32 elems); int bcm_xdr_unpack_u8_vec(bcm_xdr_buf_t *, u8 *vec, u32 elems);
int bcm_xdr_pack_u16_vec(bcm_xdr_buf_t *b, uint len, void *vec); int bcm_xdr_pack_u16_vec(bcm_xdr_buf_t *b, uint len, void *vec);
int bcm_xdr_unpack_u16_vec(bcm_xdr_buf_t *b, uint len, void *vec); int bcm_xdr_unpack_u16_vec(bcm_xdr_buf_t *b, uint len, void *vec);
int bcm_xdr_pack_uint32_vec(bcm_xdr_buf_t *b, uint len, void *vec); int bcm_xdr_pack_u32_vec(bcm_xdr_buf_t *b, uint len, void *vec);
int bcm_xdr_unpack_uint32_vec(bcm_xdr_buf_t *b, uint len, void *vec); int bcm_xdr_unpack_u32_vec(bcm_xdr_buf_t *b, uint len, void *vec);
int bcm_xdr_pack_opaque_raw(bcm_xdr_buf_t *b, uint len, void *data); int bcm_xdr_pack_opaque_raw(bcm_xdr_buf_t *b, uint len, void *data);
int bcm_xdr_pack_opaque_pad(bcm_xdr_buf_t *b); int bcm_xdr_pack_opaque_pad(bcm_xdr_buf_t *b);
......
drivers/staging/brcm80211/include/bcmcdc.h
浏览文件 @ 66cbd3ab
...@@ -16,11 +16,11 @@ ...@@ -16,11 +16,11 @@
#include <proto/ethernet.h> #include <proto/ethernet.h>
typedef struct cdc_ioctl { typedef struct cdc_ioctl {
uint32 cmd; /* ioctl command value */ u32 cmd; /* ioctl command value */
uint32 len; /* lower 16: output buflen; upper 16: u32 len; /* lower 16: output buflen; upper 16:
input buflen (excludes header) */ input buflen (excludes header) */
uint32 flags; /* flag defns given below */ u32 flags; /* flag defns given below */
uint32 status; /* status code returned from the device */ u32 status; /* status code returned from the device */
} cdc_ioctl_t; } cdc_ioctl_t;
/* Max valid buffer size that can be sent to the dongle */ /* Max valid buffer size that can be sent to the dongle */
......
drivers/staging/brcm80211/include/bcmdefs.h
浏览文件 @ 66cbd3ab
...@@ -104,8 +104,8 @@ ...@@ -104,8 +104,8 @@
#ifdef BCMDMA64OSL #ifdef BCMDMA64OSL
typedef struct { typedef struct {
uint32 loaddr; u32 loaddr;
uint32 hiaddr; u32 hiaddr;
} dma64addr_t; } dma64addr_t;
typedef dma64addr_t dmaaddr_t; typedef dma64addr_t dmaaddr_t;
...@@ -134,7 +134,7 @@ typedef unsigned long dmaaddr_t; ...@@ -134,7 +134,7 @@ typedef unsigned long dmaaddr_t;
/* One physical DMA segment */ /* One physical DMA segment */
typedef struct { typedef struct {
dmaaddr_t addr; dmaaddr_t addr;
uint32 length; u32 length;
} hnddma_seg_t; } hnddma_seg_t;
#define MAX_DMA_SEGS 4 #define MAX_DMA_SEGS 4
......
drivers/staging/brcm80211/include/bcmendian.h
浏览文件 @ 66cbd3ab
...@@ -26,15 +26,15 @@ ...@@ -26,15 +26,15 @@
/* Reverse the bytes in a 32-bit value */ /* Reverse the bytes in a 32-bit value */
#define BCMSWAP32(val) \ #define BCMSWAP32(val) \
((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \ ((u32)((((u32)(val) & (u32)0x000000ffU) << 24) | \
(((uint32)(val) & (uint32)0x0000ff00U) << 8) | \ (((u32)(val) & (u32)0x0000ff00U) << 8) | \
(((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \ (((u32)(val) & (u32)0x00ff0000U) >> 8) | \
(((uint32)(val) & (uint32)0xff000000U) >> 24))) (((u32)(val) & (u32)0xff000000U) >> 24)))
/* Reverse the two 16-bit halves of a 32-bit value */ /* Reverse the two 16-bit halves of a 32-bit value */
#define BCMSWAP32BY16(val) \ #define BCMSWAP32BY16(val) \
((uint32)((((uint32)(val) & (uint32)0x0000ffffU) << 16) | \ ((u32)((((u32)(val) & (u32)0x0000ffffU) << 16) | \
(((uint32)(val) & (uint32)0xffff0000U) >> 16))) (((u32)(val) & (u32)0xffff0000U) >> 16)))
/* Byte swapping macros /* Byte swapping macros
* Host <=> Network (Big Endian) for 16- and 32-bit values * Host <=> Network (Big Endian) for 16- and 32-bit values
...@@ -107,13 +107,13 @@ ...@@ -107,13 +107,13 @@
#define ltoh_ua(ptr) \ #define ltoh_ua(ptr) \
(sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \ (sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \
sizeof(*(ptr)) == sizeof(u16) ? _LTOH16_UA((const u8 *)(ptr)) : \ sizeof(*(ptr)) == sizeof(u16) ? _LTOH16_UA((const u8 *)(ptr)) : \
sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const u8 *)(ptr)) : \ sizeof(*(ptr)) == sizeof(u32) ? _LTOH32_UA((const u8 *)(ptr)) : \
*(u8 *)0) *(u8 *)0)
#define ntoh_ua(ptr) \ #define ntoh_ua(ptr) \
(sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \ (sizeof(*(ptr)) == sizeof(u8) ? *(const u8 *)(ptr) : \
sizeof(*(ptr)) == sizeof(u16) ? _NTOH16_UA((const u8 *)(ptr)) : \ sizeof(*(ptr)) == sizeof(u16) ? _NTOH16_UA((const u8 *)(ptr)) : \
sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const u8 *)(ptr)) : \ sizeof(*(ptr)) == sizeof(u32) ? _NTOH32_UA((const u8 *)(ptr)) : \
*(u8 *)0) *(u8 *)0)
#ifdef __GNUC__ #ifdef __GNUC__
...@@ -128,12 +128,12 @@ ...@@ -128,12 +128,12 @@
}) })
#define bcmswap32(val) ({ \ #define bcmswap32(val) ({ \
uint32 _val = (val); \ u32 _val = (val); \
BCMSWAP32(_val); \ BCMSWAP32(_val); \
}) })
#define bcmswap32by16(val) ({ \ #define bcmswap32by16(val) ({ \
uint32 _val = (val); \ u32 _val = (val); \
BCMSWAP32BY16(_val); \ BCMSWAP32BY16(_val); \
}) })
...@@ -154,7 +154,7 @@ ...@@ -154,7 +154,7 @@
}) })
#define htol32_ua_store(val, bytes) ({ \ #define htol32_ua_store(val, bytes) ({ \
uint32 _val = (val); \ u32 _val = (val); \
u8 *_bytes = (u8 *)(bytes); \ u8 *_bytes = (u8 *)(bytes); \
_bytes[0] = _val & 0xff; \ _bytes[0] = _val & 0xff; \
_bytes[1] = (_val >> 8) & 0xff; \ _bytes[1] = (_val >> 8) & 0xff; \
...@@ -170,7 +170,7 @@ ...@@ -170,7 +170,7 @@
}) })
#define hton32_ua_store(val, bytes) ({ \ #define hton32_ua_store(val, bytes) ({ \
uint32 _val = (val); \ u32 _val = (val); \
u8 *_bytes = (u8 *)(bytes); \ u8 *_bytes = (u8 *)(bytes); \
_bytes[0] = _val >> 24; \ _bytes[0] = _val >> 24; \
_bytes[1] = (_val >> 16) & 0xff; \ _bytes[1] = (_val >> 16) & 0xff; \
...@@ -206,12 +206,12 @@ static inline u16 bcmswap16(u16 val) ...@@ -206,12 +206,12 @@ static inline u16 bcmswap16(u16 val)
return BCMSWAP16(val); return BCMSWAP16(val);
} }
static inline uint32 bcmswap32(uint32 val) static inline u32 bcmswap32(u32 val)
{ {
return BCMSWAP32(val); return BCMSWAP32(val);
} }
static inline uint32 bcmswap32by16(uint32 val) static inline u32 bcmswap32by16(u32 val)
{ {
return BCMSWAP32BY16(val); return BCMSWAP32BY16(val);
} }
...@@ -241,7 +241,7 @@ static inline void htol16_ua_store(u16 val, u8 *bytes) ...@@ -241,7 +241,7 @@ static inline void htol16_ua_store(u16 val, u8 *bytes)
/* /*
* Store 32-bit value to unaligned little-endian byte array. * Store 32-bit value to unaligned little-endian byte array.
*/ */
static inline void htol32_ua_store(uint32 val, u8 *bytes) static inline void htol32_ua_store(u32 val, u8 *bytes)
{ {
bytes[0] = val & 0xff; bytes[0] = val & 0xff;
bytes[1] = (val >> 8) & 0xff; bytes[1] = (val >> 8) & 0xff;
...@@ -261,7 +261,7 @@ static inline void hton16_ua_store(u16 val, u8 *bytes) ...@@ -261,7 +261,7 @@ static inline void hton16_ua_store(u16 val, u8 *bytes)
/* /*
* Store 32-bit value to unaligned network-(big-)endian byte array. * Store 32-bit value to unaligned network-(big-)endian byte array.
*/ */
static inline void hton32_ua_store(uint32 val, u8 *bytes) static inline void hton32_ua_store(u32 val, u8 *bytes)
{ {
bytes[0] = val >> 24; bytes[0] = val >> 24;
bytes[1] = (val >> 16) & 0xff; bytes[1] = (val >> 16) & 0xff;
...@@ -280,7 +280,7 @@ static inline u16 ltoh16_ua(const void *bytes) ...@@ -280,7 +280,7 @@ static inline u16 ltoh16_ua(const void *bytes)
/* /*
* Load 32-bit value from unaligned little-endian byte array. * Load 32-bit value from unaligned little-endian byte array.
*/ */
static inline uint32 ltoh32_ua(const void *bytes) static inline u32 ltoh32_ua(const void *bytes)
{ {
return _LTOH32_UA((const u8 *)bytes); return _LTOH32_UA((const u8 *)bytes);
} }
...@@ -296,7 +296,7 @@ static inline u16 ntoh16_ua(const void *bytes) ...@@ -296,7 +296,7 @@ static inline u16 ntoh16_ua(const void *bytes)
/* /*
* Load 32-bit value from unaligned big-(network-)endian byte array. * Load 32-bit value from unaligned big-(network-)endian byte array.
*/ */
static inline uint32 ntoh32_ua(const void *bytes) static inline u32 ntoh32_ua(const void *bytes)
{ {
return _NTOH32_UA((const u8 *)bytes); return _NTOH32_UA((const u8 *)bytes);
} }
......
drivers/staging/brcm80211/include/bcmnvram.h
浏览文件 @ 66cbd3ab
...@@ -23,11 +23,11 @@ ...@@ -23,11 +23,11 @@
#include <bcmdefs.h> #include <bcmdefs.h>
struct nvram_header { struct nvram_header {
uint32 magic; u32 magic;
uint32 len; u32 len;
uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */ u32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */ u32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
uint32 config_ncdl; /* ncdl values for memc */ u32 config_ncdl; /* ncdl values for memc */
}; };
struct nvram_tuple { struct nvram_tuple {
......
drivers/staging/brcm80211/include/bcmsdbus.h
浏览文件 @ 66cbd3ab
...@@ -72,22 +72,22 @@ extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t *si, uint rw, uint fnc, ...@@ -72,22 +72,22 @@ extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t *si, uint rw, uint fnc,
/* read or write 2/4 bytes using cmd53 */ /* read or write 2/4 bytes using cmd53 */
extern SDIOH_API_RC sdioh_request_word(sdioh_info_t *si, uint cmd_type, extern SDIOH_API_RC sdioh_request_word(sdioh_info_t *si, uint cmd_type,
uint rw, uint fnc, uint addr, uint rw, uint fnc, uint addr,
uint32 *word, uint nbyte); u32 *word, uint nbyte);
/* read or write any buffer using cmd53 */ /* read or write any buffer using cmd53 */
extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma, extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma,
uint fix_inc, uint rw, uint fnc_num, uint fix_inc, uint rw, uint fnc_num,
uint32 addr, uint regwidth, u32 addr, uint regwidth,
uint32 buflen, u8 *buffer, u32 buflen, u8 *buffer,
void *pkt); void *pkt);
/* get cis data */ /* get cis data */
extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t *si, uint fuc, u8 *cis, extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t *si, uint fuc, u8 *cis,
uint32 length); u32 length);
extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t *si, uint fuc, uint32 addr, extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t *si, uint fuc, u32 addr,
u8 *data); u8 *data);
extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t *si, uint fuc, uint32 addr, extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t *si, uint fuc, u32 addr,
u8 *data); u8 *data);
/* query number of io functions */ /* query number of io functions */
......
drivers/staging/brcm80211/include/bcmsdh.h
浏览文件 @ 66cbd3ab
...@@ -75,15 +75,15 @@ extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh); ...@@ -75,15 +75,15 @@ extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
* data: data byte to write * data: data byte to write
* err: pointer to error code (or NULL) * err: pointer to error code (or NULL)
*/ */
extern u8 bcmsdh_cfg_read(void *sdh, uint func, uint32 addr, int *err); extern u8 bcmsdh_cfg_read(void *sdh, uint func, u32 addr, int *err);
extern void bcmsdh_cfg_write(void *sdh, uint func, uint32 addr, u8 data, extern void bcmsdh_cfg_write(void *sdh, uint func, u32 addr, u8 data,
int *err); int *err);
/* Read/Write 4bytes from/to cfg space */ /* Read/Write 4bytes from/to cfg space */
extern uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, extern u32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, u32 addr,
int *err); int *err);
extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, u32 addr,
uint32 data, int *err); u32 data, int *err);
/* Read CIS content for specified function. /* Read CIS content for specified function.
* fn: function whose CIS is being requested (0 is common CIS) * fn: function whose CIS is being requested (0 is common CIS)
...@@ -99,8 +99,8 @@ extern int bcmsdh_cis_read(void *sdh, uint func, u8 *cis, uint length); ...@@ -99,8 +99,8 @@ extern int bcmsdh_cis_read(void *sdh, uint func, u8 *cis, uint length);
* size: register width in bytes (2 or 4) * size: register width in bytes (2 or 4)
* data: data for register write * data: data for register write
*/ */
extern uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size); extern u32 bcmsdh_reg_read(void *sdh, u32 addr, uint size);
extern uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data); extern u32 bcmsdh_reg_write(void *sdh, u32 addr, uint size, u32 data);
/* Indicate if last reg read/write failed */ /* Indicate if last reg read/write failed */
extern bool bcmsdh_regfail(void *sdh); extern bool bcmsdh_regfail(void *sdh);
...@@ -118,10 +118,10 @@ extern bool bcmsdh_regfail(void *sdh); ...@@ -118,10 +118,10 @@ extern bool bcmsdh_regfail(void *sdh);
* NOTE: Async operation is not currently supported. * NOTE: Async operation is not currently supported.
*/ */
typedef void (*bcmsdh_cmplt_fn_t) (void *handle, int status, bool sync_waiting); typedef void (*bcmsdh_cmplt_fn_t) (void *handle, int status, bool sync_waiting);
extern int bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags, extern int bcmsdh_send_buf(void *sdh, u32 addr, uint fn, uint flags,
u8 *buf, uint nbytes, void *pkt, u8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle); bcmsdh_cmplt_fn_t complete, void *handle);
extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags, extern int bcmsdh_recv_buf(void *sdh, u32 addr, uint fn, uint flags,
u8 *buf, uint nbytes, void *pkt, u8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete, void *handle); bcmsdh_cmplt_fn_t complete, void *handle);
...@@ -140,7 +140,7 @@ extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags, ...@@ -140,7 +140,7 @@ extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
* nbytes: number of bytes to transfer to/from buf * nbytes: number of bytes to transfer to/from buf
* Returns 0 or error code. * Returns 0 or error code.
*/ */
extern int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, u8 *buf, extern int bcmsdh_rwdata(void *sdh, uint rw, u32 addr, u8 *buf,
uint nbytes); uint nbytes);
/* Issue an abort to the specified function */ /* Issue an abort to the specified function */
...@@ -187,12 +187,12 @@ extern bool bcmsdh_chipmatch(u16 vendor, u16 device); ...@@ -187,12 +187,12 @@ extern bool bcmsdh_chipmatch(u16 vendor, u16 device);
extern void bcmsdh_device_remove(void *sdh); extern void bcmsdh_device_remove(void *sdh);
/* Function to pass device-status bits to DHD. */ /* Function to pass device-status bits to DHD. */
extern uint32 bcmsdh_get_dstatus(void *sdh); extern u32 bcmsdh_get_dstatus(void *sdh);
/* Function to return current window addr */ /* Function to return current window addr */
extern uint32 bcmsdh_cur_sbwad(void *sdh); extern u32 bcmsdh_cur_sbwad(void *sdh);
/* Function to pass chipid and rev to lower layers for controlling pr's */ /* Function to pass chipid and rev to lower layers for controlling pr's */
extern void bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev); extern void bcmsdh_chipinfo(void *sdh, u32 chip, u32 chiprev);
#endif /* _bcmsdh_h_ */ #endif /* _bcmsdh_h_ */
drivers/staging/brcm80211/include/bcmsdh_sdmmc.h
浏览文件 @ 66cbd3ab
...@@ -68,8 +68,8 @@ struct sdioh_info { ...@@ -68,8 +68,8 @@ struct sdioh_info {
int sd_mode; /* SD1/SD4/SPI */ int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */ int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
u8 num_funcs; /* Supported funcs on client */ u8 num_funcs; /* Supported funcs on client */
uint32 com_cis_ptr; u32 com_cis_ptr;
uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS]; u32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
uint max_dma_len; uint max_dma_len;
uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */ uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */
/* SDDMA_DESCRIPTOR SGList[32]; *//* Scatter/Gather DMA List */ /* SDDMA_DESCRIPTOR SGList[32]; *//* Scatter/Gather DMA List */
...@@ -94,7 +94,7 @@ extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd); ...@@ -94,7 +94,7 @@ extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd);
*/ */
/* Register mapping routines */ /* Register mapping routines */
extern uint32 *sdioh_sdmmc_reg_map(osl_t *osh, int32 addr, int size); extern u32 *sdioh_sdmmc_reg_map(osl_t *osh, int32 addr, int size);
extern void sdioh_sdmmc_reg_unmap(osl_t *osh, int32 addr, int size); extern void sdioh_sdmmc_reg_unmap(osl_t *osh, int32 addr, int size);
/* Interrupt (de)registration routines */ /* Interrupt (de)registration routines */
...@@ -104,7 +104,7 @@ extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t *sd); ...@@ -104,7 +104,7 @@ extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t *sd);
typedef struct _BCMSDH_SDMMC_INSTANCE { typedef struct _BCMSDH_SDMMC_INSTANCE {
sdioh_info_t *sd; sdioh_info_t *sd;
struct sdio_func *func[SDIOD_MAX_IOFUNCS]; struct sdio_func *func[SDIOD_MAX_IOFUNCS];
uint32 host_claimed; u32 host_claimed;
} BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE; } BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE;
#endif /* __BCMSDH_SDMMC_H__ */ #endif /* __BCMSDH_SDMMC_H__ */
drivers/staging/brcm80211/include/bcmsdpcm.h
浏览文件 @ 66cbd3ab
...@@ -153,33 +153,33 @@ ...@@ -153,33 +153,33 @@
*/ */
typedef volatile struct { typedef volatile struct {
uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */ u32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */
uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */ u32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */
uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */ u32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */
uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */ u32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */
uint32 abort; /* AbortCount, SDIO: aborts */ u32 abort; /* AbortCount, SDIO: aborts */
uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */ u32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */
uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */ u32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */ u32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */ u32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */
uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */ u32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */
uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */ u32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */
uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */ u32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */
uint32 rxdescuflo; /* receive descriptor underflows */ u32 rxdescuflo; /* receive descriptor underflows */
uint32 rxfifooflo; /* receive fifo overflows */ u32 rxfifooflo; /* receive fifo overflows */
uint32 txfifouflo; /* transmit fifo underflows */ u32 txfifouflo; /* transmit fifo underflows */
uint32 runt; /* runt (too short) frames recv'd from bus */ u32 runt; /* runt (too short) frames recv'd from bus */
uint32 badlen; /* frame's rxh len does not match its hw tag len */ u32 badlen; /* frame's rxh len does not match its hw tag len */
uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */ u32 badcksum; /* frame's hw tag chksum doesn't agree with len value */
uint32 seqbreak; /* break in sequence # space from one rx frame to the next */ u32 seqbreak; /* break in sequence # space from one rx frame to the next */
uint32 rxfcrc; /* frame rx header indicates crc error */ u32 rxfcrc; /* frame rx header indicates crc error */
uint32 rxfwoos; /* frame rx header indicates write out of sync */ u32 rxfwoos; /* frame rx header indicates write out of sync */
uint32 rxfwft; /* frame rx header indicates write frame termination */ u32 rxfwft; /* frame rx header indicates write frame termination */
uint32 rxfabort; /* frame rx header indicates frame aborted */ u32 rxfabort; /* frame rx header indicates frame aborted */
uint32 woosint; /* write out of sync interrupt */ u32 woosint; /* write out of sync interrupt */
uint32 roosint; /* read out of sync interrupt */ u32 roosint; /* read out of sync interrupt */
uint32 rftermint; /* read frame terminate interrupt */ u32 rftermint; /* read frame terminate interrupt */
uint32 wftermint; /* write frame terminate interrupt */ u32 wftermint; /* write frame terminate interrupt */
} sdpcmd_cnt_t; } sdpcmd_cnt_t;
/* /*
...@@ -241,13 +241,13 @@ typedef volatile struct { ...@@ -241,13 +241,13 @@ typedef volatile struct {
#define SDPCM_SHARED_TRAP 0x0400 #define SDPCM_SHARED_TRAP 0x0400
typedef struct { typedef struct {
uint32 flags; u32 flags;
uint32 trap_addr; u32 trap_addr;
uint32 assert_exp_addr; u32 assert_exp_addr;
uint32 assert_file_addr; u32 assert_file_addr;
uint32 assert_line; u32 assert_line;
uint32 console_addr; /* Address of hndrte_cons_t */ u32 console_addr; /* Address of hndrte_cons_t */
uint32 msgtrace_addr; u32 msgtrace_addr;
} sdpcm_shared_t; } sdpcm_shared_t;
extern sdpcm_shared_t sdpcm_shared; extern sdpcm_shared_t sdpcm_shared;
......
drivers/staging/brcm80211/include/bcmsrom_tbl.h
浏览文件 @ 66cbd3ab
...@@ -22,8 +22,8 @@ ...@@ -22,8 +22,8 @@
typedef struct { typedef struct {
const char *name; const char *name;
uint32 revmask; u32 revmask;
uint32 flags; u32 flags;
u16 off; u16 off;
u16 mask; u16 mask;
} sromvar_t; } sromvar_t;
......
drivers/staging/brcm80211/include/bcmutils.h
浏览文件 @ 66cbd3ab
...@@ -327,7 +327,7 @@ extern "C" { ...@@ -327,7 +327,7 @@ extern "C" {
"s16", \ "s16", \
"u16", \ "u16", \
"int32", \ "int32", \
"uint32", \ "u32", \
"buffer", \ "buffer", \
"" } "" }
...@@ -517,7 +517,7 @@ extern "C" { ...@@ -517,7 +517,7 @@ extern "C" {
/* bcm_format_flags() bit description structure */ /* bcm_format_flags() bit description structure */
typedef struct bcm_bit_desc { typedef struct bcm_bit_desc {
uint32 bit; u32 bit;
const char *name; const char *name;
} bcm_bit_desc_t; } bcm_bit_desc_t;
...@@ -546,17 +546,17 @@ extern "C" { ...@@ -546,17 +546,17 @@ extern "C" {
3) == 0) { 3) == 0) {
/* ARM CM3 rel time: 1229 (727 if alignment check could be omitted) */ /* ARM CM3 rel time: 1229 (727 if alignment check could be omitted) */
/* x86 supports unaligned. This version runs 6x-9x faster on x86. */ /* x86 supports unaligned. This version runs 6x-9x faster on x86. */
((uint32 *) dst)[0] = ((u32 *) dst)[0] =
((const uint32 *)src1)[0] ^ ((const uint32 *) ((const u32 *)src1)[0] ^ ((const u32 *)
src2)[0]; src2)[0];
((uint32 *) dst)[1] = ((u32 *) dst)[1] =
((const uint32 *)src1)[1] ^ ((const uint32 *) ((const u32 *)src1)[1] ^ ((const u32 *)
src2)[1]; src2)[1];
((uint32 *) dst)[2] = ((u32 *) dst)[2] =
((const uint32 *)src1)[2] ^ ((const uint32 *) ((const u32 *)src1)[2] ^ ((const u32 *)
src2)[2]; src2)[2];
((uint32 *) dst)[3] = ((u32 *) dst)[3] =
((const uint32 *)src1)[3] ^ ((const uint32 *) ((const u32 *)src1)[3] ^ ((const u32 *)
src2)[3]; src2)[3];
} else { } else {
/* ARM CM3 rel time: 4668 (4191 if alignment check could be omitted) */ /* ARM CM3 rel time: 4668 (4191 if alignment check could be omitted) */
...@@ -572,7 +572,7 @@ extern "C" { ...@@ -572,7 +572,7 @@ extern "C" {
extern u16 BCMROMFN(hndcrc16) (u8 *p, uint nbytes, u16 crc); extern u16 BCMROMFN(hndcrc16) (u8 *p, uint nbytes, u16 crc);
/* format/print */ /* format/print */
#if defined(BCMDBG) #if defined(BCMDBG)
extern int bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, extern int bcm_format_flags(const bcm_bit_desc_t *bd, u32 flags,
char *buf, int len); char *buf, int len);
extern int bcm_format_hex(char *str, const void *bytes, int len); extern int bcm_format_hex(char *str, const void *bytes, int len);
#endif #endif
...@@ -584,7 +584,7 @@ extern "C" { ...@@ -584,7 +584,7 @@ extern "C" {
#endif /* BRCM_FULLMAC */ #endif /* BRCM_FULLMAC */
extern char *bcm_chipname(uint chipid, char *buf, uint len); extern char *bcm_chipname(uint chipid, char *buf, uint len);
#ifdef BRCM_FULLMAC #ifdef BRCM_FULLMAC
extern char *bcm_brev_str(uint32 brev, char *buf); extern char *bcm_brev_str(u32 brev, char *buf);
extern void printbig(char *buf); extern void printbig(char *buf);
#endif /* BRCM_FULLMAC */ #endif /* BRCM_FULLMAC */
extern void prhex(const char *msg, unsigned char *buf, uint len); extern void prhex(const char *msg, unsigned char *buf, uint len);
...@@ -604,7 +604,7 @@ extern "C" { ...@@ -604,7 +604,7 @@ extern "C" {
#endif #endif
/* multi-bool data type: set of bools, mbool is true if any is set */ /* multi-bool data type: set of bools, mbool is true if any is set */
typedef uint32 mbool; typedef u32 mbool;
#define mboolset(mb, bit) ((mb) |= (bit)) /* set one bool */ #define mboolset(mb, bit) ((mb) |= (bit)) /* set one bool */
#define mboolclr(mb, bit) ((mb) &= ~(bit)) /* clear one bool */ #define mboolclr(mb, bit) ((mb) &= ~(bit)) /* clear one bool */
#define mboolisset(mb, bit) (((mb) & (bit)) != 0) /* TRUE if one bool is set */ #define mboolisset(mb, bit) (((mb) & (bit)) != 0) /* TRUE if one bool is set */
...@@ -619,8 +619,8 @@ extern "C" { ...@@ -619,8 +619,8 @@ extern "C" {
/* generic datastruct to help dump routines */ /* generic datastruct to help dump routines */
struct fielddesc { struct fielddesc {
const char *nameandfmt; const char *nameandfmt;
uint32 offset; u32 offset;
uint32 len; u32 len;
}; };
#ifdef BRCM_FULLMAC #ifdef BRCM_FULLMAC
...@@ -631,12 +631,12 @@ extern "C" { ...@@ -631,12 +631,12 @@ extern "C" {
extern void bcm_print_bytes(char *name, const unsigned char *cdata, int len); extern void bcm_print_bytes(char *name, const unsigned char *cdata, int len);
#endif #endif
typedef uint32(*bcmutl_rdreg_rtn) (void *arg0, uint arg1, typedef u32(*bcmutl_rdreg_rtn) (void *arg0, uint arg1,
uint32 offset); u32 offset);
#ifdef BRCM_FULLMAC #ifdef BRCM_FULLMAC
extern uint bcmdumpfields(bcmutl_rdreg_rtn func_ptr, void *arg0, extern uint bcmdumpfields(bcmutl_rdreg_rtn func_ptr, void *arg0,
uint arg1, struct fielddesc *str, char *buf, uint arg1, struct fielddesc *str, char *buf,
uint32 bufsize); u32 bufsize);
extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf,
uint len); uint len);
......
drivers/staging/brcm80211/include/d11.h
浏览文件 @ 66cbd3ab
...@@ -65,15 +65,15 @@ ...@@ -65,15 +65,15 @@
#define TX_CTL_FIFO TX_AC_VO_FIFO #define TX_CTL_FIFO TX_AC_VO_FIFO
typedef volatile struct { typedef volatile struct {
uint32 intstatus; u32 intstatus;
uint32 intmask; u32 intmask;
} intctrlregs_t; } intctrlregs_t;
/* read: 32-bit register that can be read as 32-bit or as 2 16-bit /* read: 32-bit register that can be read as 32-bit or as 2 16-bit
* write: only low 16b-it half can be written * write: only low 16b-it half can be written
*/ */
typedef volatile union { typedef volatile union {
uint32 pmqhostdata; /* read only! */ u32 pmqhostdata; /* read only! */
struct { struct {
u16 pmqctrlstatus; /* read/write */ u16 pmqctrlstatus; /* read/write */
u16 PAD; u16 PAD;
...@@ -107,74 +107,74 @@ typedef volatile struct { ...@@ -107,74 +107,74 @@ typedef volatile struct {
*/ */
typedef volatile struct _d11regs { typedef volatile struct _d11regs {
/* Device Control ("semi-standard host registers") */ /* Device Control ("semi-standard host registers") */
uint32 PAD[3]; /* 0x0 - 0x8 */ u32 PAD[3]; /* 0x0 - 0x8 */
uint32 biststatus; /* 0xC */ u32 biststatus; /* 0xC */
uint32 biststatus2; /* 0x10 */ u32 biststatus2; /* 0x10 */
uint32 PAD; /* 0x14 */ u32 PAD; /* 0x14 */
uint32 gptimer; /* 0x18 *//* for corerev >= 3 */ u32 gptimer; /* 0x18 *//* for corerev >= 3 */
uint32 usectimer; /* 0x1c *//* for corerev >= 26 */ u32 usectimer; /* 0x1c *//* for corerev >= 26 */
/* Interrupt Control *//* 0x20 */ /* Interrupt Control *//* 0x20 */
intctrlregs_t intctrlregs[8]; intctrlregs_t intctrlregs[8];
uint32 PAD[40]; /* 0x60 - 0xFC */ u32 PAD[40]; /* 0x60 - 0xFC */
/* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */ /* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */
uint32 intrcvlazy[4]; /* 0x100 - 0x10C */ u32 intrcvlazy[4]; /* 0x100 - 0x10C */
uint32 PAD[4]; /* 0x110 - 0x11c */ u32 PAD[4]; /* 0x110 - 0x11c */
uint32 maccontrol; /* 0x120 */ u32 maccontrol; /* 0x120 */
uint32 maccommand; /* 0x124 */ u32 maccommand; /* 0x124 */
uint32 macintstatus; /* 0x128 */ u32 macintstatus; /* 0x128 */
uint32 macintmask; /* 0x12C */ u32 macintmask; /* 0x12C */
/* Transmit Template Access */ /* Transmit Template Access */
uint32 tplatewrptr; /* 0x130 */ u32 tplatewrptr; /* 0x130 */
uint32 tplatewrdata; /* 0x134 */ u32 tplatewrdata; /* 0x134 */
uint32 PAD[2]; /* 0x138 - 0x13C */ u32 PAD[2]; /* 0x138 - 0x13C */
/* PMQ registers */ /* PMQ registers */
pmqreg_t pmqreg; /* 0x140 */ pmqreg_t pmqreg; /* 0x140 */
uint32 pmqpatl; /* 0x144 */ u32 pmqpatl; /* 0x144 */
uint32 pmqpath; /* 0x148 */ u32 pmqpath; /* 0x148 */
uint32 PAD; /* 0x14C */ u32 PAD; /* 0x14C */
uint32 chnstatus; /* 0x150 */ u32 chnstatus; /* 0x150 */
uint32 psmdebug; /* 0x154 *//* for corerev >= 3 */ u32 psmdebug; /* 0x154 *//* for corerev >= 3 */
uint32 phydebug; /* 0x158 *//* for corerev >= 3 */ u32 phydebug; /* 0x158 *//* for corerev >= 3 */
uint32 machwcap; /* 0x15C *//* Corerev >= 13 */ u32 machwcap; /* 0x15C *//* Corerev >= 13 */
/* Extended Internal Objects */ /* Extended Internal Objects */
uint32 objaddr; /* 0x160 */ u32 objaddr; /* 0x160 */
uint32 objdata; /* 0x164 */ u32 objdata; /* 0x164 */
uint32 PAD[2]; /* 0x168 - 0x16c */ u32 PAD[2]; /* 0x168 - 0x16c */
/* New txstatus registers on corerev >= 5 */ /* New txstatus registers on corerev >= 5 */
uint32 frmtxstatus; /* 0x170 */ u32 frmtxstatus; /* 0x170 */
uint32 frmtxstatus2; /* 0x174 */ u32 frmtxstatus2; /* 0x174 */
uint32 PAD[2]; /* 0x178 - 0x17c */ u32 PAD[2]; /* 0x178 - 0x17c */
/* New TSF host access on corerev >= 3 */ /* New TSF host access on corerev >= 3 */
uint32 tsf_timerlow; /* 0x180 */ u32 tsf_timerlow; /* 0x180 */
uint32 tsf_timerhigh; /* 0x184 */ u32 tsf_timerhigh; /* 0x184 */
uint32 tsf_cfprep; /* 0x188 */ u32 tsf_cfprep; /* 0x188 */
uint32 tsf_cfpstart; /* 0x18c */ u32 tsf_cfpstart; /* 0x18c */
uint32 tsf_cfpmaxdur32; /* 0x190 */ u32 tsf_cfpmaxdur32; /* 0x190 */
uint32 PAD[3]; /* 0x194 - 0x19c */ u32 PAD[3]; /* 0x194 - 0x19c */
uint32 maccontrol1; /* 0x1a0 */ u32 maccontrol1; /* 0x1a0 */
uint32 machwcap1; /* 0x1a4 */ u32 machwcap1; /* 0x1a4 */
uint32 PAD[14]; /* 0x1a8 - 0x1dc */ u32 PAD[14]; /* 0x1a8 - 0x1dc */
/* Clock control and hardware workarounds (corerev >= 13) */ /* Clock control and hardware workarounds (corerev >= 13) */
uint32 clk_ctl_st; /* 0x1e0 */ u32 clk_ctl_st; /* 0x1e0 */
uint32 hw_war; u32 hw_war;
uint32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are u32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are
* moved to clk_ctl_st for corerev >= 17 * moved to clk_ctl_st for corerev >= 17
*/ */
uint32 PAD[5]; /* 0x1ec - 0x1fc */ u32 PAD[5]; /* 0x1ec - 0x1fc */
/* 0x200-0x37F dma/pio registers */ /* 0x200-0x37F dma/pio registers */
volatile union { volatile union {
...@@ -185,14 +185,14 @@ typedef volatile struct _d11regs { ...@@ -185,14 +185,14 @@ typedef volatile struct _d11regs {
/* FIFO diagnostic port access */ /* FIFO diagnostic port access */
dma32diag_t dmafifo; /* 0x380 - 0x38C */ dma32diag_t dmafifo; /* 0x380 - 0x38C */
uint32 aggfifocnt; /* 0x390 */ u32 aggfifocnt; /* 0x390 */
uint32 aggfifodata; /* 0x394 */ u32 aggfifodata; /* 0x394 */
uint32 PAD[16]; /* 0x398 - 0x3d4 */ u32 PAD[16]; /* 0x398 - 0x3d4 */
u16 radioregaddr; /* 0x3d8 */ u16 radioregaddr; /* 0x3d8 */
u16 radioregdata; /* 0x3da */ u16 radioregdata; /* 0x3da */
/* time delay between the change on rf disable input and radio shutdown corerev 10 */ /* time delay between the change on rf disable input and radio shutdown corerev 10 */
uint32 rfdisabledly; /* 0x3DC */ u32 rfdisabledly; /* 0x3DC */
/* PHY register access */ /* PHY register access */
u16 phyversion; /* 0x3e0 - 0x0 */ u16 phyversion; /* 0x3e0 - 0x0 */
...@@ -640,7 +640,7 @@ BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr { ...@@ -640,7 +640,7 @@ BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr {
#define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f) #define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
#define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01) #define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
#define D11A_PHY_HDR_GLENGTH(phdr) (((uint32 *)((phdr)->rlpt) >> 5) & 0x0fff) #define D11A_PHY_HDR_GLENGTH(phdr) (((u32 *)((phdr)->rlpt) >> 5) & 0x0fff)
#define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01) #define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
#define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f) #define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
...@@ -651,7 +651,7 @@ BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr { ...@@ -651,7 +651,7 @@ BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr {
#define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef) #define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
/* length is number of octets in PSDU */ /* length is number of octets in PSDU */
#define D11A_PHY_HDR_SLENGTH(phdr, length) \ #define D11A_PHY_HDR_SLENGTH(phdr, length) \
(*(uint32 *)((phdr)->rlpt) = *(uint32 *)((phdr)->rlpt) | \ (*(u32 *)((phdr)->rlpt) = *(u32 *)((phdr)->rlpt) | \
(((length) & 0x0fff) << 5)) (((length) & 0x0fff) << 5))
/* set the tail to all zeros */ /* set the tail to all zeros */
#define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03) #define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
...@@ -1330,7 +1330,7 @@ BWL_PRE_PACKED_STRUCT struct d11rxhdr { ...@@ -1330,7 +1330,7 @@ BWL_PRE_PACKED_STRUCT struct d11rxhdr {
typedef struct wlc_d11rxhdr wlc_d11rxhdr_t; typedef struct wlc_d11rxhdr wlc_d11rxhdr_t;
BWL_PRE_PACKED_STRUCT struct wlc_d11rxhdr { BWL_PRE_PACKED_STRUCT struct wlc_d11rxhdr {
d11rxhdr_t rxhdr; d11rxhdr_t rxhdr;
uint32 tsf_l; /* TSF_L reading */ u32 tsf_l; /* TSF_L reading */
s8 rssi; /* computed instanteneous rssi in BMAC */ s8 rssi; /* computed instanteneous rssi in BMAC */
s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */ s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */ s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
......
drivers/staging/brcm80211/include/dbus.h
浏览文件 @ 66cbd3ab
...@@ -111,10 +111,10 @@ typedef struct { ...@@ -111,10 +111,10 @@ typedef struct {
* Let upper layer account for packets/bytes * Let upper layer account for packets/bytes
*/ */
typedef struct { typedef struct {
uint32 rx_errors; u32 rx_errors;
uint32 tx_errors; u32 tx_errors;
uint32 rx_dropped; u32 rx_dropped;
uint32 tx_dropped; u32 tx_dropped;
} dbus_stats_t; } dbus_stats_t;
/* /*
...@@ -127,8 +127,8 @@ typedef struct { ...@@ -127,8 +127,8 @@ typedef struct {
struct dbus_callbacks; struct dbus_callbacks;
struct exec_parms; struct exec_parms;
typedef void *(*probe_cb_t) (void *arg, const char *desc, uint32 bustype, typedef void *(*probe_cb_t) (void *arg, const char *desc, u32 bustype,
uint32 hdrlen); u32 hdrlen);
typedef void (*disconnect_cb_t) (void *arg); typedef void (*disconnect_cb_t) (void *arg);
typedef void *(*exec_cb_t) (struct exec_parms *args); typedef void *(*exec_cb_t) (struct exec_parms *args);
...@@ -260,7 +260,7 @@ extern int dbus_get_config(const dbus_pub_t *pub, dbus_config_t *config); ...@@ -260,7 +260,7 @@ extern int dbus_get_config(const dbus_pub_t *pub, dbus_config_t *config);
extern void *dbus_pktget(const dbus_pub_t *pub, int len); extern void *dbus_pktget(const dbus_pub_t *pub, int len);
extern void dbus_pktfree(const dbus_pub_t *pub, void *pkt); extern void dbus_pktfree(const dbus_pub_t *pub, void *pkt);
extern int dbus_set_errmask(const dbus_pub_t *pub, uint32 mask); extern int dbus_set_errmask(const dbus_pub_t *pub, u32 mask);
extern int dbus_pnp_sleep(const dbus_pub_t *pub); extern int dbus_pnp_sleep(const dbus_pub_t *pub);
extern int dbus_pnp_resume(const dbus_pub_t *pub, int *fw_reload); extern int dbus_pnp_resume(const dbus_pub_t *pub, int *fw_reload);
extern int dbus_pnp_disconnect(const dbus_pub_t *pub); extern int dbus_pnp_disconnect(const dbus_pub_t *pub);
......
drivers/staging/brcm80211/include/hndpmu.h
浏览文件 @ 66cbd3ab
...@@ -30,17 +30,17 @@ ...@@ -30,17 +30,17 @@
extern void si_pmu_init(si_t *sih, osl_t *osh); extern void si_pmu_init(si_t *sih, osl_t *osh);
extern void si_pmu_chip_init(si_t *sih, osl_t *osh); extern void si_pmu_chip_init(si_t *sih, osl_t *osh);
extern void si_pmu_pll_init(si_t *sih, osl_t *osh, uint32 xtalfreq); extern void si_pmu_pll_init(si_t *sih, osl_t *osh, u32 xtalfreq);
extern void si_pmu_res_init(si_t *sih, osl_t *osh); extern void si_pmu_res_init(si_t *sih, osl_t *osh);
extern void si_pmu_swreg_init(si_t *sih, osl_t *osh); extern void si_pmu_swreg_init(si_t *sih, osl_t *osh);
extern uint32 si_pmu_force_ilp(si_t *sih, osl_t *osh, bool force); extern u32 si_pmu_force_ilp(si_t *sih, osl_t *osh, bool force);
extern uint32 si_pmu_si_clock(si_t *sih, osl_t *osh); extern u32 si_pmu_si_clock(si_t *sih, osl_t *osh);
extern uint32 si_pmu_cpu_clock(si_t *sih, osl_t *osh); extern u32 si_pmu_cpu_clock(si_t *sih, osl_t *osh);
extern uint32 si_pmu_mem_clock(si_t *sih, osl_t *osh); extern u32 si_pmu_mem_clock(si_t *sih, osl_t *osh);
extern uint32 si_pmu_alp_clock(si_t *sih, osl_t *osh); extern u32 si_pmu_alp_clock(si_t *sih, osl_t *osh);
extern uint32 si_pmu_ilp_clock(si_t *sih, osl_t *osh); extern u32 si_pmu_ilp_clock(si_t *sih, osl_t *osh);
extern void si_pmu_set_switcher_voltage(si_t *sih, osl_t *osh, extern void si_pmu_set_switcher_voltage(si_t *sih, osl_t *osh,
u8 bb_voltage, u8 rf_voltage); u8 bb_voltage, u8 rf_voltage);
...@@ -52,20 +52,20 @@ extern void si_pmu_pllupd(si_t *sih); ...@@ -52,20 +52,20 @@ extern void si_pmu_pllupd(si_t *sih);
extern void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid); extern void si_pmu_spuravoid(si_t *sih, osl_t *osh, u8 spuravoid);
extern bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh); extern bool si_pmu_is_otp_powered(si_t *sih, osl_t *osh);
extern uint32 si_pmu_measure_alpclk(si_t *sih, osl_t *osh); extern u32 si_pmu_measure_alpclk(si_t *sih, osl_t *osh);
extern uint32 si_pmu_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val); extern u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val);
extern uint32 si_pmu_regcontrol(si_t *sih, uint reg, uint32 mask, uint32 val); extern u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val);
extern uint32 si_pmu_pllcontrol(si_t *sih, uint reg, uint32 mask, uint32 val); extern u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val);
extern void si_pmu_pllupd(si_t *sih); extern void si_pmu_pllupd(si_t *sih);
extern void si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable); extern void si_pmu_sprom_enable(si_t *sih, osl_t *osh, bool enable);
extern void si_pmu_radio_enable(si_t *sih, bool enable); extern void si_pmu_radio_enable(si_t *sih, bool enable);
extern uint32 si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh, extern u32 si_pmu_waitforclk_on_backplane(si_t *sih, osl_t *osh,
uint32 clk, uint32 delay); u32 clk, u32 delay);
extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on); extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on);
extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh,
uint32 drivestrength); u32 drivestrength);
#endif /* _hndpmu_h_ */ #endif /* _hndpmu_h_ */
drivers/staging/brcm80211/include/hndrte_armtrap.h
浏览文件 @ 66cbd3ab
...@@ -50,26 +50,26 @@ ...@@ -50,26 +50,26 @@
#include <typedefs.h> #include <typedefs.h>
typedef struct _trap_struct { typedef struct _trap_struct {
uint32 type; u32 type;
uint32 epc; u32 epc;
uint32 cpsr; u32 cpsr;
uint32 spsr; u32 spsr;
uint32 r0; u32 r0;
uint32 r1; u32 r1;
uint32 r2; u32 r2;
uint32 r3; u32 r3;
uint32 r4; u32 r4;
uint32 r5; u32 r5;
uint32 r6; u32 r6;
uint32 r7; u32 r7;
uint32 r8; u32 r8;
uint32 r9; u32 r9;
uint32 r10; u32 r10;
uint32 r11; u32 r11;
uint32 r12; u32 r12;
uint32 r13; u32 r13;
uint32 r14; u32 r14;
uint32 pc; u32 pc;
} trap_t; } trap_t;
#endif /* !_LANGUAGE_ASSEMBLY */ #endif /* !_LANGUAGE_ASSEMBLY */
......
drivers/staging/brcm80211/include/hndrte_cons.h
浏览文件 @ 66cbd3ab
...@@ -21,7 +21,7 @@ ...@@ -21,7 +21,7 @@
#define LOG_BUF_LEN 1024 #define LOG_BUF_LEN 1024
typedef struct { typedef struct {
uint32 buf; /* Can't be pointer on (64-bit) hosts */ u32 buf; /* Can't be pointer on (64-bit) hosts */
uint buf_size; uint buf_size;
uint idx; uint idx;
char *_buf_compat; /* Redundant pointer for backward compat. */ char *_buf_compat; /* Redundant pointer for backward compat. */
......
drivers/staging/brcm80211/include/linux_osl.h
浏览文件 @ 66cbd3ab
...@@ -30,7 +30,7 @@ extern void osl_os_close_image(void *image); ...@@ -30,7 +30,7 @@ extern void osl_os_close_image(void *image);
extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag); extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag);
extern void osl_detach(osl_t *osh); extern void osl_detach(osl_t *osh);
extern uint32 g_assert_type; extern u32 g_assert_type;
#if defined(BCMDBG_ASSERT) #if defined(BCMDBG_ASSERT)
#define ASSERT(exp) \ #define ASSERT(exp) \
...@@ -57,7 +57,7 @@ extern void osl_delay(uint usec); ...@@ -57,7 +57,7 @@ extern void osl_delay(uint usec);
osl_pci_read_config((osh), (offset), (size)) osl_pci_read_config((osh), (offset), (size))
#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \ #define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
osl_pci_write_config((osh), (offset), (size), (val)) osl_pci_write_config((osh), (offset), (size), (val))
extern uint32 osl_pci_read_config(osl_t *osh, uint offset, uint size); extern u32 osl_pci_read_config(osl_t *osh, uint offset, uint size);
extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val); extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
/* PCI device bus # and slot # */ /* PCI device bus # and slot # */
...@@ -165,7 +165,7 @@ extern int osl_error(int bcmerror); ...@@ -165,7 +165,7 @@ extern int osl_error(int bcmerror);
/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */ /* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
#define PKTBUFSZ 2048 /* largest reasonable packet buffer, driver uses for ethernet MTU */ #define PKTBUFSZ 2048 /* largest reasonable packet buffer, driver uses for ethernet MTU */
#define OSL_SYSUPTIME() ((uint32)jiffies * (1000 / HZ)) #define OSL_SYSUPTIME() ((u32)jiffies * (1000 / HZ))
#define printf(fmt, args...) printk(fmt , ## args) #define printf(fmt, args...) printk(fmt , ## args)
#ifdef BRCM_FULLMAC #ifdef BRCM_FULLMAC
#include <linux/kernel.h> /* for vsn/printf's */ #include <linux/kernel.h> /* for vsn/printf's */
...@@ -184,7 +184,7 @@ extern int osl_error(int bcmerror); ...@@ -184,7 +184,7 @@ extern int osl_error(int bcmerror);
#define R_REG(osh, r) (\ #define R_REG(osh, r) (\
SELECT_BUS_READ(osh, sizeof(*(r)) == sizeof(u8) ? readb((volatile u8*)(r)) : \ SELECT_BUS_READ(osh, sizeof(*(r)) == sizeof(u8) ? readb((volatile u8*)(r)) : \
sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \ sizeof(*(r)) == sizeof(u16) ? readw((volatile u16*)(r)) : \
readl((volatile uint32*)(r)), OSL_READ_REG(osh, r)) \ readl((volatile u32*)(r)), OSL_READ_REG(osh, r)) \
) )
#else /* __mips__ */ #else /* __mips__ */
#define R_REG(osh, r) (\ #define R_REG(osh, r) (\
...@@ -199,9 +199,9 @@ extern int osl_error(int bcmerror); ...@@ -199,9 +199,9 @@ extern int osl_error(int bcmerror);
case sizeof(u16): \ case sizeof(u16): \
__osl_v = readw((volatile u16*)(r)); \ __osl_v = readw((volatile u16*)(r)); \
break; \ break; \
case sizeof(uint32): \ case sizeof(u32): \
__osl_v = \ __osl_v = \
readl((volatile uint32*)(r)); \ readl((volatile u32*)(r)); \
break; \ break; \
} \ } \
__asm__ __volatile__("sync"); \ __asm__ __volatile__("sync"); \
...@@ -224,8 +224,8 @@ extern int osl_error(int bcmerror); ...@@ -224,8 +224,8 @@ extern int osl_error(int bcmerror);
writeb((u8)(v), (volatile u8*)(r)); break; \ writeb((u8)(v), (volatile u8*)(r)); break; \
case sizeof(u16): \ case sizeof(u16): \
writew((u16)(v), (volatile u16*)(r)); break; \ writew((u16)(v), (volatile u16*)(r)); break; \
case sizeof(uint32): \ case sizeof(u32): \
writel((uint32)(v), (volatile uint32*)(r)); break; \ writel((u32)(v), (volatile u32*)(r)); break; \
}, \ }, \
(OSL_WRITE_REG(osh, r, v))); \ (OSL_WRITE_REG(osh, r, v))); \
} while (0) } while (0)
...@@ -243,8 +243,8 @@ extern int osl_error(int bcmerror); ...@@ -243,8 +243,8 @@ extern int osl_error(int bcmerror);
__osl_v = \ __osl_v = \
readw((volatile u16*)((uintptr)(r)^2)); \ readw((volatile u16*)((uintptr)(r)^2)); \
break; \ break; \
case sizeof(uint32): \ case sizeof(u32): \
__osl_v = readl((volatile uint32*)(r)); \ __osl_v = readl((volatile u32*)(r)); \
break; \ break; \
} \ } \
__osl_v; \ __osl_v; \
...@@ -260,9 +260,9 @@ extern int osl_error(int bcmerror); ...@@ -260,9 +260,9 @@ extern int osl_error(int bcmerror);
case sizeof(u16): \ case sizeof(u16): \
writew((u16)(v), \ writew((u16)(v), \
(volatile u16*)((uintptr)(r)^2)); break; \ (volatile u16*)((uintptr)(r)^2)); break; \
case sizeof(uint32): \ case sizeof(u32): \
writel((uint32)(v), \ writel((u32)(v), \
(volatile uint32*)(r)); break; \ (volatile u32*)(r)); break; \
}, \ }, \
(OSL_WRITE_REG(osh, r, v))); \ (OSL_WRITE_REG(osh, r, v))); \
} while (0) } while (0)
...@@ -402,7 +402,7 @@ osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt) ...@@ -402,7 +402,7 @@ osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt)
#define RPC_READ_REG(osh, r) (\ #define RPC_READ_REG(osh, r) (\
sizeof(*(r)) == sizeof(u8) ? osl_readb((osh), (volatile u8*)(r)) : \ sizeof(*(r)) == sizeof(u8) ? osl_readb((osh), (volatile u8*)(r)) : \
sizeof(*(r)) == sizeof(u16) ? osl_readw((osh), (volatile u16*)(r)) : \ sizeof(*(r)) == sizeof(u16) ? osl_readw((osh), (volatile u16*)(r)) : \
osl_readl((osh), (volatile uint32*)(r)) \ osl_readl((osh), (volatile u32*)(r)) \
) )
#define RPC_WRITE_REG(osh, r, v) do { \ #define RPC_WRITE_REG(osh, r, v) do { \
switch (sizeof(*(r))) { \ switch (sizeof(*(r))) { \
...@@ -412,18 +412,18 @@ osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt) ...@@ -412,18 +412,18 @@ osl_pkt_tonative(osl_pubinfo_t *osh, void *pkt)
case sizeof(u16): \ case sizeof(u16): \
osl_writew((osh), (volatile u16*)(r), (u16)(v)); \ osl_writew((osh), (volatile u16*)(r), (u16)(v)); \
break; \ break; \
case sizeof(uint32): \ case sizeof(u32): \
osl_writel((osh), (volatile uint32*)(r), (uint32)(v)); \ osl_writel((osh), (volatile u32*)(r), (u32)(v)); \
break; \ break; \
} \ } \
} while (0) } while (0)
extern u8 osl_readb(osl_t *osh, volatile u8 *r); extern u8 osl_readb(osl_t *osh, volatile u8 *r);
extern u16 osl_readw(osl_t *osh, volatile u16 *r); extern u16 osl_readw(osl_t *osh, volatile u16 *r);
extern uint32 osl_readl(osl_t *osh, volatile uint32 *r); extern u32 osl_readl(osl_t *osh, volatile u32 *r);
extern void osl_writeb(osl_t *osh, volatile u8 *r, u8 v); extern void osl_writeb(osl_t *osh, volatile u8 *r, u8 v);
extern void osl_writew(osl_t *osh, volatile u16 *r, u16 v); extern void osl_writew(osl_t *osh, volatile u16 *r, u16 v);
extern void osl_writel(osl_t *osh, volatile uint32 *r, uint32 v); extern void osl_writel(osl_t *osh, volatile u32 *r, u32 v);
#endif /* BCMSDIO */ #endif /* BCMSDIO */
#endif /* _linux_osl_h_ */ #endif /* _linux_osl_h_ */
drivers/staging/brcm80211/include/msgtrace.h
浏览文件 @ 66cbd3ab
...@@ -29,14 +29,14 @@ typedef BWL_PRE_PACKED_STRUCT struct msgtrace_hdr { ...@@ -29,14 +29,14 @@ typedef BWL_PRE_PACKED_STRUCT struct msgtrace_hdr {
u8 version; u8 version;
u8 spare; u8 spare;
u16 len; /* Len of the trace */ u16 len; /* Len of the trace */
uint32 seqnum; /* Sequence number of message. Useful u32 seqnum; /* Sequence number of message. Useful
* if the messsage has been lost * if the messsage has been lost
* because of DMA error or a bus reset * because of DMA error or a bus reset
* (ex: SDIO Func2) * (ex: SDIO Func2)
*/ */
uint32 discarded_bytes; /* Number of discarded bytes because of u32 discarded_bytes; /* Number of discarded bytes because of
trace overflow */ trace overflow */
uint32 discarded_printf; /* Number of discarded printf u32 discarded_printf; /* Number of discarded printf
because of trace overflow */ because of trace overflow */
} BWL_POST_PACKED_STRUCT msgtrace_hdr_t; } BWL_POST_PACKED_STRUCT msgtrace_hdr_t;
......
drivers/staging/brcm80211/include/nicpci.h
浏览文件 @ 66cbd3ab
...@@ -46,14 +46,14 @@ ...@@ -46,14 +46,14 @@
struct sbpcieregs; struct sbpcieregs;
extern u8 pcicore_find_pci_capability(osl_t *osh, u8 req_cap_id, extern u8 pcicore_find_pci_capability(osl_t *osh, u8 req_cap_id,
unsigned char *buf, uint32 *buflen); unsigned char *buf, u32 *buflen);
extern uint pcie_readreg(osl_t *osh, struct sbpcieregs *pcieregs, extern uint pcie_readreg(osl_t *osh, struct sbpcieregs *pcieregs,
uint addrtype, uint offset); uint addrtype, uint offset);
extern uint pcie_writereg(osl_t *osh, struct sbpcieregs *pcieregs, extern uint pcie_writereg(osl_t *osh, struct sbpcieregs *pcieregs,
uint addrtype, uint offset, uint val); uint addrtype, uint offset, uint val);
extern u8 pcie_clkreq(void *pch, uint32 mask, uint32 val); extern u8 pcie_clkreq(void *pch, u32 mask, u32 val);
extern uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val); extern u32 pcie_lcreg(void *pch, u32 mask, u32 val);
extern void *pcicore_init(si_t *sih, osl_t *osh, void *regs); extern void *pcicore_init(si_t *sih, osl_t *osh, void *regs);
extern void pcicore_deinit(void *pch); extern void pcicore_deinit(void *pch);
...@@ -64,11 +64,11 @@ extern void pcicore_sleep(void *pch); ...@@ -64,11 +64,11 @@ extern void pcicore_sleep(void *pch);
extern void pcicore_down(void *pch, int state); extern void pcicore_down(void *pch, int state);
extern void pcie_war_ovr_aspm_update(void *pch, u8 aspm); extern void pcie_war_ovr_aspm_update(void *pch, u8 aspm);
extern uint32 pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset, extern u32 pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset,
uint32 mask, uint32 val); u32 mask, u32 val);
extern uint32 pcicore_pciereg(void *pch, uint32 offset, uint32 mask, extern u32 pcicore_pciereg(void *pch, u32 offset, u32 mask,
uint32 val, uint type); u32 val, uint type);
extern bool pcicore_pmecap_fast(osl_t *osh); extern bool pcicore_pmecap_fast(osl_t *osh);
extern void pcicore_pmeen(void *pch); extern void pcicore_pmeen(void *pch);
......
drivers/staging/brcm80211/include/pci_core.h
浏览文件 @ 66cbd3ab
...@@ -28,30 +28,30 @@ ...@@ -28,30 +28,30 @@
/* Sonics side: PCI core and host control registers */ /* Sonics side: PCI core and host control registers */
typedef struct sbpciregs { typedef struct sbpciregs {
uint32 control; /* PCI control */ u32 control; /* PCI control */
uint32 PAD[3]; u32 PAD[3];
uint32 arbcontrol; /* PCI arbiter control */ u32 arbcontrol; /* PCI arbiter control */
uint32 clkrun; /* Clkrun Control (>=rev11) */ u32 clkrun; /* Clkrun Control (>=rev11) */
uint32 PAD[2]; u32 PAD[2];
uint32 intstatus; /* Interrupt status */ u32 intstatus; /* Interrupt status */
uint32 intmask; /* Interrupt mask */ u32 intmask; /* Interrupt mask */
uint32 sbtopcimailbox; /* Sonics to PCI mailbox */ u32 sbtopcimailbox; /* Sonics to PCI mailbox */
uint32 PAD[9]; u32 PAD[9];
uint32 bcastaddr; /* Sonics broadcast address */ u32 bcastaddr; /* Sonics broadcast address */
uint32 bcastdata; /* Sonics broadcast data */ u32 bcastdata; /* Sonics broadcast data */
uint32 PAD[2]; u32 PAD[2];
uint32 gpioin; /* ro: gpio input (>=rev2) */ u32 gpioin; /* ro: gpio input (>=rev2) */
uint32 gpioout; /* rw: gpio output (>=rev2) */ u32 gpioout; /* rw: gpio output (>=rev2) */
uint32 gpioouten; /* rw: gpio output enable (>= rev2) */ u32 gpioouten; /* rw: gpio output enable (>= rev2) */
uint32 gpiocontrol; /* rw: gpio control (>= rev2) */ u32 gpiocontrol; /* rw: gpio control (>= rev2) */
uint32 PAD[36]; u32 PAD[36];
uint32 sbtopci0; /* Sonics to PCI translation 0 */ u32 sbtopci0; /* Sonics to PCI translation 0 */
uint32 sbtopci1; /* Sonics to PCI translation 1 */ u32 sbtopci1; /* Sonics to PCI translation 1 */
uint32 sbtopci2; /* Sonics to PCI translation 2 */ u32 sbtopci2; /* Sonics to PCI translation 2 */
uint32 PAD[189]; u32 PAD[189];
uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */ u32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
u16 sprom[36]; /* SPROM shadow Area */ u16 sprom[36]; /* SPROM shadow Area */
uint32 PAD[46]; u32 PAD[46];
} sbpciregs_t; } sbpciregs_t;
#endif /* _LANGUAGE_ASSEMBLY */ #endif /* _LANGUAGE_ASSEMBLY */
......
drivers/staging/brcm80211/include/pcicfg.h
浏览文件 @ 66cbd3ab
...@@ -115,12 +115,12 @@ typedef struct _pci_config_regs { ...@@ -115,12 +115,12 @@ typedef struct _pci_config_regs {
u8 latency_timer; u8 latency_timer;
u8 header_type; u8 header_type;
u8 bist; u8 bist;
uint32 base[PCI_BAR_MAX]; u32 base[PCI_BAR_MAX];
uint32 cardbus_cis; u32 cardbus_cis;
u16 subsys_vendor; u16 subsys_vendor;
u16 subsys_id; u16 subsys_id;
uint32 baserom; u32 baserom;
uint32 rsvd_a[PCR_RSVDA_MAX]; u32 rsvd_a[PCR_RSVDA_MAX];
u8 int_line; u8 int_line;
u8 int_pin; u8 int_pin;
u8 min_gnt; u8 min_gnt;
...@@ -343,7 +343,7 @@ typedef struct _ppb_config_regs { ...@@ -343,7 +343,7 @@ typedef struct _ppb_config_regs {
u8 latency_timer; u8 latency_timer;
u8 header_type; u8 header_type;
u8 bist; u8 bist;
uint32 rsvd_a[PPB_RSVDA_MAX]; u32 rsvd_a[PPB_RSVDA_MAX];
u8 prim_bus; u8 prim_bus;
u8 sec_bus; u8 sec_bus;
u8 sub_bus; u8 sub_bus;
...@@ -355,20 +355,20 @@ typedef struct _ppb_config_regs { ...@@ -355,20 +355,20 @@ typedef struct _ppb_config_regs {
u16 mem_lim; u16 mem_lim;
u16 pf_mem_base; u16 pf_mem_base;
u16 pf_mem_lim; u16 pf_mem_lim;
uint32 pf_mem_base_hi; u32 pf_mem_base_hi;
uint32 pf_mem_lim_hi; u32 pf_mem_lim_hi;
u16 io_base_hi; u16 io_base_hi;
u16 io_lim_hi; u16 io_lim_hi;
u16 subsys_vendor; u16 subsys_vendor;
u16 subsys_id; u16 subsys_id;
uint32 rsvd_b; u32 rsvd_b;
u8 rsvd_c; u8 rsvd_c;
u8 int_pin; u8 int_pin;
u16 bridge_ctrl; u16 bridge_ctrl;
u8 chip_ctrl; u8 chip_ctrl;
u8 diag_ctrl; u8 diag_ctrl;
u16 arb_ctrl; u16 arb_ctrl;
uint32 rsvd_d[PPB_RSVDD_MAX]; u32 rsvd_d[PPB_RSVDD_MAX];
u8 dev_dep[192]; u8 dev_dep[192];
} ppb_config_regs; } ppb_config_regs;
...@@ -385,7 +385,7 @@ typedef struct _pciconfig_cap_msi { ...@@ -385,7 +385,7 @@ typedef struct _pciconfig_cap_msi {
u8 capID; u8 capID;
u8 nextptr; u8 nextptr;
u16 msgctrl; u16 msgctrl;
uint32 msgaddr; u32 msgaddr;
} pciconfig_cap_msi; } pciconfig_cap_msi;
/* Data structure to define the Power managment facility /* Data structure to define the Power managment facility
...@@ -410,18 +410,18 @@ typedef struct _pciconfig_cap_pcie { ...@@ -410,18 +410,18 @@ typedef struct _pciconfig_cap_pcie {
u8 capID; u8 capID;
u8 nextptr; u8 nextptr;
u16 pcie_cap; u16 pcie_cap;
uint32 dev_cap; u32 dev_cap;
u16 dev_ctrl; u16 dev_ctrl;
u16 dev_status; u16 dev_status;
uint32 link_cap; u32 link_cap;
u16 link_ctrl; u16 link_ctrl;
u16 link_status; u16 link_status;
uint32 slot_cap; u32 slot_cap;
u16 slot_ctrl; u16 slot_ctrl;
u16 slot_status; u16 slot_status;
u16 root_ctrl; u16 root_ctrl;
u16 root_cap; u16 root_cap;
uint32 root_status; u32 root_status;
} pciconfig_cap_pcie; } pciconfig_cap_pcie;
/* PCIE Enhanced CAPABILITY DEFINES */ /* PCIE Enhanced CAPABILITY DEFINES */
......
drivers/staging/brcm80211/include/pcie_core.h
浏览文件 @ 66cbd3ab
...@@ -46,36 +46,36 @@ ...@@ -46,36 +46,36 @@
/* SB side: PCIE core and host control registers */ /* SB side: PCIE core and host control registers */
typedef struct sbpcieregs { typedef struct sbpcieregs {
uint32 control; /* host mode only */ u32 control; /* host mode only */
uint32 PAD[2]; u32 PAD[2];
uint32 biststatus; /* bist Status: 0x00C */ u32 biststatus; /* bist Status: 0x00C */
uint32 gpiosel; /* PCIE gpio sel: 0x010 */ u32 gpiosel; /* PCIE gpio sel: 0x010 */
uint32 gpioouten; /* PCIE gpio outen: 0x14 */ u32 gpioouten; /* PCIE gpio outen: 0x14 */
uint32 PAD[2]; u32 PAD[2];
uint32 intstatus; /* Interrupt status: 0x20 */ u32 intstatus; /* Interrupt status: 0x20 */
uint32 intmask; /* Interrupt mask: 0x24 */ u32 intmask; /* Interrupt mask: 0x24 */
uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */ u32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
uint32 PAD[53]; u32 PAD[53];
uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */ u32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */ u32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */ u32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
uint32 PAD[5]; u32 PAD[5];
/* pcie core supports in direct access to config space */ /* pcie core supports in direct access to config space */
uint32 configaddr; /* pcie config space access: Address field: 0x120 */ u32 configaddr; /* pcie config space access: Address field: 0x120 */
uint32 configdata; /* pcie config space access: Data field: 0x124 */ u32 configdata; /* pcie config space access: Data field: 0x124 */
/* mdio access to serdes */ /* mdio access to serdes */
uint32 mdiocontrol; /* controls the mdio access: 0x128 */ u32 mdiocontrol; /* controls the mdio access: 0x128 */
uint32 mdiodata; /* Data to the mdio access: 0x12c */ u32 mdiodata; /* Data to the mdio access: 0x12c */
/* pcie protocol phy/dllp/tlp register indirect access mechanism */ /* pcie protocol phy/dllp/tlp register indirect access mechanism */
uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */ u32 pcieindaddr; /* indirect access to the internal register: 0x130 */
uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */ u32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */ u32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
uint32 PAD[177]; u32 PAD[177];
uint32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */ u32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */
u16 sprom[64]; /* SPROM shadow Area */ u16 sprom[64]; /* SPROM shadow Area */
} sbpcieregs_t; } sbpcieregs_t;
......
drivers/staging/brcm80211/include/proto/802.11.h
浏览文件 @ 66cbd3ab
...@@ -81,7 +81,7 @@ BWL_PRE_PACKED_STRUCT struct dot11_management_header { ...@@ -81,7 +81,7 @@ BWL_PRE_PACKED_STRUCT struct dot11_management_header {
#define DOT11_MGMT_HDR_LEN 24 #define DOT11_MGMT_HDR_LEN 24
BWL_PRE_PACKED_STRUCT struct dot11_bcn_prb { BWL_PRE_PACKED_STRUCT struct dot11_bcn_prb {
uint32 timestamp[2]; u32 timestamp[2];
u16 beacon_interval; u16 beacon_interval;
u16 capability; u16 capability;
} BWL_POST_PACKED_STRUCT; } BWL_POST_PACKED_STRUCT;
...@@ -236,20 +236,20 @@ typedef struct wme_param_ie wme_param_ie_t; ...@@ -236,20 +236,20 @@ typedef struct wme_param_ie wme_param_ie_t;
#define DOT11_MAXNUMFRAGS 16 #define DOT11_MAXNUMFRAGS 16
typedef struct d11cnt { typedef struct d11cnt {
uint32 txfrag; u32 txfrag;
uint32 txmulti; u32 txmulti;
uint32 txfail; u32 txfail;
uint32 txretry; u32 txretry;
uint32 txretrie; u32 txretrie;
uint32 rxdup; u32 rxdup;
uint32 txrts; u32 txrts;
uint32 txnocts; u32 txnocts;
uint32 txnoack; u32 txnoack;
uint32 rxfrag; u32 rxfrag;
uint32 rxmulti; u32 rxmulti;
uint32 rxcrc; u32 rxcrc;
uint32 txfrmsnt; u32 txfrmsnt;
uint32 rxundec; u32 rxundec;
} d11cnt_t; } d11cnt_t;
#define MCSSET_LEN 16 #define MCSSET_LEN 16
...@@ -259,7 +259,7 @@ BWL_PRE_PACKED_STRUCT struct ht_cap_ie { ...@@ -259,7 +259,7 @@ BWL_PRE_PACKED_STRUCT struct ht_cap_ie {
u8 params; u8 params;
u8 supp_mcs[MCSSET_LEN]; u8 supp_mcs[MCSSET_LEN];
u16 ext_htcap; u16 ext_htcap;
uint32 txbf_cap; u32 txbf_cap;
u8 as_cap; u8 as_cap;
} BWL_POST_PACKED_STRUCT; } BWL_POST_PACKED_STRUCT;
typedef struct ht_cap_ie ht_cap_ie_t; typedef struct ht_cap_ie ht_cap_ie_t;
......
drivers/staging/brcm80211/include/proto/bcmevent.h
浏览文件 @ 66cbd3ab
...@@ -30,11 +30,11 @@ ...@@ -30,11 +30,11 @@
typedef BWL_PRE_PACKED_STRUCT struct { typedef BWL_PRE_PACKED_STRUCT struct {
u16 version; u16 version;
u16 flags; u16 flags;
uint32 event_type; u32 event_type;
uint32 status; u32 status;
uint32 reason; u32 reason;
uint32 auth_type; u32 auth_type;
uint32 datalen; u32 datalen;
struct ether_addr addr; struct ether_addr addr;
char ifname[BCM_MSG_IFNAME_MAX]; char ifname[BCM_MSG_IFNAME_MAX];
} BWL_POST_PACKED_STRUCT wl_event_msg_t; } BWL_POST_PACKED_STRUCT wl_event_msg_t;
......
drivers/staging/brcm80211/include/sbchipc.h
浏览文件 @ 66cbd3ab
...@@ -27,147 +27,147 @@ ...@@ -27,147 +27,147 @@
#endif /* PAD */ #endif /* PAD */
typedef volatile struct { typedef volatile struct {
uint32 chipid; /* 0x0 */ u32 chipid; /* 0x0 */
uint32 capabilities; u32 capabilities;
uint32 corecontrol; /* corerev >= 1 */ u32 corecontrol; /* corerev >= 1 */
uint32 bist; u32 bist;
/* OTP */ /* OTP */
uint32 otpstatus; /* 0x10, corerev >= 10 */ u32 otpstatus; /* 0x10, corerev >= 10 */
uint32 otpcontrol; u32 otpcontrol;
uint32 otpprog; u32 otpprog;
uint32 otplayout; /* corerev >= 23 */ u32 otplayout; /* corerev >= 23 */
/* Interrupt control */ /* Interrupt control */
uint32 intstatus; /* 0x20 */ u32 intstatus; /* 0x20 */
uint32 intmask; u32 intmask;
/* Chip specific regs */ /* Chip specific regs */
uint32 chipcontrol; /* 0x28, rev >= 11 */ u32 chipcontrol; /* 0x28, rev >= 11 */
uint32 chipstatus; /* 0x2c, rev >= 11 */ u32 chipstatus; /* 0x2c, rev >= 11 */
/* Jtag Master */ /* Jtag Master */
uint32 jtagcmd; /* 0x30, rev >= 10 */ u32 jtagcmd; /* 0x30, rev >= 10 */
uint32 jtagir; u32 jtagir;
uint32 jtagdr; u32 jtagdr;
uint32 jtagctrl; u32 jtagctrl;
/* serial flash interface registers */ /* serial flash interface registers */
uint32 flashcontrol; /* 0x40 */ u32 flashcontrol; /* 0x40 */
uint32 flashaddress; u32 flashaddress;
uint32 flashdata; u32 flashdata;
uint32 PAD[1]; u32 PAD[1];
/* Silicon backplane configuration broadcast control */ /* Silicon backplane configuration broadcast control */
uint32 broadcastaddress; /* 0x50 */ u32 broadcastaddress; /* 0x50 */
uint32 broadcastdata; u32 broadcastdata;
/* gpio - cleared only by power-on-reset */ /* gpio - cleared only by power-on-reset */
uint32 gpiopullup; /* 0x58, corerev >= 20 */ u32 gpiopullup; /* 0x58, corerev >= 20 */
uint32 gpiopulldown; /* 0x5c, corerev >= 20 */ u32 gpiopulldown; /* 0x5c, corerev >= 20 */
uint32 gpioin; /* 0x60 */ u32 gpioin; /* 0x60 */
uint32 gpioout; /* 0x64 */ u32 gpioout; /* 0x64 */
uint32 gpioouten; /* 0x68 */ u32 gpioouten; /* 0x68 */
uint32 gpiocontrol; /* 0x6C */ u32 gpiocontrol; /* 0x6C */
uint32 gpiointpolarity; /* 0x70 */ u32 gpiointpolarity; /* 0x70 */
uint32 gpiointmask; /* 0x74 */ u32 gpiointmask; /* 0x74 */
/* GPIO events corerev >= 11 */ /* GPIO events corerev >= 11 */
uint32 gpioevent; u32 gpioevent;
uint32 gpioeventintmask; u32 gpioeventintmask;
/* Watchdog timer */ /* Watchdog timer */
uint32 watchdog; /* 0x80 */ u32 watchdog; /* 0x80 */
/* GPIO events corerev >= 11 */ /* GPIO events corerev >= 11 */
uint32 gpioeventintpolarity; u32 gpioeventintpolarity;
/* GPIO based LED powersave registers corerev >= 16 */ /* GPIO based LED powersave registers corerev >= 16 */
uint32 gpiotimerval; /* 0x88 */ u32 gpiotimerval; /* 0x88 */
uint32 gpiotimeroutmask; u32 gpiotimeroutmask;
/* clock control */ /* clock control */
uint32 clockcontrol_n; /* 0x90 */ u32 clockcontrol_n; /* 0x90 */
uint32 clockcontrol_sb; /* aka m0 */ u32 clockcontrol_sb; /* aka m0 */
uint32 clockcontrol_pci; /* aka m1 */ u32 clockcontrol_pci; /* aka m1 */
uint32 clockcontrol_m2; /* mii/uart/mipsref */ u32 clockcontrol_m2; /* mii/uart/mipsref */
uint32 clockcontrol_m3; /* cpu */ u32 clockcontrol_m3; /* cpu */
uint32 clkdiv; /* corerev >= 3 */ u32 clkdiv; /* corerev >= 3 */
uint32 gpiodebugsel; /* corerev >= 28 */ u32 gpiodebugsel; /* corerev >= 28 */
uint32 capabilities_ext; /* 0xac */ u32 capabilities_ext; /* 0xac */
/* pll delay registers (corerev >= 4) */ /* pll delay registers (corerev >= 4) */
uint32 pll_on_delay; /* 0xb0 */ u32 pll_on_delay; /* 0xb0 */
uint32 fref_sel_delay; u32 fref_sel_delay;
uint32 slow_clk_ctl; /* 5 < corerev < 10 */ u32 slow_clk_ctl; /* 5 < corerev < 10 */
uint32 PAD; u32 PAD;
/* Instaclock registers (corerev >= 10) */ /* Instaclock registers (corerev >= 10) */
uint32 system_clk_ctl; /* 0xc0 */ u32 system_clk_ctl; /* 0xc0 */
uint32 clkstatestretch; u32 clkstatestretch;
uint32 PAD[2]; u32 PAD[2];
/* Indirect backplane access (corerev >= 22) */ /* Indirect backplane access (corerev >= 22) */
uint32 bp_addrlow; /* 0xd0 */ u32 bp_addrlow; /* 0xd0 */
uint32 bp_addrhigh; u32 bp_addrhigh;
uint32 bp_data; u32 bp_data;
uint32 PAD; u32 PAD;
uint32 bp_indaccess; u32 bp_indaccess;
uint32 PAD[3]; u32 PAD[3];
/* More clock dividers (corerev >= 32) */ /* More clock dividers (corerev >= 32) */
uint32 clkdiv2; u32 clkdiv2;
uint32 PAD[2]; u32 PAD[2];
/* In AI chips, pointer to erom */ /* In AI chips, pointer to erom */
uint32 eromptr; /* 0xfc */ u32 eromptr; /* 0xfc */
/* ExtBus control registers (corerev >= 3) */ /* ExtBus control registers (corerev >= 3) */
uint32 pcmcia_config; /* 0x100 */ u32 pcmcia_config; /* 0x100 */
uint32 pcmcia_memwait; u32 pcmcia_memwait;
uint32 pcmcia_attrwait; u32 pcmcia_attrwait;
uint32 pcmcia_iowait; u32 pcmcia_iowait;
uint32 ide_config; u32 ide_config;
uint32 ide_memwait; u32 ide_memwait;
uint32 ide_attrwait; u32 ide_attrwait;
uint32 ide_iowait; u32 ide_iowait;
uint32 prog_config; u32 prog_config;
uint32 prog_waitcount; u32 prog_waitcount;
uint32 flash_config; u32 flash_config;
uint32 flash_waitcount; u32 flash_waitcount;
uint32 SECI_config; /* 0x130 SECI configuration */ u32 SECI_config; /* 0x130 SECI configuration */
uint32 PAD[3]; u32 PAD[3];
/* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */ /* Enhanced Coexistence Interface (ECI) registers (corerev >= 21) */
uint32 eci_output; /* 0x140 */ u32 eci_output; /* 0x140 */
uint32 eci_control; u32 eci_control;
uint32 eci_inputlo; u32 eci_inputlo;
uint32 eci_inputmi; u32 eci_inputmi;
uint32 eci_inputhi; u32 eci_inputhi;
uint32 eci_inputintpolaritylo; u32 eci_inputintpolaritylo;
uint32 eci_inputintpolaritymi; u32 eci_inputintpolaritymi;
uint32 eci_inputintpolarityhi; u32 eci_inputintpolarityhi;
uint32 eci_intmasklo; u32 eci_intmasklo;
uint32 eci_intmaskmi; u32 eci_intmaskmi;
uint32 eci_intmaskhi; u32 eci_intmaskhi;
uint32 eci_eventlo; u32 eci_eventlo;
uint32 eci_eventmi; u32 eci_eventmi;
uint32 eci_eventhi; u32 eci_eventhi;
uint32 eci_eventmasklo; u32 eci_eventmasklo;
uint32 eci_eventmaskmi; u32 eci_eventmaskmi;
uint32 eci_eventmaskhi; u32 eci_eventmaskhi;
uint32 PAD[3]; u32 PAD[3];
/* SROM interface (corerev >= 32) */ /* SROM interface (corerev >= 32) */
uint32 sromcontrol; /* 0x190 */ u32 sromcontrol; /* 0x190 */
uint32 sromaddress; u32 sromaddress;
uint32 sromdata; u32 sromdata;
uint32 PAD[17]; u32 PAD[17];
/* Clock control and hardware workarounds (corerev >= 20) */ /* Clock control and hardware workarounds (corerev >= 20) */
uint32 clk_ctl_st; /* 0x1e0 */ u32 clk_ctl_st; /* 0x1e0 */
uint32 hw_war; u32 hw_war;
uint32 PAD[70]; u32 PAD[70];
/* UARTs */ /* UARTs */
u8 uart0data; /* 0x300 */ u8 uart0data; /* 0x300 */
...@@ -188,38 +188,38 @@ typedef volatile struct { ...@@ -188,38 +188,38 @@ typedef volatile struct {
u8 uart1lsr; u8 uart1lsr;
u8 uart1msr; u8 uart1msr;
u8 uart1scratch; u8 uart1scratch;
uint32 PAD[126]; u32 PAD[126];
/* PMU registers (corerev >= 20) */ /* PMU registers (corerev >= 20) */
uint32 pmucontrol; /* 0x600 */ u32 pmucontrol; /* 0x600 */
uint32 pmucapabilities; u32 pmucapabilities;
uint32 pmustatus; u32 pmustatus;
uint32 res_state; u32 res_state;
uint32 res_pending; u32 res_pending;
uint32 pmutimer; u32 pmutimer;
uint32 min_res_mask; u32 min_res_mask;
uint32 max_res_mask; u32 max_res_mask;
uint32 res_table_sel; u32 res_table_sel;
uint32 res_dep_mask; u32 res_dep_mask;
uint32 res_updn_timer; u32 res_updn_timer;
uint32 res_timer; u32 res_timer;
uint32 clkstretch; u32 clkstretch;
uint32 pmuwatchdog; u32 pmuwatchdog;
uint32 gpiosel; /* 0x638, rev >= 1 */ u32 gpiosel; /* 0x638, rev >= 1 */
uint32 gpioenable; /* 0x63c, rev >= 1 */ u32 gpioenable; /* 0x63c, rev >= 1 */
uint32 res_req_timer_sel; u32 res_req_timer_sel;
uint32 res_req_timer; u32 res_req_timer;
uint32 res_req_mask; u32 res_req_mask;
uint32 PAD; u32 PAD;
uint32 chipcontrol_addr; /* 0x650 */ u32 chipcontrol_addr; /* 0x650 */
uint32 chipcontrol_data; /* 0x654 */ u32 chipcontrol_data; /* 0x654 */
uint32 regcontrol_addr; u32 regcontrol_addr;
uint32 regcontrol_data; u32 regcontrol_data;
uint32 pllcontrol_addr; u32 pllcontrol_addr;
uint32 pllcontrol_data; u32 pllcontrol_data;
uint32 pmustrapopt; /* 0x668, corerev >= 28 */ u32 pmustrapopt; /* 0x668, corerev >= 28 */
uint32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */ u32 pmu_xtalfreq; /* 0x66C, pmurev >= 10 */
uint32 PAD[100]; u32 PAD[100];
u16 sromotp[768]; u16 sromotp[768];
} chipcregs_t; } chipcregs_t;
......
drivers/staging/brcm80211/include/sbconfig.h
浏览文件 @ 66cbd3ab
...@@ -74,43 +74,43 @@ ...@@ -74,43 +74,43 @@
#ifndef _LANGUAGE_ASSEMBLY #ifndef _LANGUAGE_ASSEMBLY
typedef volatile struct _sbconfig { typedef volatile struct _sbconfig {
uint32 PAD[2]; u32 PAD[2];
uint32 sbipsflag; /* initiator port ocp slave flag */ u32 sbipsflag; /* initiator port ocp slave flag */
uint32 PAD[3]; u32 PAD[3];
uint32 sbtpsflag; /* target port ocp slave flag */ u32 sbtpsflag; /* target port ocp slave flag */
uint32 PAD[11]; u32 PAD[11];
uint32 sbtmerrloga; /* (sonics >= 2.3) */ u32 sbtmerrloga; /* (sonics >= 2.3) */
uint32 PAD; u32 PAD;
uint32 sbtmerrlog; /* (sonics >= 2.3) */ u32 sbtmerrlog; /* (sonics >= 2.3) */
uint32 PAD[3]; u32 PAD[3];
uint32 sbadmatch3; /* address match3 */ u32 sbadmatch3; /* address match3 */
uint32 PAD; u32 PAD;
uint32 sbadmatch2; /* address match2 */ u32 sbadmatch2; /* address match2 */
uint32 PAD; u32 PAD;
uint32 sbadmatch1; /* address match1 */ u32 sbadmatch1; /* address match1 */
uint32 PAD[7]; u32 PAD[7];
uint32 sbimstate; /* initiator agent state */ u32 sbimstate; /* initiator agent state */
uint32 sbintvec; /* interrupt mask */ u32 sbintvec; /* interrupt mask */
uint32 sbtmstatelow; /* target state */ u32 sbtmstatelow; /* target state */
uint32 sbtmstatehigh; /* target state */ u32 sbtmstatehigh; /* target state */
uint32 sbbwa0; /* bandwidth allocation table0 */ u32 sbbwa0; /* bandwidth allocation table0 */
uint32 PAD; u32 PAD;
uint32 sbimconfiglow; /* initiator configuration */ u32 sbimconfiglow; /* initiator configuration */
uint32 sbimconfighigh; /* initiator configuration */ u32 sbimconfighigh; /* initiator configuration */
uint32 sbadmatch0; /* address match0 */ u32 sbadmatch0; /* address match0 */
uint32 PAD; u32 PAD;
uint32 sbtmconfiglow; /* target configuration */ u32 sbtmconfiglow; /* target configuration */
uint32 sbtmconfighigh; /* target configuration */ u32 sbtmconfighigh; /* target configuration */
uint32 sbbconfig; /* broadcast configuration */ u32 sbbconfig; /* broadcast configuration */
uint32 PAD; u32 PAD;
uint32 sbbstate; /* broadcast state */ u32 sbbstate; /* broadcast state */
uint32 PAD[3]; u32 PAD[3];
uint32 sbactcnfg; /* activate configuration */ u32 sbactcnfg; /* activate configuration */
uint32 PAD[3]; u32 PAD[3];
uint32 sbflagst; /* current sbflags */ u32 sbflagst; /* current sbflags */
uint32 PAD[3]; u32 PAD[3];
uint32 sbidlow; /* identification */ u32 sbidlow; /* identification */
uint32 sbidhigh; /* identification */ u32 sbidhigh; /* identification */
} sbconfig_t; } sbconfig_t;
#endif /* _LANGUAGE_ASSEMBLY */ #endif /* _LANGUAGE_ASSEMBLY */
......
drivers/staging/brcm80211/include/sbhnddma.h
浏览文件 @ 66cbd3ab
...@@ -27,10 +27,10 @@ ...@@ -27,10 +27,10 @@
/* dma registers per channel(xmt or rcv) */ /* dma registers per channel(xmt or rcv) */
typedef volatile struct { typedef volatile struct {
uint32 control; /* enable, et al */ u32 control; /* enable, et al */
uint32 addr; /* descriptor ring base address (4K aligned) */ u32 addr; /* descriptor ring base address (4K aligned) */
uint32 ptr; /* last descriptor posted to chip */ u32 ptr; /* last descriptor posted to chip */
uint32 status; /* current active descriptor, et al */ u32 status; /* current active descriptor, et al */
} dma32regs_t; } dma32regs_t;
typedef volatile struct { typedef volatile struct {
...@@ -39,10 +39,10 @@ typedef volatile struct { ...@@ -39,10 +39,10 @@ typedef volatile struct {
} dma32regp_t; } dma32regp_t;
typedef volatile struct { /* diag access */ typedef volatile struct { /* diag access */
uint32 fifoaddr; /* diag address */ u32 fifoaddr; /* diag address */
uint32 fifodatalow; /* low 32bits of data */ u32 fifodatalow; /* low 32bits of data */
uint32 fifodatahigh; /* high 32bits of data */ u32 fifodatahigh; /* high 32bits of data */
uint32 pad; /* reserved */ u32 pad; /* reserved */
} dma32diag_t; } dma32diag_t;
/* /*
...@@ -50,8 +50,8 @@ typedef volatile struct { /* diag access */ ...@@ -50,8 +50,8 @@ typedef volatile struct { /* diag access */
* Descriptors are only read by the hardware, never written back. * Descriptors are only read by the hardware, never written back.
*/ */
typedef volatile struct { typedef volatile struct {
uint32 ctrl; /* misc control bits & bufcount */ u32 ctrl; /* misc control bits & bufcount */
uint32 addr; /* data buffer address */ u32 addr; /* data buffer address */
} dma32dd_t; } dma32dd_t;
/* /*
...@@ -64,12 +64,12 @@ typedef volatile struct { ...@@ -64,12 +64,12 @@ typedef volatile struct {
#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t)) #define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
/* transmit channel control */ /* transmit channel control */
#define XC_XE ((uint32)1 << 0) /* transmit enable */ #define XC_XE ((u32)1 << 0) /* transmit enable */
#define XC_SE ((uint32)1 << 1) /* transmit suspend request */ #define XC_SE ((u32)1 << 1) /* transmit suspend request */
#define XC_LE ((uint32)1 << 2) /* loopback enable */ #define XC_LE ((u32)1 << 2) /* loopback enable */
#define XC_FL ((uint32)1 << 4) /* flush request */ #define XC_FL ((u32)1 << 4) /* flush request */
#define XC_PD ((uint32)1 << 11) /* parity check disable */ #define XC_PD ((u32)1 << 11) /* parity check disable */
#define XC_AE ((uint32)3 << 16) /* address extension bits */ #define XC_AE ((u32)3 << 16) /* address extension bits */
#define XC_AE_SHIFT 16 #define XC_AE_SHIFT 16
/* transmit descriptor table pointer */ /* transmit descriptor table pointer */
...@@ -95,14 +95,14 @@ typedef volatile struct { ...@@ -95,14 +95,14 @@ typedef volatile struct {
#define XS_AD_SHIFT 20 #define XS_AD_SHIFT 20
/* receive channel control */ /* receive channel control */
#define RC_RE ((uint32)1 << 0) /* receive enable */ #define RC_RE ((u32)1 << 0) /* receive enable */
#define RC_RO_MASK 0xfe /* receive frame offset */ #define RC_RO_MASK 0xfe /* receive frame offset */
#define RC_RO_SHIFT 1 #define RC_RO_SHIFT 1
#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */ #define RC_FM ((u32)1 << 8) /* direct fifo receive (pio) mode */
#define RC_SH ((uint32)1 << 9) /* separate rx header descriptor enable */ #define RC_SH ((u32)1 << 9) /* separate rx header descriptor enable */
#define RC_OC ((uint32)1 << 10) /* overflow continue */ #define RC_OC ((u32)1 << 10) /* overflow continue */
#define RC_PD ((uint32)1 << 11) /* parity check disable */ #define RC_PD ((u32)1 << 11) /* parity check disable */
#define RC_AE ((uint32)3 << 16) /* address extension bits */ #define RC_AE ((u32)3 << 16) /* address extension bits */
#define RC_AE_SHIFT 16 #define RC_AE_SHIFT 16
/* receive descriptor table pointer */ /* receive descriptor table pointer */
...@@ -143,13 +143,13 @@ typedef volatile struct { ...@@ -143,13 +143,13 @@ typedef volatile struct {
/* descriptor control flags */ /* descriptor control flags */
#define CTRL_BC_MASK 0x00001fff /* buffer byte count, real data len must <= 4KB */ #define CTRL_BC_MASK 0x00001fff /* buffer byte count, real data len must <= 4KB */
#define CTRL_AE ((uint32)3 << 16) /* address extension bits */ #define CTRL_AE ((u32)3 << 16) /* address extension bits */
#define CTRL_AE_SHIFT 16 #define CTRL_AE_SHIFT 16
#define CTRL_PARITY ((uint32)3 << 18) /* parity bit */ #define CTRL_PARITY ((u32)3 << 18) /* parity bit */
#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */ #define CTRL_EOT ((u32)1 << 28) /* end of descriptor table */
#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */ #define CTRL_IOC ((u32)1 << 29) /* interrupt on completion */
#define CTRL_EOF ((uint32)1 << 30) /* end of frame */ #define CTRL_EOF ((u32)1 << 30) /* end of frame */
#define CTRL_SOF ((uint32)1 << 31) /* start of frame */ #define CTRL_SOF ((u32)1 << 31) /* start of frame */
/* control flags in the range [27:20] are core-specific and not defined here */ /* control flags in the range [27:20] are core-specific and not defined here */
#define CTRL_CORE_MASK 0x0ff00000 #define CTRL_CORE_MASK 0x0ff00000
...@@ -158,12 +158,12 @@ typedef volatile struct { ...@@ -158,12 +158,12 @@ typedef volatile struct {
/* dma registers per channel(xmt or rcv) */ /* dma registers per channel(xmt or rcv) */
typedef volatile struct { typedef volatile struct {
uint32 control; /* enable, et al */ u32 control; /* enable, et al */
uint32 ptr; /* last descriptor posted to chip */ u32 ptr; /* last descriptor posted to chip */
uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */ u32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */ u32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
uint32 status0; /* current descriptor, xmt state */ u32 status0; /* current descriptor, xmt state */
uint32 status1; /* active descriptor, xmt error */ u32 status1; /* active descriptor, xmt error */
} dma64regs_t; } dma64regs_t;
typedef volatile struct { typedef volatile struct {
...@@ -172,10 +172,10 @@ typedef volatile struct { ...@@ -172,10 +172,10 @@ typedef volatile struct {
} dma64regp_t; } dma64regp_t;
typedef volatile struct { /* diag access */ typedef volatile struct { /* diag access */
uint32 fifoaddr; /* diag address */ u32 fifoaddr; /* diag address */
uint32 fifodatalow; /* low 32bits of data */ u32 fifodatalow; /* low 32bits of data */
uint32 fifodatahigh; /* high 32bits of data */ u32 fifodatahigh; /* high 32bits of data */
uint32 pad; /* reserved */ u32 pad; /* reserved */
} dma64diag_t; } dma64diag_t;
/* /*
...@@ -183,10 +183,10 @@ typedef volatile struct { /* diag access */ ...@@ -183,10 +183,10 @@ typedef volatile struct { /* diag access */
* Descriptors are only read by the hardware, never written back. * Descriptors are only read by the hardware, never written back.
*/ */
typedef volatile struct { typedef volatile struct {
uint32 ctrl1; /* misc control bits & bufcount */ u32 ctrl1; /* misc control bits & bufcount */
uint32 ctrl2; /* buffer count and address extension */ u32 ctrl2; /* buffer count and address extension */
uint32 addrlow; /* memory address of the date buffer, bits 31:0 */ u32 addrlow; /* memory address of the date buffer, bits 31:0 */
uint32 addrhigh; /* memory address of the date buffer, bits 63:32 */ u32 addrhigh; /* memory address of the date buffer, bits 63:32 */
} dma64dd_t; } dma64dd_t;
/* /*
...@@ -287,10 +287,10 @@ typedef volatile struct { ...@@ -287,10 +287,10 @@ typedef volatile struct {
/* descriptor control flags 1 */ /* descriptor control flags 1 */
#define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */ #define D64_CTRL_COREFLAGS 0x0ff00000 /* core specific flags */
#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */ #define D64_CTRL1_EOT ((u32)1 << 28) /* end of descriptor table */
#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */ #define D64_CTRL1_IOC ((u32)1 << 29) /* interrupt on completion */
#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */ #define D64_CTRL1_EOF ((u32)1 << 30) /* end of frame */
#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */ #define D64_CTRL1_SOF ((u32)1 << 31) /* start of frame */
/* descriptor control flags 2 */ /* descriptor control flags 2 */
#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */ #define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count. real data len must <= 16KB */
......
drivers/staging/brcm80211/include/sbhndpio.h
浏览文件 @ 66cbd3ab
...@@ -39,8 +39,8 @@ typedef volatile struct { ...@@ -39,8 +39,8 @@ typedef volatile struct {
/* 4byte-wide pio register set per channel(xmt or rcv) */ /* 4byte-wide pio register set per channel(xmt or rcv) */
typedef volatile struct { typedef volatile struct {
uint32 fifocontrol; u32 fifocontrol;
uint32 fifodata; u32 fifodata;
} pio4regs_t; } pio4regs_t;
/* a pair of pio channels(tx and rx) */ /* a pair of pio channels(tx and rx) */
......
drivers/staging/brcm80211/include/sbsdpcmdev.h
浏览文件 @ 66cbd3ab
...@@ -26,38 +26,38 @@ ...@@ -26,38 +26,38 @@
typedef volatile struct { typedef volatile struct {
dma64regs_t xmt; /* dma tx */ dma64regs_t xmt; /* dma tx */
uint32 PAD[2]; u32 PAD[2];
dma64regs_t rcv; /* dma rx */ dma64regs_t rcv; /* dma rx */
uint32 PAD[2]; u32 PAD[2];
} dma64p_t; } dma64p_t;
/* dma64 sdiod corerev >= 1 */ /* dma64 sdiod corerev >= 1 */
typedef volatile struct { typedef volatile struct {
dma64p_t dma64regs[2]; dma64p_t dma64regs[2];
dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */ dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */
uint32 PAD[92]; u32 PAD[92];
} sdiodma64_t; } sdiodma64_t;
/* dma32 sdiod corerev == 0 */ /* dma32 sdiod corerev == 0 */
typedef volatile struct { typedef volatile struct {
dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */ dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */
dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */ dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */
uint32 PAD[108]; u32 PAD[108];
} sdiodma32_t; } sdiodma32_t;
/* dma32 regs for pcmcia core */ /* dma32 regs for pcmcia core */
typedef volatile struct { typedef volatile struct {
dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */ dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */
dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */ dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */
uint32 PAD[116]; u32 PAD[116];
} pcmdma32_t; } pcmdma32_t;
/* core registers */ /* core registers */
typedef volatile struct { typedef volatile struct {
uint32 corecontrol; /* CoreControl, 0x000, rev8 */ u32 corecontrol; /* CoreControl, 0x000, rev8 */
uint32 corestatus; /* CoreStatus, 0x004, rev8 */ u32 corestatus; /* CoreStatus, 0x004, rev8 */
uint32 PAD[1]; u32 PAD[1];
uint32 biststatus; /* BistStatus, 0x00c, rev8 */ u32 biststatus; /* BistStatus, 0x00c, rev8 */
/* PCMCIA access */ /* PCMCIA access */
u16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */ u16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */
...@@ -70,21 +70,21 @@ typedef volatile struct { ...@@ -70,21 +70,21 @@ typedef volatile struct {
u16 PAD[1]; u16 PAD[1];
/* interrupt */ /* interrupt */
uint32 intstatus; /* IntStatus, 0x020, rev8 */ u32 intstatus; /* IntStatus, 0x020, rev8 */
uint32 hostintmask; /* IntHostMask, 0x024, rev8 */ u32 hostintmask; /* IntHostMask, 0x024, rev8 */
uint32 intmask; /* IntSbMask, 0x028, rev8 */ u32 intmask; /* IntSbMask, 0x028, rev8 */
uint32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */ u32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */
uint32 sbintmask; /* SBIntMask, 0x030, rev8 */ u32 sbintmask; /* SBIntMask, 0x030, rev8 */
uint32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */ u32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */
uint32 PAD[2]; u32 PAD[2];
uint32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */ u32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */
uint32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */ u32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */
uint32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */ u32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */
uint32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */ u32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */
/* synchronized access to registers in SDIO clock domain */ /* synchronized access to registers in SDIO clock domain */
uint32 sdioaccess; /* SdioAccess, 0x050, rev8 */ u32 sdioaccess; /* SdioAccess, 0x050, rev8 */
uint32 PAD[3]; u32 PAD[3];
/* PCMCIA frame control */ /* PCMCIA frame control */
u8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */ u8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */
...@@ -93,25 +93,25 @@ typedef volatile struct { ...@@ -93,25 +93,25 @@ typedef volatile struct {
u8 PAD[155]; u8 PAD[155];
/* interrupt batching control */ /* interrupt batching control */
uint32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */ u32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */
uint32 PAD[3]; u32 PAD[3];
/* counters */ /* counters */
uint32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */ u32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
uint32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */ u32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
uint32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */ u32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
uint32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */ u32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
uint32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */ u32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */
uint32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */ u32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
uint32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */ u32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
uint32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */ u32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
uint32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */ u32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
uint32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */ u32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
uint32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */ u32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
uint32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */ u32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
uint32 PAD[40]; u32 PAD[40];
uint32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */ u32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */
uint32 PAD[7]; u32 PAD[7];
/* DMA engines */ /* DMA engines */
volatile union { volatile union {
...@@ -141,7 +141,7 @@ typedef volatile struct { ...@@ -141,7 +141,7 @@ typedef volatile struct {
/* sprom "size" & "blank" info */ /* sprom "size" & "blank" info */
u16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */ u16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */
uint32 PAD[464]; u32 PAD[464];
/* Sonics SiliconBackplane registers */ /* Sonics SiliconBackplane registers */
sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */ sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */
......
drivers/staging/brcm80211/include/sbsocram.h
浏览文件 @ 66cbd3ab
...@@ -28,34 +28,34 @@ ...@@ -28,34 +28,34 @@
/* Memcsocram core registers */ /* Memcsocram core registers */
typedef volatile struct sbsocramregs { typedef volatile struct sbsocramregs {
uint32 coreinfo; u32 coreinfo;
uint32 bwalloc; u32 bwalloc;
uint32 extracoreinfo; u32 extracoreinfo;
uint32 biststat; u32 biststat;
uint32 bankidx; u32 bankidx;
uint32 standbyctrl; u32 standbyctrl;
uint32 errlogstatus; /* rev 6 */ u32 errlogstatus; /* rev 6 */
uint32 errlogaddr; /* rev 6 */ u32 errlogaddr; /* rev 6 */
/* used for patching rev 3 & 5 */ /* used for patching rev 3 & 5 */
uint32 cambankidx; u32 cambankidx;
uint32 cambankstandbyctrl; u32 cambankstandbyctrl;
uint32 cambankpatchctrl; u32 cambankpatchctrl;
uint32 cambankpatchtblbaseaddr; u32 cambankpatchtblbaseaddr;
uint32 cambankcmdreg; u32 cambankcmdreg;
uint32 cambankdatareg; u32 cambankdatareg;
uint32 cambankmaskreg; u32 cambankmaskreg;
uint32 PAD[1]; u32 PAD[1];
uint32 bankinfo; /* corev 8 */ u32 bankinfo; /* corev 8 */
uint32 PAD[15]; u32 PAD[15];
uint32 extmemconfig; u32 extmemconfig;
uint32 extmemparitycsr; u32 extmemparitycsr;
uint32 extmemparityerrdata; u32 extmemparityerrdata;
uint32 extmemparityerrcnt; u32 extmemparityerrcnt;
uint32 extmemwrctrlandsize; u32 extmemwrctrlandsize;
uint32 PAD[84]; u32 PAD[84];
uint32 workaround; u32 workaround;
uint32 pwrctl; /* corerev >= 2 */ u32 pwrctl; /* corerev >= 2 */
} sbsocramregs_t; } sbsocramregs_t;
#endif /* _LANGUAGE_ASSEMBLY */ #endif /* _LANGUAGE_ASSEMBLY */
......
drivers/staging/brcm80211/include/siutils.h
浏览文件 @ 66cbd3ab
...@@ -34,10 +34,10 @@ struct si_pub { ...@@ -34,10 +34,10 @@ struct si_pub {
uint buscorerev; /* buscore rev */ uint buscorerev; /* buscore rev */
uint buscoreidx; /* buscore index */ uint buscoreidx; /* buscore index */
int ccrev; /* chip common core rev */ int ccrev; /* chip common core rev */
uint32 cccaps; /* chip common capabilities */ u32 cccaps; /* chip common capabilities */
uint32 cccaps_ext; /* chip common capabilities extension */ u32 cccaps_ext; /* chip common capabilities extension */
int pmurev; /* pmu core rev */ int pmurev; /* pmu core rev */
uint32 pmucaps; /* pmu capabilities */ u32 pmucaps; /* pmu capabilities */
uint boardtype; /* board type */ uint boardtype; /* board type */
uint boardvendor; /* board vendor */ uint boardvendor; /* board vendor */
uint boardflags; /* board flags */ uint boardflags; /* board flags */
...@@ -45,7 +45,7 @@ struct si_pub { ...@@ -45,7 +45,7 @@ struct si_pub {
uint chip; /* chip number */ uint chip; /* chip number */
uint chiprev; /* chip revision */ uint chiprev; /* chip revision */
uint chippkg; /* chip package option */ uint chippkg; /* chip package option */
uint32 chipst; /* chip status */ u32 chipst; /* chip status */
bool issim; /* chip is in simulation or emulation */ bool issim; /* chip is in simulation or emulation */
uint socirev; /* SOC interconnect rev */ uint socirev; /* SOC interconnect rev */
bool pci_pr32414; bool pci_pr32414;
...@@ -122,7 +122,7 @@ typedef const struct si_pub si_t; ...@@ -122,7 +122,7 @@ typedef const struct si_pub si_t;
#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK) #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
#endif #endif
typedef void (*gpio_handler_t) (uint32 stat, void *arg); typedef void (*gpio_handler_t) (u32 stat, void *arg);
/* External PA enable mask */ /* External PA enable mask */
#define GPIO_CTRL_EPA_EN_MASK 0x40 #define GPIO_CTRL_EPA_EN_MASK 0x40
...@@ -141,9 +141,9 @@ extern uint si_corerev(si_t *sih); ...@@ -141,9 +141,9 @@ extern uint si_corerev(si_t *sih);
extern void *si_osh(si_t *sih); extern void *si_osh(si_t *sih);
extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
uint val); uint val);
extern void si_write_wrapperreg(si_t *sih, uint32 offset, uint32 val); extern void si_write_wrapperreg(si_t *sih, u32 offset, u32 val);
extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val); extern u32 si_core_cflags(si_t *sih, u32 mask, u32 val);
extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val); extern u32 si_core_sflags(si_t *sih, u32 mask, u32 val);
extern bool si_iscoreup(si_t *sih); extern bool si_iscoreup(si_t *sih);
extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit); extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
#ifndef BCMSDIO #ifndef BCMSDIO
...@@ -153,10 +153,10 @@ extern void *si_setcore(si_t *sih, uint coreid, uint coreunit); ...@@ -153,10 +153,10 @@ extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx,
uint *intr_val); uint *intr_val);
extern void si_restore_core(si_t *sih, uint coreid, uint intr_val); extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits); extern void si_core_reset(si_t *sih, u32 bits, u32 resetbits);
extern void si_core_disable(si_t *sih, uint32 bits); extern void si_core_disable(si_t *sih, u32 bits);
extern uint32 si_alp_clock(si_t *sih); extern u32 si_alp_clock(si_t *sih);
extern uint32 si_ilp_clock(si_t *sih); extern u32 si_ilp_clock(si_t *sih);
extern void si_pci_setup(si_t *sih, uint coremask); extern void si_pci_setup(si_t *sih, uint coremask);
extern void si_setint(si_t *sih, int siflag); extern void si_setint(si_t *sih, int siflag);
extern bool si_backplane64(si_t *sih); extern bool si_backplane64(si_t *sih);
...@@ -169,10 +169,10 @@ extern u16 si_clkctl_fast_pwrup_delay(si_t *sih); ...@@ -169,10 +169,10 @@ extern u16 si_clkctl_fast_pwrup_delay(si_t *sih);
extern bool si_clkctl_cc(si_t *sih, uint mode); extern bool si_clkctl_cc(si_t *sih, uint mode);
extern int si_clkctl_xtal(si_t *sih, uint what, bool on); extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
extern bool si_deviceremoved(si_t *sih); extern bool si_deviceremoved(si_t *sih);
extern uint32 si_socram_size(si_t *sih); extern u32 si_socram_size(si_t *sih);
extern void si_watchdog(si_t *sih, uint ticks); extern void si_watchdog(si_t *sih, uint ticks);
extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, extern u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val,
u8 priority); u8 priority);
#ifdef BCMSDIO #ifdef BCMSDIO
...@@ -212,15 +212,15 @@ extern void si_sprom_init(si_t *sih); ...@@ -212,15 +212,15 @@ extern void si_sprom_init(si_t *sih);
#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
typedef uint32(*si_intrsoff_t) (void *intr_arg); typedef u32(*si_intrsoff_t) (void *intr_arg);
typedef void (*si_intrsrestore_t) (void *intr_arg, uint32 arg); typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
typedef bool(*si_intrsenabled_t) (void *intr_arg); typedef bool(*si_intrsenabled_t) (void *intr_arg);
typedef struct gpioh_item { typedef struct gpioh_item {
void *arg; void *arg;
bool level; bool level;
gpio_handler_t handler; gpio_handler_t handler;
uint32 event; u32 event;
struct gpioh_item *next; struct gpioh_item *next;
} gpioh_item_t; } gpioh_item_t;
...@@ -250,19 +250,19 @@ typedef struct si_info { ...@@ -250,19 +250,19 @@ typedef struct si_info {
uint curidx; /* current core index */ uint curidx; /* current core index */
uint numcores; /* # discovered cores */ uint numcores; /* # discovered cores */
uint coreid[SI_MAXCORES]; /* id of each core */ uint coreid[SI_MAXCORES]; /* id of each core */
uint32 coresba[SI_MAXCORES]; /* backplane address of each core */ u32 coresba[SI_MAXCORES]; /* backplane address of each core */
void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */ void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */ u32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */ u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
uint32 coresba2_size[SI_MAXCORES]; /* second address space size */ u32 coresba2_size[SI_MAXCORES]; /* second address space size */
void *curwrap; /* current wrapper va */ void *curwrap; /* current wrapper va */
void *wrappers[SI_MAXCORES]; /* other cores wrapper va */ void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */ u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */ u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */ u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
uint32 oob_router; /* oob router registers for axi */ u32 oob_router; /* oob router registers for axi */
} si_info_t; } si_info_t;
#define SI_INFO(sih) (si_info_t *)(uintptr)sih #define SI_INFO(sih) (si_info_t *)(uintptr)sih
...@@ -356,17 +356,17 @@ extern uint ai_corevendor(si_t *sih); ...@@ -356,17 +356,17 @@ extern uint ai_corevendor(si_t *sih);
extern uint ai_corerev(si_t *sih); extern uint ai_corerev(si_t *sih);
extern bool ai_iscoreup(si_t *sih); extern bool ai_iscoreup(si_t *sih);
extern void *ai_setcoreidx(si_t *sih, uint coreidx); extern void *ai_setcoreidx(si_t *sih, uint coreidx);
extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val); extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val); extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
uint val); uint val);
extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
extern void ai_core_disable(si_t *sih, uint32 bits); extern void ai_core_disable(si_t *sih, u32 bits);
extern int ai_numaddrspaces(si_t *sih); extern int ai_numaddrspaces(si_t *sih);
extern uint32 ai_addrspace(si_t *sih, uint asidx); extern u32 ai_addrspace(si_t *sih, uint asidx);
extern uint32 ai_addrspacesize(si_t *sih, uint asidx); extern u32 ai_addrspacesize(si_t *sih, uint asidx);
extern void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val); extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
#ifdef BCMSDIO #ifdef BCMSDIO
#define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx) #define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
......
drivers/staging/brcm80211/include/spid.h
浏览文件 @ 66cbd3ab
...@@ -31,12 +31,12 @@ typedef volatile struct { ...@@ -31,12 +31,12 @@ typedef volatile struct {
u8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */ u8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
u16 intr_reg; /* 0x04, Intr status register */ u16 intr_reg; /* 0x04, Intr status register */
u16 intr_en_reg; /* 0x06, Intr mask register */ u16 intr_en_reg; /* 0x06, Intr mask register */
uint32 status_reg; /* 0x08, RO, Status bits of last spi transfer */ u32 status_reg; /* 0x08, RO, Status bits of last spi transfer */
u16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */ u16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */
u16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */ u16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */
u16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */ u16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */
uint32 test_read; /* 0x14, RO 0xfeedbead signature */ u32 test_read; /* 0x14, RO 0xfeedbead signature */
uint32 test_rw; /* 0x18, RW */ u32 test_rw; /* 0x18, RW */
u8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */ u8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */
u8 resp_delay_f1; /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */ u8 resp_delay_f1; /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */
u8 resp_delay_f2; /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */ u8 resp_delay_f2; /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */
......
drivers/staging/brcm80211/include/typedefs.h
浏览文件 @ 66cbd3ab
...@@ -44,10 +44,6 @@ typedef unsigned int uint; ...@@ -44,10 +44,6 @@ typedef unsigned int uint;
/* define [u]int32/64, uintptr */ /* define [u]int32/64, uintptr */
#ifndef TYPEDEF_UINT32
typedef unsigned int uint32;
#endif
#ifndef TYPEDEF_UINTPTR #ifndef TYPEDEF_UINTPTR
typedef unsigned int uintptr; typedef unsigned int uintptr;
#endif #endif
...@@ -77,7 +73,6 @@ typedef signed int int32; ...@@ -77,7 +73,6 @@ typedef signed int int32;
#define AUTO (-1) /* Auto = -1 */ #define AUTO (-1) /* Auto = -1 */
#undef TYPEDEF_UINT #undef TYPEDEF_UINT
#undef TYPEDEF_UINT32
#undef TYPEDEF_UINTPTR #undef TYPEDEF_UINTPTR
#undef TYPEDEF_INT32 #undef TYPEDEF_INT32
......
drivers/staging/brcm80211/phy/wlc_phy_cmn.c
浏览文件 @ 66cbd3ab
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
#include <wlc_phy_radio.h> #include <wlc_phy_radio.h>
#include <wlc_phy_lcn.h> #include <wlc_phy_lcn.h>
uint32 phyhal_msg_level = PHYHAL_ERROR; u32 phyhal_msg_level = PHYHAL_ERROR;
typedef struct _chan_info_basic { typedef struct _chan_info_basic {
u16 chan; u16 chan;
...@@ -126,10 +126,10 @@ const u8 ofdm_rate_lookup[] = { ...@@ -126,10 +126,10 @@ const u8 ofdm_rate_lookup[] = {
#define PHY_WREG_LIMIT 24 #define PHY_WREG_LIMIT 24
static void wlc_set_phy_uninitted(phy_info_t *pi); static void wlc_set_phy_uninitted(phy_info_t *pi);
static uint32 wlc_phy_get_radio_ver(phy_info_t *pi); static u32 wlc_phy_get_radio_ver(phy_info_t *pi);
static void wlc_phy_timercb_phycal(void *arg); static void wlc_phy_timercb_phycal(void *arg);
static bool wlc_phy_noise_calc_phy(phy_info_t *pi, uint32 *cmplx_pwr, static bool wlc_phy_noise_calc_phy(phy_info_t *pi, u32 *cmplx_pwr,
s8 *pwr_ant); s8 *pwr_ant);
static void wlc_phy_cal_perical_mphase_schedule(phy_info_t *pi, uint delay); static void wlc_phy_cal_perical_mphase_schedule(phy_info_t *pi, uint delay);
...@@ -142,8 +142,8 @@ static void wlc_phy_txpower_reg_limit_calc(phy_info_t *pi, ...@@ -142,8 +142,8 @@ static void wlc_phy_txpower_reg_limit_calc(phy_info_t *pi,
static bool wlc_phy_cal_txpower_recalc_sw(phy_info_t *pi); static bool wlc_phy_cal_txpower_recalc_sw(phy_info_t *pi);
static s8 wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan, static s8 wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan,
uint32 band, u8 rate); u32 band, u8 rate);
static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, uint32 band); static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, u32 band);
static s8 wlc_phy_env_measure_vbat(phy_info_t *pi); static s8 wlc_phy_env_measure_vbat(phy_info_t *pi);
static s8 wlc_phy_env_measure_temperature(phy_info_t *pi); static s8 wlc_phy_env_measure_temperature(phy_info_t *pi);
...@@ -304,31 +304,31 @@ void write_radio_reg(phy_info_t *pi, u16 addr, u16 val) ...@@ -304,31 +304,31 @@ void write_radio_reg(phy_info_t *pi, u16 addr, u16 val)
} }
} }
static uint32 read_radio_id(phy_info_t *pi) static u32 read_radio_id(phy_info_t *pi)
{ {
uint32 id; u32 id;
if (NORADIO_ENAB(pi->pubpi)) if (NORADIO_ENAB(pi->pubpi))
return NORADIO_IDCODE; return NORADIO_IDCODE;
if (D11REV_GE(pi->sh->corerev, 24)) { if (D11REV_GE(pi->sh->corerev, 24)) {
uint32 b0, b1, b2; u32 b0, b1, b2;
W_REG(pi->sh->osh, &pi->regs->radioregaddr, 0); W_REG(pi->sh->osh, &pi->regs->radioregaddr, 0);
#ifdef __mips__ #ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr); (void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
#endif #endif
b0 = (uint32) R_REG(pi->sh->osh, &pi->regs->radioregdata); b0 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
W_REG(pi->sh->osh, &pi->regs->radioregaddr, 1); W_REG(pi->sh->osh, &pi->regs->radioregaddr, 1);
#ifdef __mips__ #ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr); (void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
#endif #endif
b1 = (uint32) R_REG(pi->sh->osh, &pi->regs->radioregdata); b1 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
W_REG(pi->sh->osh, &pi->regs->radioregaddr, 2); W_REG(pi->sh->osh, &pi->regs->radioregaddr, 2);
#ifdef __mips__ #ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->radioregaddr); (void)R_REG(pi->sh->osh, &pi->regs->radioregaddr);
#endif #endif
b2 = (uint32) R_REG(pi->sh->osh, &pi->regs->radioregdata); b2 = (u32) R_REG(pi->sh->osh, &pi->regs->radioregdata);
id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4) id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
& 0xf); & 0xf);
...@@ -337,8 +337,8 @@ static uint32 read_radio_id(phy_info_t *pi) ...@@ -337,8 +337,8 @@ static uint32 read_radio_id(phy_info_t *pi)
#ifdef __mips__ #ifdef __mips__
(void)R_REG(pi->sh->osh, &pi->regs->phy4waddr); (void)R_REG(pi->sh->osh, &pi->regs->phy4waddr);
#endif #endif
id = (uint32) R_REG(pi->sh->osh, &pi->regs->phy4wdatalo); id = (u32) R_REG(pi->sh->osh, &pi->regs->phy4wdatalo);
id |= (uint32) R_REG(pi->sh->osh, &pi->regs->phy4wdatahi) << 16; id |= (u32) R_REG(pi->sh->osh, &pi->regs->phy4wdatahi) << 16;
} }
pi->phy_wreg = 0; pi->phy_wreg = 0;
return id; return id;
...@@ -396,7 +396,7 @@ void write_phy_channel_reg(phy_info_t *pi, uint val) ...@@ -396,7 +396,7 @@ void write_phy_channel_reg(phy_info_t *pi, uint val)
#if defined(BCMDBG) #if defined(BCMDBG)
static bool wlc_phy_war41476(phy_info_t *pi) static bool wlc_phy_war41476(phy_info_t *pi)
{ {
uint32 mc = R_REG(pi->sh->osh, &pi->regs->maccontrol); u32 mc = R_REG(pi->sh->osh, &pi->regs->maccontrol);
return ((mc & MCTL_EN_MAC) == 0) return ((mc & MCTL_EN_MAC) == 0)
|| ((mc & MCTL_PHYLOCK) == MCTL_PHYLOCK); || ((mc & MCTL_PHYLOCK) == MCTL_PHYLOCK);
...@@ -439,7 +439,7 @@ void write_phy_reg(phy_info_t *pi, u16 addr, u16 val) ...@@ -439,7 +439,7 @@ void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
if (addr == 0x72) if (addr == 0x72)
(void)R_REG(osh, &regs->phyregdata); (void)R_REG(osh, &regs->phyregdata);
#else #else
W_REG(osh, (volatile uint32 *)(uintptr) (&regs->phyregaddr), W_REG(osh, (volatile u32 *)(uintptr) (&regs->phyregaddr),
addr | (val << 16)); addr | (val << 16));
if (BUSTYPE(pi->sh->bustype) == PCI_BUS) { if (BUSTYPE(pi->sh->bustype) == PCI_BUS) {
if (++pi->phy_wreg >= pi->phy_wreg_limit) { if (++pi->phy_wreg >= pi->phy_wreg_limit) {
...@@ -607,7 +607,7 @@ void BCMATTACHFN(wlc_phy_shared_detach) (shared_phy_t *phy_sh) ...@@ -607,7 +607,7 @@ void BCMATTACHFN(wlc_phy_shared_detach) (shared_phy_t *phy_sh)
wlc_phy_t *BCMATTACHFN(wlc_phy_attach) (shared_phy_t *sh, void *regs, wlc_phy_t *BCMATTACHFN(wlc_phy_attach) (shared_phy_t *sh, void *regs,
int bandtype, char *vars) { int bandtype, char *vars) {
phy_info_t *pi; phy_info_t *pi;
uint32 sflags = 0; u32 sflags = 0;
uint phyversion; uint phyversion;
int i; int i;
osl_t *osh; osl_t *osh;
...@@ -686,7 +686,7 @@ wlc_phy_t *BCMATTACHFN(wlc_phy_attach) (shared_phy_t *sh, void *regs, ...@@ -686,7 +686,7 @@ wlc_phy_t *BCMATTACHFN(wlc_phy_attach) (shared_phy_t *sh, void *regs,
pi->pubpi.radioid = NORADIO_ID; pi->pubpi.radioid = NORADIO_ID;
pi->pubpi.radiorev = 5; pi->pubpi.radiorev = 5;
} else { } else {
uint32 idcode; u32 idcode;
wlc_phy_anacore((wlc_phy_t *) pi, ON); wlc_phy_anacore((wlc_phy_t *) pi, ON);
...@@ -833,7 +833,7 @@ bool wlc_phy_get_encore(wlc_phy_t *pih) ...@@ -833,7 +833,7 @@ bool wlc_phy_get_encore(wlc_phy_t *pih)
return pi->pubpi.abgphy_encore; return pi->pubpi.abgphy_encore;
} }
uint32 wlc_phy_get_coreflags(wlc_phy_t *pih) u32 wlc_phy_get_coreflags(wlc_phy_t *pih)
{ {
phy_info_t *pi = (phy_info_t *) pih; phy_info_t *pi = (phy_info_t *) pih;
return pi->pubpi.coreflags; return pi->pubpi.coreflags;
...@@ -899,11 +899,11 @@ void wlc_phy_anacore(wlc_phy_t *pih, bool on) ...@@ -899,11 +899,11 @@ void wlc_phy_anacore(wlc_phy_t *pih, bool on)
} }
} }
uint32 wlc_phy_clk_bwbits(wlc_phy_t *pih) u32 wlc_phy_clk_bwbits(wlc_phy_t *pih)
{ {
phy_info_t *pi = (phy_info_t *) pih; phy_info_t *pi = (phy_info_t *) pih;
uint32 phy_bw_clkbits = 0; u32 phy_bw_clkbits = 0;
if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) { if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) {
switch (pi->bw) { switch (pi->bw) {
...@@ -973,7 +973,7 @@ void wlc_phy_hw_state_upd(wlc_phy_t *pih, bool newstate) ...@@ -973,7 +973,7 @@ void wlc_phy_hw_state_upd(wlc_phy_t *pih, bool newstate)
void WLBANDINITFN(wlc_phy_init) (wlc_phy_t *pih, chanspec_t chanspec) void WLBANDINITFN(wlc_phy_init) (wlc_phy_t *pih, chanspec_t chanspec)
{ {
uint32 mc; u32 mc;
initfn_t phy_init = NULL; initfn_t phy_init = NULL;
phy_info_t *pi = (phy_info_t *) pih; phy_info_t *pi = (phy_info_t *) pih;
...@@ -1064,9 +1064,9 @@ int BCMUNINITFN(wlc_phy_down) (wlc_phy_t *pih) ...@@ -1064,9 +1064,9 @@ int BCMUNINITFN(wlc_phy_down) (wlc_phy_t *pih)
return callbacks; return callbacks;
} }
static uint32 wlc_phy_get_radio_ver(phy_info_t *pi) static u32 wlc_phy_get_radio_ver(phy_info_t *pi)
{ {
uint32 ver; u32 ver;
ver = read_radio_id(pi); ver = read_radio_id(pi);
...@@ -1091,7 +1091,7 @@ wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset, ...@@ -1091,7 +1091,7 @@ wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
} }
} }
void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val) void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val)
{ {
ASSERT((width == 8) || (width == 16) || (width == 32)); ASSERT((width == 8) || (width == 16) || (width == 32));
...@@ -1126,7 +1126,7 @@ wlc_phy_write_table(phy_info_t *pi, const phytbl_info_t *ptbl_info, ...@@ -1126,7 +1126,7 @@ wlc_phy_write_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
uint tbl_width = ptbl_info->tbl_width; uint tbl_width = ptbl_info->tbl_width;
const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr; const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr;
const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr; const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr;
const uint32 *ptbl_32b = (const uint32 *)ptbl_info->tbl_ptr; const u32 *ptbl_32b = (const u32 *)ptbl_info->tbl_ptr;
ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32)); ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32));
...@@ -1169,7 +1169,7 @@ wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info, ...@@ -1169,7 +1169,7 @@ wlc_phy_read_table(phy_info_t *pi, const phytbl_info_t *ptbl_info,
uint tbl_width = ptbl_info->tbl_width; uint tbl_width = ptbl_info->tbl_width;
u8 *ptbl_8b = (u8 *) (uintptr) ptbl_info->tbl_ptr; u8 *ptbl_8b = (u8 *) (uintptr) ptbl_info->tbl_ptr;
u16 *ptbl_16b = (u16 *) (uintptr) ptbl_info->tbl_ptr; u16 *ptbl_16b = (u16 *) (uintptr) ptbl_info->tbl_ptr;
uint32 *ptbl_32b = (uint32 *) (uintptr) ptbl_info->tbl_ptr; u32 *ptbl_32b = (u32 *) (uintptr) ptbl_info->tbl_ptr;
ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32)); ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32));
...@@ -1264,11 +1264,11 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on) ...@@ -1264,11 +1264,11 @@ void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on)
0x6e, 0x84, 0x0b, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00, 0x6e, 0x84, 0x0b, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
}; };
uint32 *dummypkt; u32 *dummypkt;
ASSERT((R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) == 0); ASSERT((R_REG(pi->sh->osh, &pi->regs->maccontrol) & MCTL_EN_MAC) == 0);
dummypkt = (uint32 *) (ofdm ? ofdmpkt : cckpkt); dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN, wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
dummypkt); dummypkt);
...@@ -1783,7 +1783,7 @@ wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan, u8 *max_txpwr, ...@@ -1783,7 +1783,7 @@ wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan, u8 *max_txpwr,
void void
wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint bandunit, int32 *max_pwr, wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint bandunit, int32 *max_pwr,
int32 *min_pwr, uint32 *step_pwr) int32 *min_pwr, u32 *step_pwr)
{ {
return; return;
} }
...@@ -1813,7 +1813,7 @@ void wlc_phy_txpower_recalc_target(phy_info_t *pi) ...@@ -1813,7 +1813,7 @@ void wlc_phy_txpower_recalc_target(phy_info_t *pi)
u8 max_num_rate; u8 max_num_rate;
u8 start_rate = 0; u8 start_rate = 0;
chanspec_t chspec; chanspec_t chspec;
uint32 band = CHSPEC2WLC_BAND(pi->radio_chanspec); u32 band = CHSPEC2WLC_BAND(pi->radio_chanspec);
initfn_t txpwr_recalc_fn = NULL; initfn_t txpwr_recalc_fn = NULL;
chspec = pi->radio_chanspec; chspec = pi->radio_chanspec;
...@@ -1826,7 +1826,7 @@ void wlc_phy_txpower_recalc_target(phy_info_t *pi) ...@@ -1826,7 +1826,7 @@ void wlc_phy_txpower_recalc_target(phy_info_t *pi)
pactrl = 0; pactrl = 0;
if (ISLCNPHY(pi)) { if (ISLCNPHY(pi)) {
uint32 offset_mcs, i; u32 offset_mcs, i;
if (CHSPEC_IS40(pi->radio_chanspec)) { if (CHSPEC_IS40(pi->radio_chanspec)) {
offset_mcs = pi->mcs40_po; offset_mcs = pi->mcs40_po;
...@@ -2080,7 +2080,7 @@ void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent) ...@@ -2080,7 +2080,7 @@ void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent)
pi->txpwr_percent = txpwr_percent; pi->txpwr_percent = txpwr_percent;
} }
void wlc_phy_machwcap_set(wlc_phy_t *ppi, uint32 machwcap) void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap)
{ {
phy_info_t *pi = (phy_info_t *) ppi; phy_info_t *pi = (phy_info_t *) ppi;
...@@ -2270,14 +2270,14 @@ void wlc_phy_txpower_ipa_upd(phy_info_t *pi) ...@@ -2270,14 +2270,14 @@ void wlc_phy_txpower_ipa_upd(phy_info_t *pi)
} }
} }
static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi); static u32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi);
static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi) static u32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi)
{ {
s16 tx0_status, tx1_status; s16 tx0_status, tx1_status;
u16 estPower1, estPower2; u16 estPower1, estPower2;
u8 pwr0, pwr1, adj_pwr0, adj_pwr1; u8 pwr0, pwr1, adj_pwr0, adj_pwr1;
uint32 est_pwr; u32 est_pwr;
estPower1 = read_phy_reg(pi, 0x118); estPower1 = read_phy_reg(pi, 0x118);
estPower2 = read_phy_reg(pi, 0x119); estPower2 = read_phy_reg(pi, 0x119);
...@@ -2317,7 +2317,7 @@ static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi) ...@@ -2317,7 +2317,7 @@ static uint32 wlc_phy_txpower_est_power_nphy(phy_info_t *pi)
} }
est_pwr = est_pwr =
(uint32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) | adj_pwr1); (u32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) | adj_pwr1);
return est_pwr; return est_pwr;
} }
...@@ -2360,7 +2360,7 @@ wlc_phy_txpower_get_current(wlc_phy_t *ppi, tx_power_t *power, uint channel) ...@@ -2360,7 +2360,7 @@ wlc_phy_txpower_get_current(wlc_phy_t *ppi, tx_power_t *power, uint channel)
} }
if (ISNPHY(pi)) { if (ISNPHY(pi)) {
uint32 est_pout; u32 est_pout;
wlapi_suspend_mac_and_wait(pi->sh->physhim); wlapi_suspend_mac_and_wait(pi->sh->physhim);
wlc_phyreg_enter((wlc_phy_t *) pi); wlc_phyreg_enter((wlc_phy_t *) pi);
...@@ -2504,7 +2504,7 @@ void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val) ...@@ -2504,7 +2504,7 @@ void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val)
} }
static bool static bool
wlc_phy_noise_calc_phy(phy_info_t *pi, uint32 *cmplx_pwr, s8 *pwr_ant) wlc_phy_noise_calc_phy(phy_info_t *pi, u32 *cmplx_pwr, s8 *pwr_ant)
{ {
s8 cmplx_pwr_dbm[PHY_CORE_MAX]; s8 cmplx_pwr_dbm[PHY_CORE_MAX];
u8 i; u8 i;
...@@ -2616,7 +2616,7 @@ wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch) ...@@ -2616,7 +2616,7 @@ wlc_phy_noise_sample_request(wlc_phy_t *pih, u8 reason, u8 ch)
MCMD_BG_NOISE); MCMD_BG_NOISE);
} else { } else {
phy_iq_est_t est[PHY_CORE_MAX]; phy_iq_est_t est[PHY_CORE_MAX];
uint32 cmplx_pwr[PHY_CORE_MAX]; u32 cmplx_pwr[PHY_CORE_MAX];
s8 noise_dbm_ant[PHY_CORE_MAX]; s8 noise_dbm_ant[PHY_CORE_MAX];
u16 log_num_samps, num_samps, classif_state = 0; u16 log_num_samps, num_samps, classif_state = 0;
u8 wait_time = 32; u8 wait_time = 32;
...@@ -2698,10 +2698,10 @@ static void wlc_phy_noise_cb(phy_info_t *pi, u8 channel, s8 noise_dbm) ...@@ -2698,10 +2698,10 @@ static void wlc_phy_noise_cb(phy_info_t *pi, u8 channel, s8 noise_dbm)
static s8 wlc_phy_noise_read_shmem(phy_info_t *pi) static s8 wlc_phy_noise_read_shmem(phy_info_t *pi)
{ {
uint32 cmplx_pwr[PHY_CORE_MAX]; u32 cmplx_pwr[PHY_CORE_MAX];
s8 noise_dbm_ant[PHY_CORE_MAX]; s8 noise_dbm_ant[PHY_CORE_MAX];
u16 lo, hi; u16 lo, hi;
uint32 cmplx_pwr_tot = 0; u32 cmplx_pwr_tot = 0;
s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY; s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
u8 idx, core; u8 idx, core;
...@@ -2746,7 +2746,7 @@ void wlc_phy_noise_sample_intr(wlc_phy_t *pih) ...@@ -2746,7 +2746,7 @@ void wlc_phy_noise_sample_intr(wlc_phy_t *pih)
s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY; s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
if (ISLCNPHY(pi)) { if (ISLCNPHY(pi)) {
uint32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1; u32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1;
u16 lo, hi; u16 lo, hi;
int32 pwr_offset_dB, gain_dB; int32 pwr_offset_dB, gain_dB;
u16 status_0, status_1; u16 status_0, status_1;
...@@ -2836,10 +2836,10 @@ s8 lcnphy_gain_index_offset_for_pkt_rssi[] = { ...@@ -2836,10 +2836,10 @@ s8 lcnphy_gain_index_offset_for_pkt_rssi[] = {
0 0
}; };
void wlc_phy_compute_dB(uint32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core) void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core)
{ {
u8 shift_ct, lsb, msb, secondmsb, i; u8 shift_ct, lsb, msb, secondmsb, i;
uint32 tmp; u32 tmp;
for (i = 0; i < core; i++) { for (i = 0; i < core; i++) {
tmp = cmplx_pwr[i]; tmp = cmplx_pwr[i];
...@@ -3021,7 +3021,7 @@ void wlc_phy_BSSinit(wlc_phy_t *pih, bool bonlyap, int rssi) ...@@ -3021,7 +3021,7 @@ void wlc_phy_BSSinit(wlc_phy_t *pih, bool bonlyap, int rssi)
} }
void void
wlc_phy_papd_decode_epsilon(uint32 epsilon, int32 *eps_real, int32 *eps_imag) wlc_phy_papd_decode_epsilon(u32 epsilon, int32 *eps_real, int32 *eps_imag)
{ {
*eps_imag = (epsilon >> 13); *eps_imag = (epsilon >> 13);
if (*eps_imag > 0xfff) if (*eps_imag > 0xfff)
...@@ -3219,9 +3219,9 @@ u8 wlc_phy_nbits(int32 value) ...@@ -3219,9 +3219,9 @@ u8 wlc_phy_nbits(int32 value)
return nbits; return nbits;
} }
uint32 wlc_phy_sqrt_int(uint32 value) u32 wlc_phy_sqrt_int(u32 value)
{ {
uint32 root = 0, shift = 0; u32 root = 0, shift = 0;
for (shift = 0; shift < 32; shift += 2) { for (shift = 0; shift < 32; shift += 2) {
if (((0x40000000 >> shift) + root) <= value) { if (((0x40000000 >> shift) + root) <= value) {
...@@ -3363,7 +3363,7 @@ void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode) ...@@ -3363,7 +3363,7 @@ void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode)
} }
static s8 static s8
wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan, uint32 band, wlc_user_txpwr_antport_to_rfport(phy_info_t *pi, uint chan, u32 band,
u8 rate) u8 rate)
{ {
s8 offset = 0; s8 offset = 0;
...@@ -3389,7 +3389,7 @@ static s8 wlc_phy_env_measure_temperature(phy_info_t *pi) ...@@ -3389,7 +3389,7 @@ static s8 wlc_phy_env_measure_temperature(phy_info_t *pi)
return 0; return 0;
} }
static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, uint32 band) static void wlc_phy_upd_env_txpwr_rate_limits(phy_info_t *pi, u32 band)
{ {
u8 i; u8 i;
s8 temp, vbat; s8 temp, vbat;
...@@ -3414,9 +3414,9 @@ wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset, s8 *ofdmoffset) ...@@ -3414,9 +3414,9 @@ wlc_phy_get_pwrdet_offsets(phy_info_t *pi, s8 *cckoffset, s8 *ofdmoffset)
*ofdmoffset = 0; *ofdmoffset = 0;
} }
uint32 wlc_phy_qdiv_roundup(uint32 dividend, uint32 divisor, u8 precision) u32 wlc_phy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
{ {
uint32 quotient, remainder, roundup, rbit; u32 quotient, remainder, roundup, rbit;
ASSERT(divisor); ASSERT(divisor);
......
drivers/staging/brcm80211/phy/wlc_phy_hal.h
浏览文件 @ 66cbd3ab
...@@ -147,8 +147,8 @@ typedef struct shared_phy_params { ...@@ -147,8 +147,8 @@ typedef struct shared_phy_params {
uint boardtype; uint boardtype;
uint boardrev; uint boardrev;
uint boardvendor; uint boardvendor;
uint32 boardflags; u32 boardflags;
uint32 boardflags2; u32 boardflags2;
} shared_phy_params_t; } shared_phy_params_t;
#ifdef WLC_LOW #ifdef WLC_LOW
...@@ -163,14 +163,14 @@ extern bool wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype, ...@@ -163,14 +163,14 @@ extern bool wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype,
u16 *phyrev, u16 *radioid, u16 *phyrev, u16 *radioid,
u16 *radiover); u16 *radiover);
extern bool wlc_phy_get_encore(wlc_phy_t *pih); extern bool wlc_phy_get_encore(wlc_phy_t *pih);
extern uint32 wlc_phy_get_coreflags(wlc_phy_t *pih); extern u32 wlc_phy_get_coreflags(wlc_phy_t *pih);
extern void wlc_phy_hw_clk_state_upd(wlc_phy_t *ppi, bool newstate); extern void wlc_phy_hw_clk_state_upd(wlc_phy_t *ppi, bool newstate);
extern void wlc_phy_hw_state_upd(wlc_phy_t *ppi, bool newstate); extern void wlc_phy_hw_state_upd(wlc_phy_t *ppi, bool newstate);
extern void wlc_phy_init(wlc_phy_t *ppi, chanspec_t chanspec); extern void wlc_phy_init(wlc_phy_t *ppi, chanspec_t chanspec);
extern void wlc_phy_watchdog(wlc_phy_t *ppi); extern void wlc_phy_watchdog(wlc_phy_t *ppi);
extern int wlc_phy_down(wlc_phy_t *ppi); extern int wlc_phy_down(wlc_phy_t *ppi);
extern uint32 wlc_phy_clk_bwbits(wlc_phy_t *pih); extern u32 wlc_phy_clk_bwbits(wlc_phy_t *pih);
extern void wlc_phy_cal_init(wlc_phy_t *ppi); extern void wlc_phy_cal_init(wlc_phy_t *ppi);
extern void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init); extern void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init);
...@@ -205,7 +205,7 @@ extern void wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint chan, ...@@ -205,7 +205,7 @@ extern void wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint chan,
extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan, extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan,
u8 *_max_, u8 *_min_); u8 *_max_, u8 *_min_);
extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint band, int32 *, extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint band, int32 *,
int32 *, uint32 *); int32 *, u32 *);
extern void wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *, extern void wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *,
chanspec_t chanspec); chanspec_t chanspec);
extern int wlc_phy_txpower_get(wlc_phy_t *ppi, uint *qdbm, bool *override); extern int wlc_phy_txpower_get(wlc_phy_t *ppi, uint *qdbm, bool *override);
...@@ -248,7 +248,7 @@ extern bool wlc_phy_test_ison(wlc_phy_t *ppi); ...@@ -248,7 +248,7 @@ extern bool wlc_phy_test_ison(wlc_phy_t *ppi);
extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent); extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent);
extern void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war); extern void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war);
extern void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt); extern void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt);
extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, uint32 machwcap); extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap);
extern void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end); extern void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end);
......
drivers/staging/brcm80211/phy/wlc_phy_int.h
浏览文件 @ 66cbd3ab
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
#define PHYHAL_TRACE 0x0002 #define PHYHAL_TRACE 0x0002
#define PHYHAL_INFORM 0x0004 #define PHYHAL_INFORM 0x0004
extern uint32 phyhal_msg_level; extern u32 phyhal_msg_level;
#define PHY_INFORM_ON() (phyhal_msg_level & PHYHAL_INFORM) #define PHY_INFORM_ON() (phyhal_msg_level & PHYHAL_INFORM)
#define PHY_THERMAL_ON() (phyhal_msg_level & PHYHAL_THERMAL) #define PHY_THERMAL_ON() (phyhal_msg_level & PHYHAL_THERMAL)
...@@ -292,10 +292,10 @@ typedef struct _phy_table_info { ...@@ -292,10 +292,10 @@ typedef struct _phy_table_info {
typedef struct phytbl_info { typedef struct phytbl_info {
const void *tbl_ptr; const void *tbl_ptr;
uint32 tbl_len; u32 tbl_len;
uint32 tbl_id; u32 tbl_id;
uint32 tbl_offset; u32 tbl_offset;
uint32 tbl_width; u32 tbl_width;
} phytbl_info_t; } phytbl_info_t;
typedef struct { typedef struct {
...@@ -485,8 +485,8 @@ typedef struct _nphy_txgains { ...@@ -485,8 +485,8 @@ typedef struct _nphy_txgains {
typedef struct _nphy_noisevar_buf { typedef struct _nphy_noisevar_buf {
int bufcount; int bufcount;
int tone_id[PHY_NOISEVAR_BUFSIZE]; int tone_id[PHY_NOISEVAR_BUFSIZE];
uint32 noise_vars[PHY_NOISEVAR_BUFSIZE]; u32 noise_vars[PHY_NOISEVAR_BUFSIZE];
uint32 min_noise_vars[PHY_NOISEVAR_BUFSIZE]; u32 min_noise_vars[PHY_NOISEVAR_BUFSIZE];
} phy_noisevar_buf_t; } phy_noisevar_buf_t;
typedef struct { typedef struct {
...@@ -510,7 +510,7 @@ typedef struct { ...@@ -510,7 +510,7 @@ typedef struct {
u16 txiqlocal_bestcoeffs[11]; u16 txiqlocal_bestcoeffs[11];
u16 txiqlocal_bestcoeffs_valid; u16 txiqlocal_bestcoeffs_valid;
uint32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY]; u32 papd_eps_tbl[PHY_PAPD_EPS_TBL_SIZE_LCNPHY];
u16 analog_gain_ref; u16 analog_gain_ref;
u16 lut_begin; u16 lut_begin;
u16 lut_end; u16 lut_end;
...@@ -530,7 +530,7 @@ struct shared_phy { ...@@ -530,7 +530,7 @@ struct shared_phy {
si_t *sih; si_t *sih;
void *physhim; void *physhim;
uint corerev; uint corerev;
uint32 machwcap; u32 machwcap;
bool up; bool up;
bool clk; bool clk;
uint now; uint now;
...@@ -543,8 +543,8 @@ struct shared_phy { ...@@ -543,8 +543,8 @@ struct shared_phy {
uint boardtype; uint boardtype;
uint boardrev; uint boardrev;
uint boardvendor; uint boardvendor;
uint32 boardflags; u32 boardflags;
uint32 boardflags2; u32 boardflags2;
uint bustype; uint bustype;
uint buscorerev; uint buscorerev;
uint fast_timer; uint fast_timer;
...@@ -688,8 +688,8 @@ struct phy_info { ...@@ -688,8 +688,8 @@ struct phy_info {
bool edcrs_threshold_lock; bool edcrs_threshold_lock;
uint32 tr_R_gain_val; u32 tr_R_gain_val;
uint32 tr_T_gain_val; u32 tr_T_gain_val;
s16 ofdm_analog_filt_bw_override; s16 ofdm_analog_filt_bw_override;
s16 cck_analog_filt_bw_override; s16 cck_analog_filt_bw_override;
...@@ -701,11 +701,11 @@ struct phy_info { ...@@ -701,11 +701,11 @@ struct phy_info {
u16 crsglitch_prev; u16 crsglitch_prev;
bool interference_mode_crs; bool interference_mode_crs;
uint32 phy_tx_tone_freq; u32 phy_tx_tone_freq;
uint phy_lastcal; uint phy_lastcal;
bool phy_forcecal; bool phy_forcecal;
bool phy_fixed_noise; bool phy_fixed_noise;
uint32 xtalfreq; u32 xtalfreq;
u8 pdiv; u8 pdiv;
s8 carrier_suppr_disable; s8 carrier_suppr_disable;
...@@ -781,16 +781,16 @@ struct phy_info { ...@@ -781,16 +781,16 @@ struct phy_info {
bool nphy_tableloaded; bool nphy_tableloaded;
s8 nphy_rssisel; s8 nphy_rssisel;
uint32 nphy_bb_mult_save; u32 nphy_bb_mult_save;
u16 nphy_txiqlocal_bestc[11]; u16 nphy_txiqlocal_bestc[11];
bool nphy_txiqlocal_coeffsvalid; bool nphy_txiqlocal_coeffsvalid;
phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2]; phy_txpwrindex_t nphy_txpwrindex[PHY_CORE_NUM_2];
phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2]; phy_pwrctrl_t nphy_pwrctrl_info[PHY_CORE_NUM_2];
u16 cck2gpo; u16 cck2gpo;
uint32 ofdm2gpo; u32 ofdm2gpo;
uint32 ofdm5gpo; u32 ofdm5gpo;
uint32 ofdm5glpo; u32 ofdm5glpo;
uint32 ofdm5ghpo; u32 ofdm5ghpo;
u8 bw402gpo; u8 bw402gpo;
u8 bw405gpo; u8 bw405gpo;
u8 bw405glpo; u8 bw405glpo;
...@@ -811,7 +811,7 @@ struct phy_info { ...@@ -811,7 +811,7 @@ struct phy_info {
u16 mcs5gpo[8]; u16 mcs5gpo[8];
u16 mcs5glpo[8]; u16 mcs5glpo[8];
u16 mcs5ghpo[8]; u16 mcs5ghpo[8];
uint32 nphy_rxcalparams; u32 nphy_rxcalparams;
u8 phy_spuravoid; u8 phy_spuravoid;
bool phy_isspuravoid; bool phy_isspuravoid;
...@@ -863,7 +863,7 @@ struct phy_info { ...@@ -863,7 +863,7 @@ struct phy_info {
u8 nphy_papd_cal_gain_index[2]; u8 nphy_papd_cal_gain_index[2];
s16 nphy_papd_epsilon_offset[2]; s16 nphy_papd_epsilon_offset[2];
bool nphy_papd_recal_enable; bool nphy_papd_recal_enable;
uint32 nphy_papd_recal_counter; u32 nphy_papd_recal_counter;
bool nphy_force_papd_cal; bool nphy_force_papd_cal;
bool nphy_papdcomp; bool nphy_papdcomp;
bool ipa2g_on; bool ipa2g_on;
...@@ -935,8 +935,8 @@ struct phy_info { ...@@ -935,8 +935,8 @@ struct phy_info {
s8 txpwrindex[PHY_CORE_MAX]; s8 txpwrindex[PHY_CORE_MAX];
u8 phycal_tempdelta; u8 phycal_tempdelta;
uint32 mcs20_po; u32 mcs20_po;
uint32 mcs40_po; u32 mcs40_po;
}; };
typedef int32 fixed; typedef int32 fixed;
...@@ -948,8 +948,8 @@ typedef struct _cint32 { ...@@ -948,8 +948,8 @@ typedef struct _cint32 {
typedef struct radio_regs { typedef struct radio_regs {
u16 address; u16 address;
uint32 init_a; u32 init_a;
uint32 init_g; u32 init_g;
u8 do_init_a; u8 do_init_a;
u8 do_init_g; u8 do_init_g;
} radio_regs_t; } radio_regs_t;
...@@ -1018,15 +1018,15 @@ extern void wlc_phy_write_table(phy_info_t *pi, ...@@ -1018,15 +1018,15 @@ extern void wlc_phy_write_table(phy_info_t *pi,
extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset, extern void wlc_phy_table_addr(phy_info_t *pi, uint tbl_id, uint tbl_offset,
u16 tblAddr, u16 tblDataHi, u16 tblAddr, u16 tblDataHi,
u16 tblDataLo); u16 tblDataLo);
extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, uint32 val); extern void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val);
extern void write_phy_channel_reg(phy_info_t *pi, uint val); extern void write_phy_channel_reg(phy_info_t *pi, uint val);
extern void wlc_phy_txpower_update_shm(phy_info_t *pi); extern void wlc_phy_txpower_update_shm(phy_info_t *pi);
extern void wlc_phy_cordic(fixed theta, cint32 *val); extern void wlc_phy_cordic(fixed theta, cint32 *val);
extern u8 wlc_phy_nbits(int32 value); extern u8 wlc_phy_nbits(int32 value);
extern uint32 wlc_phy_sqrt_int(uint32 value); extern u32 wlc_phy_sqrt_int(u32 value);
extern void wlc_phy_compute_dB(uint32 *cmplx_pwr, s8 *p_dB, u8 core); extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi, extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi,
radio_20xx_regs_t *radioregs); radio_20xx_regs_t *radioregs);
...@@ -1036,7 +1036,7 @@ extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs, ...@@ -1036,7 +1036,7 @@ extern uint wlc_phy_init_radio_regs(phy_info_t *pi, radio_regs_t *radioregs,
extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi); extern void wlc_phy_txpower_ipa_upd(phy_info_t *pi);
extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on); extern void wlc_phy_do_dummy_tx(phy_info_t *pi, bool ofdm, bool pa_on);
extern void wlc_phy_papd_decode_epsilon(uint32 epsilon, int32 *eps_real, extern void wlc_phy_papd_decode_epsilon(u32 epsilon, int32 *eps_real,
int32 *eps_imag); int32 *eps_imag);
extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi); extern void wlc_phy_cal_perical_mphase_reset(phy_info_t *pi);
...@@ -1094,7 +1094,7 @@ extern void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode); ...@@ -1094,7 +1094,7 @@ extern void wlc_lcnphy_epa_switch(phy_info_t *pi, bool mode);
extern void wlc_2064_vco_cal(phy_info_t *pi); extern void wlc_2064_vco_cal(phy_info_t *pi);
extern void wlc_phy_txpower_recalc_target(phy_info_t *pi); extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
extern uint32 wlc_phy_qdiv_roundup(uint32 dividend, uint32 divisor, extern u32 wlc_phy_qdiv_roundup(u32 dividend, u32 divisor,
u8 precision); u8 precision);
#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18 #define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
...@@ -1133,8 +1133,8 @@ extern int32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, int32 gain_index); ...@@ -1133,8 +1133,8 @@ extern int32 wlc_lcnphy_rx_signal_power(phy_info_t *pi, int32 gain_index);
typedef struct _phy_iq_est { typedef struct _phy_iq_est {
int32 iq_prod; int32 iq_prod;
uint32 i_pwr; u32 i_pwr;
uint32 q_pwr; u32 q_pwr;
} phy_iq_est_t; } phy_iq_est_t;
extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable); extern void wlc_phy_stay_in_carriersearch_nphy(phy_info_t *pi, bool enable);
...@@ -1148,10 +1148,10 @@ extern void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode); ...@@ -1148,10 +1148,10 @@ extern void wlc_nphy_deaf_mode(phy_info_t *pi, bool mode);
0x72, 0x74, 0x73) 0x72, 0x74, 0x73)
#define wlc_nphy_table_data_write(pi, w, v) wlc_phy_table_data_write((pi), (w), (v)) #define wlc_nphy_table_data_write(pi, w, v) wlc_phy_table_data_write((pi), (w), (v))
extern void wlc_phy_table_read_nphy(phy_info_t *pi, uint32, uint32 l, uint32 o, extern void wlc_phy_table_read_nphy(phy_info_t *pi, u32, u32 l, u32 o,
uint32 w, void *d); u32 w, void *d);
extern void wlc_phy_table_write_nphy(phy_info_t *pi, uint32, uint32, uint32, extern void wlc_phy_table_write_nphy(phy_info_t *pi, u32, u32, u32,
uint32, const void *); u32, const void *);
#define PHY_IPA(pi) \ #define PHY_IPA(pi) \
((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \ ((pi->ipa2g_on && CHSPEC_IS2G(pi->radio_chanspec)) || \
...@@ -1206,7 +1206,7 @@ extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi); ...@@ -1206,7 +1206,7 @@ extern void wlc_phy_rssi_cal_nphy(phy_info_t *pi);
extern int wlc_phy_aci_scan_nphy(phy_info_t *pi); extern int wlc_phy_aci_scan_nphy(phy_info_t *pi);
extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower, extern void wlc_phy_cal_txgainctrl_nphy(phy_info_t *pi, int32 dBm_targetpower,
bool debug); bool debug);
extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, uint32 f_kHz, u16 max_val, extern int wlc_phy_tx_tone_nphy(phy_info_t *pi, u32 f_kHz, u16 max_val,
u8 mode, u8, bool); u8 mode, u8, bool);
extern void wlc_phy_stopplayback_nphy(phy_info_t *pi); extern void wlc_phy_stopplayback_nphy(phy_info_t *pi);
extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf, extern void wlc_phy_est_tonepwr_nphy(phy_info_t *pi, int32 *qdBm_pwrbuf,
......
drivers/staging/brcm80211/phy/wlc_phy_lcn.h
浏览文件 @ 66cbd3ab
...@@ -27,7 +27,7 @@ struct phy_info_lcnphy { ...@@ -27,7 +27,7 @@ struct phy_info_lcnphy {
bool lcnphy_recal; bool lcnphy_recal;
u8 lcnphy_rc_cap; u8 lcnphy_rc_cap;
uint32 lcnphy_mcs20_po; u32 lcnphy_mcs20_po;
u8 lcnphy_tr_isolation_mid; u8 lcnphy_tr_isolation_mid;
u8 lcnphy_tr_isolation_low; u8 lcnphy_tr_isolation_low;
...@@ -69,17 +69,17 @@ struct phy_info_lcnphy { ...@@ -69,17 +69,17 @@ struct phy_info_lcnphy {
s8 lcnphy_tx_power_idx_override; s8 lcnphy_tx_power_idx_override;
u16 lcnphy_noise_samples; u16 lcnphy_noise_samples;
uint32 lcnphy_papdRxGnIdx; u32 lcnphy_papdRxGnIdx;
uint32 lcnphy_papd_rxGnCtrl_init; u32 lcnphy_papd_rxGnCtrl_init;
uint32 lcnphy_gain_idx_14_lowword; u32 lcnphy_gain_idx_14_lowword;
uint32 lcnphy_gain_idx_14_hiword; u32 lcnphy_gain_idx_14_hiword;
uint32 lcnphy_gain_idx_27_lowword; u32 lcnphy_gain_idx_27_lowword;
uint32 lcnphy_gain_idx_27_hiword; u32 lcnphy_gain_idx_27_hiword;
s16 lcnphy_ofdmgainidxtableoffset; s16 lcnphy_ofdmgainidxtableoffset;
s16 lcnphy_dsssgainidxtableoffset; s16 lcnphy_dsssgainidxtableoffset;
uint32 lcnphy_tr_R_gain_val; u32 lcnphy_tr_R_gain_val;
uint32 lcnphy_tr_T_gain_val; u32 lcnphy_tr_T_gain_val;
s8 lcnphy_input_pwr_offset_db; s8 lcnphy_input_pwr_offset_db;
u16 lcnphy_Med_Low_Gain_db; u16 lcnphy_Med_Low_Gain_db;
u16 lcnphy_Very_Low_Gain_db; u16 lcnphy_Very_Low_Gain_db;
......
drivers/staging/brcm80211/phy/wlc_phytbl_lcn.c
浏览文件 @ 66cbd3ab
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
#include <wlc_phy_int.h> #include <wlc_phy_int.h>
#include <wlc_phytbl_lcn.h> #include <wlc_phytbl_lcn.h>
const uint32 dot11lcn_gain_tbl_rev0[] = { const u32 dot11lcn_gain_tbl_rev0[] = {
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
...@@ -118,7 +118,7 @@ const uint32 dot11lcn_gain_tbl_rev0[] = { ...@@ -118,7 +118,7 @@ const uint32 dot11lcn_gain_tbl_rev0[] = {
0x00000000, 0x00000000,
}; };
const uint32 dot11lcn_gain_tbl_rev1[] = { const u32 dot11lcn_gain_tbl_rev1[] = {
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
...@@ -258,7 +258,7 @@ const u16 dot11lcn_aux_gain_idx_tbl_rev0[] = { ...@@ -258,7 +258,7 @@ const u16 dot11lcn_aux_gain_idx_tbl_rev0[] = {
0x0000, 0x0000,
}; };
const uint32 dot11lcn_gain_idx_tbl_rev0[] = { const u32 dot11lcn_gain_idx_tbl_rev0[] = {
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x10000000, 0x10000000,
...@@ -521,7 +521,7 @@ const u8 dot11lcn_gain_val_tbl_2G[] = { ...@@ -521,7 +521,7 @@ const u8 dot11lcn_gain_val_tbl_2G[] = {
0x00 0x00
}; };
const uint32 dot11lcn_gain_idx_tbl_2G[] = { const u32 dot11lcn_gain_idx_tbl_2G[] = {
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
...@@ -676,7 +676,7 @@ const uint32 dot11lcn_gain_idx_tbl_2G[] = { ...@@ -676,7 +676,7 @@ const uint32 dot11lcn_gain_idx_tbl_2G[] = {
0x00000000 0x00000000
}; };
const uint32 dot11lcn_gain_tbl_2G[] = { const u32 dot11lcn_gain_tbl_2G[] = {
0x00000000, 0x00000000,
0x00000004, 0x00000004,
0x00000008, 0x00000008,
...@@ -775,7 +775,7 @@ const uint32 dot11lcn_gain_tbl_2G[] = { ...@@ -775,7 +775,7 @@ const uint32 dot11lcn_gain_tbl_2G[] = {
0x00000000 0x00000000
}; };
const uint32 dot11lcn_gain_tbl_extlna_2G[] = { const u32 dot11lcn_gain_tbl_extlna_2G[] = {
0x00000000, 0x00000000,
0x00000004, 0x00000004,
0x00000008, 0x00000008,
...@@ -986,7 +986,7 @@ const u8 dot11lcn_gain_val_tbl_extlna_2G[] = { ...@@ -986,7 +986,7 @@ const u8 dot11lcn_gain_val_tbl_extlna_2G[] = {
0x00 0x00
}; };
const uint32 dot11lcn_gain_idx_tbl_extlna_2G[] = { const u32 dot11lcn_gain_idx_tbl_extlna_2G[] = {
0x00000000, 0x00000000,
0x00000040, 0x00000040,
0x00000000, 0x00000000,
...@@ -1141,7 +1141,7 @@ const uint32 dot11lcn_gain_idx_tbl_extlna_2G[] = { ...@@ -1141,7 +1141,7 @@ const uint32 dot11lcn_gain_idx_tbl_extlna_2G[] = {
0x00000000 0x00000000
}; };
const uint32 dot11lcn_aux_gain_idx_tbl_5G[] = { const u32 dot11lcn_aux_gain_idx_tbl_5G[] = {
0x0000, 0x0000,
0x0000, 0x0000,
0x0000, 0x0000,
...@@ -1182,7 +1182,7 @@ const uint32 dot11lcn_aux_gain_idx_tbl_5G[] = { ...@@ -1182,7 +1182,7 @@ const uint32 dot11lcn_aux_gain_idx_tbl_5G[] = {
0x0000 0x0000
}; };
const uint32 dot11lcn_gain_val_tbl_5G[] = { const u32 dot11lcn_gain_val_tbl_5G[] = {
0xf7, 0xf7,
0xfd, 0xfd,
0x00, 0x00,
...@@ -1253,7 +1253,7 @@ const uint32 dot11lcn_gain_val_tbl_5G[] = { ...@@ -1253,7 +1253,7 @@ const uint32 dot11lcn_gain_val_tbl_5G[] = {
0x00 0x00
}; };
const uint32 dot11lcn_gain_idx_tbl_5G[] = { const u32 dot11lcn_gain_idx_tbl_5G[] = {
0x00000000, 0x00000000,
0x00000000, 0x00000000,
0x00000000, 0x00000000,
...@@ -1408,7 +1408,7 @@ const uint32 dot11lcn_gain_idx_tbl_5G[] = { ...@@ -1408,7 +1408,7 @@ const uint32 dot11lcn_gain_idx_tbl_5G[] = {
0x00000000 0x00000000
}; };
const uint32 dot11lcn_gain_tbl_5G[] = { const u32 dot11lcn_gain_tbl_5G[] = {
0x00000000, 0x00000000,
0x00000040, 0x00000040,
0x00000080, 0x00000080,
...@@ -1609,19 +1609,19 @@ const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[] = { ...@@ -1609,19 +1609,19 @@ const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[] = {
17, 0, 8} 17, 0, 8}
}; };
const uint32 dot11lcnphytbl_rx_gain_info_sz_rev0 = const u32 dot11lcnphytbl_rx_gain_info_sz_rev0 =
sizeof(dot11lcnphytbl_rx_gain_info_rev0) / sizeof(dot11lcnphytbl_rx_gain_info_rev0) /
sizeof(dot11lcnphytbl_rx_gain_info_rev0[0]); sizeof(dot11lcnphytbl_rx_gain_info_rev0[0]);
const uint32 dot11lcnphytbl_rx_gain_info_sz_rev1 = const u32 dot11lcnphytbl_rx_gain_info_sz_rev1 =
sizeof(dot11lcnphytbl_rx_gain_info_rev1) / sizeof(dot11lcnphytbl_rx_gain_info_rev1) /
sizeof(dot11lcnphytbl_rx_gain_info_rev1[0]); sizeof(dot11lcnphytbl_rx_gain_info_rev1[0]);
const uint32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz = const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz =
sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2) / sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2) /
sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2[0]); sizeof(dot11lcnphytbl_rx_gain_info_2G_rev2[0]);
const uint32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz = const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz =
sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) / sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2) /
sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]); sizeof(dot11lcnphytbl_rx_gain_info_5G_rev2[0]);
...@@ -1759,7 +1759,7 @@ const u16 dot11lcn_noise_scale_tbl_rev0[] = { ...@@ -1759,7 +1759,7 @@ const u16 dot11lcn_noise_scale_tbl_rev0[] = {
0x0000, 0x0000,
}; };
const uint32 dot11lcn_fltr_ctrl_tbl_rev0[] = { const u32 dot11lcn_fltr_ctrl_tbl_rev0[] = {
0x000141f8, 0x000141f8,
0x000021f8, 0x000021f8,
0x000021fb, 0x000021fb,
...@@ -1772,7 +1772,7 @@ const uint32 dot11lcn_fltr_ctrl_tbl_rev0[] = { ...@@ -1772,7 +1772,7 @@ const uint32 dot11lcn_fltr_ctrl_tbl_rev0[] = {
0x0000024b, 0x0000024b,
}; };
const uint32 dot11lcn_ps_ctrl_tbl_rev0[] = { const u32 dot11lcn_ps_ctrl_tbl_rev0[] = {
0x00100001, 0x00100001,
0x00200010, 0x00200010,
0x00300001, 0x00300001,
...@@ -2612,7 +2612,7 @@ const u16 dot11lcn_iq_local_tbl_rev0[] = { ...@@ -2612,7 +2612,7 @@ const u16 dot11lcn_iq_local_tbl_rev0[] = {
0x0000, 0x0000,
}; };
const uint32 dot11lcn_papd_compdelta_tbl_rev0[] = { const u32 dot11lcn_papd_compdelta_tbl_rev0[] = {
0x00080000, 0x00080000,
0x00080000, 0x00080000,
0x00080000, 0x00080000,
...@@ -2858,7 +2858,7 @@ const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250 = { ...@@ -2858,7 +2858,7 @@ const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250 = {
sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[0]), 15, 0, 16 sizeof(dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[0]), 15, 0, 16
}; };
const uint32 dot11lcnphytbl_info_sz_rev0 = const u32 dot11lcnphytbl_info_sz_rev0 =
sizeof(dot11lcnphytbl_info_rev0) / sizeof(dot11lcnphytbl_info_rev0[0]); sizeof(dot11lcnphytbl_info_rev0) / sizeof(dot11lcnphytbl_info_rev0[0]);
const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[128] = { const lcnphy_tx_gain_tbl_entry dot11lcnphy_2GHz_extPA_gaintable_rev0[128] = {
......
drivers/staging/brcm80211/phy/wlc_phytbl_lcn.h
浏览文件 @ 66cbd3ab
...@@ -17,19 +17,19 @@ ...@@ -17,19 +17,19 @@
typedef phytbl_info_t dot11lcnphytbl_info_t; typedef phytbl_info_t dot11lcnphytbl_info_t;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev0[]; extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_rev0[];
extern const uint32 dot11lcnphytbl_rx_gain_info_sz_rev0; extern const u32 dot11lcnphytbl_rx_gain_info_sz_rev0;
extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313; extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313;
extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa; extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa;
extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa_combo; extern const dot11lcnphytbl_info_t dot11lcn_sw_ctrl_tbl_info_4313_epa_combo;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_info_rev0[]; extern const dot11lcnphytbl_info_t dot11lcnphytbl_info_rev0[];
extern const uint32 dot11lcnphytbl_info_sz_rev0; extern const u32 dot11lcnphytbl_info_sz_rev0;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_2G_rev2[]; extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_2G_rev2[];
extern const uint32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz; extern const u32 dot11lcnphytbl_rx_gain_info_2G_rev2_sz;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_5G_rev2[]; extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_5G_rev2[];
extern const uint32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz; extern const u32 dot11lcnphytbl_rx_gain_info_5G_rev2_sz;
extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[]; extern const dot11lcnphytbl_info_t dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[];
......
drivers/staging/brcm80211/phy/wlc_phytbl_n.h
浏览文件 @ 66cbd3ab
...@@ -20,20 +20,20 @@ typedef phytbl_info_t mimophytbl_info_t; ...@@ -20,20 +20,20 @@ typedef phytbl_info_t mimophytbl_info_t;
extern const mimophytbl_info_t mimophytbl_info_rev0[], extern const mimophytbl_info_t mimophytbl_info_rev0[],
mimophytbl_info_rev0_volatile[]; mimophytbl_info_rev0_volatile[];
extern const uint32 mimophytbl_info_sz_rev0, mimophytbl_info_sz_rev0_volatile; extern const u32 mimophytbl_info_sz_rev0, mimophytbl_info_sz_rev0_volatile;
extern const mimophytbl_info_t mimophytbl_info_rev3[], extern const mimophytbl_info_t mimophytbl_info_rev3[],
mimophytbl_info_rev3_volatile[], mimophytbl_info_rev3_volatile1[], mimophytbl_info_rev3_volatile[], mimophytbl_info_rev3_volatile1[],
mimophytbl_info_rev3_volatile2[], mimophytbl_info_rev3_volatile3[]; mimophytbl_info_rev3_volatile2[], mimophytbl_info_rev3_volatile3[];
extern const uint32 mimophytbl_info_sz_rev3, mimophytbl_info_sz_rev3_volatile, extern const u32 mimophytbl_info_sz_rev3, mimophytbl_info_sz_rev3_volatile,
mimophytbl_info_sz_rev3_volatile1, mimophytbl_info_sz_rev3_volatile2, mimophytbl_info_sz_rev3_volatile1, mimophytbl_info_sz_rev3_volatile2,
mimophytbl_info_sz_rev3_volatile3; mimophytbl_info_sz_rev3_volatile3;
extern const uint32 noise_var_tbl_rev3[]; extern const u32 noise_var_tbl_rev3[];
extern const mimophytbl_info_t mimophytbl_info_rev7[]; extern const mimophytbl_info_t mimophytbl_info_rev7[];
extern const uint32 mimophytbl_info_sz_rev7; extern const u32 mimophytbl_info_sz_rev7;
extern const uint32 noise_var_tbl_rev7[]; extern const u32 noise_var_tbl_rev7[];
extern const mimophytbl_info_t mimophytbl_info_rev16[]; extern const mimophytbl_info_t mimophytbl_info_rev16[];
extern const uint32 mimophytbl_info_sz_rev16; extern const u32 mimophytbl_info_sz_rev16;
drivers/staging/brcm80211/sys/wl_dbg.h
浏览文件 @ 66cbd3ab
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
#define _wl_dbg_h_ #define _wl_dbg_h_
/* wl_msg_level is a bit vector with defs in wlioctl.h */ /* wl_msg_level is a bit vector with defs in wlioctl.h */
extern uint32 wl_msg_level; extern u32 wl_msg_level;
#define WL_PRINT(args) printf args #define WL_PRINT(args) printf args
#define WL_NONE(args) #define WL_NONE(args)
...@@ -42,7 +42,7 @@ extern uint32 wl_msg_level; ...@@ -42,7 +42,7 @@ extern uint32 wl_msg_level;
#define WL_AMPDU_HWTXS_VAL 0x00000040 /* AMPDU_HWTXS */ #define WL_AMPDU_HWTXS_VAL 0x00000040 /* AMPDU_HWTXS */
#define WL_AMPDU_HWDBG_VAL 0x00000080 /* AMPDU_DBG */ #define WL_AMPDU_HWDBG_VAL 0x00000080 /* AMPDU_DBG */
extern uint32 wl_ampdu_dbg; extern u32 wl_ampdu_dbg;
#define WL_AMPDU_UPDN(args) do {if (wl_ampdu_dbg & WL_AMPDU_UPDN_VAL) {WL_AMPDU(args); } } while (0) #define WL_AMPDU_UPDN(args) do {if (wl_ampdu_dbg & WL_AMPDU_UPDN_VAL) {WL_AMPDU(args); } } while (0)
#define WL_AMPDU_RX(args) do {if (wl_ampdu_dbg & WL_AMPDU_RX_VAL) {WL_AMPDU(args); } } while (0) #define WL_AMPDU_RX(args) do {if (wl_ampdu_dbg & WL_AMPDU_RX_VAL) {WL_AMPDU(args); } } while (0)
......
drivers/staging/brcm80211/sys/wl_export.h
浏览文件 @ 66cbd3ab
...@@ -24,11 +24,11 @@ struct wlc_if; ...@@ -24,11 +24,11 @@ struct wlc_if;
extern void wl_init(struct wl_info *wl); extern void wl_init(struct wl_info *wl);
extern uint wl_reset(struct wl_info *wl); extern uint wl_reset(struct wl_info *wl);
extern void wl_intrson(struct wl_info *wl); extern void wl_intrson(struct wl_info *wl);
extern uint32 wl_intrsoff(struct wl_info *wl); extern u32 wl_intrsoff(struct wl_info *wl);
extern void wl_intrsrestore(struct wl_info *wl, uint32 macintmask); extern void wl_intrsrestore(struct wl_info *wl, u32 macintmask);
extern void wl_event(struct wl_info *wl, char *ifname, wlc_event_t *e); extern void wl_event(struct wl_info *wl, char *ifname, wlc_event_t *e);
extern void wl_event_sendup(struct wl_info *wl, const wlc_event_t *e, extern void wl_event_sendup(struct wl_info *wl, const wlc_event_t *e,
u8 *data, uint32 len); u8 *data, u32 len);
extern int wl_up(struct wl_info *wl); extern int wl_up(struct wl_info *wl);
extern void wl_down(struct wl_info *wl); extern void wl_down(struct wl_info *wl);
extern void wl_txflowcontrol(struct wl_info *wl, struct wl_if *wlif, bool state, extern void wl_txflowcontrol(struct wl_info *wl, struct wl_if *wlif, bool state,
......
drivers/staging/brcm80211/sys/wl_mac80211.c
浏览文件 @ 66cbd3ab
...@@ -475,7 +475,7 @@ wl_ops_bss_info_changed(struct ieee80211_hw *hw, ...@@ -475,7 +475,7 @@ wl_ops_bss_info_changed(struct ieee80211_hw *hw,
} }
if (changed & BSS_CHANGED_BASIC_RATES) { if (changed & BSS_CHANGED_BASIC_RATES) {
WL_NONE(("Need to change Basic Rates:\t0x%x! Implement me\n", WL_NONE(("Need to change Basic Rates:\t0x%x! Implement me\n",
(uint32) info->basic_rates)); (u32) info->basic_rates));
/* Basic rateset changed */ /* Basic rateset changed */
} }
if (changed & BSS_CHANGED_BEACON_INT) { if (changed & BSS_CHANGED_BEACON_INT) {
...@@ -982,8 +982,8 @@ static wl_info_t *wl_attach(u16 vendor, u16 device, unsigned long regs, ...@@ -982,8 +982,8 @@ static wl_info_t *wl_attach(u16 vendor, u16 device, unsigned long regs,
} }
#ifdef WLC_HIGH_ONLY #ifdef WLC_HIGH_ONLY
static void *wl_dbus_probe_cb(void *arg, const char *desc, uint32 bustype, static void *wl_dbus_probe_cb(void *arg, const char *desc, u32 bustype,
uint32 hdrlen) u32 hdrlen)
{ {
wl_info_t *wl; wl_info_t *wl;
WL_ERROR(("%s:\n", __func__)); WL_ERROR(("%s:\n", __func__));
...@@ -1305,7 +1305,7 @@ wl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -1305,7 +1305,7 @@ wl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
int rc; int rc;
wl_info_t *wl; wl_info_t *wl;
struct ieee80211_hw *hw; struct ieee80211_hw *hw;
uint32 val; u32 val;
ASSERT(pdev); ASSERT(pdev);
...@@ -1388,7 +1388,7 @@ static int wl_resume(struct pci_dev *pdev) ...@@ -1388,7 +1388,7 @@ static int wl_resume(struct pci_dev *pdev)
wl_info_t *wl; wl_info_t *wl;
struct ieee80211_hw *hw; struct ieee80211_hw *hw;
int err = 0; int err = 0;
uint32 val; u32 val;
WL_TRACE(("wl: wl_resume\n")); WL_TRACE(("wl: wl_resume\n"));
hw = pci_get_drvdata(pdev); hw = pci_get_drvdata(pdev);
...@@ -1485,7 +1485,7 @@ static int __init wl_module_init(void) ...@@ -1485,7 +1485,7 @@ static int __init wl_module_init(void)
} }
#ifndef WLC_HIGH_ONLY #ifndef WLC_HIGH_ONLY
{ {
extern uint32 phyhal_msg_level; extern u32 phyhal_msg_level;
if (phymsglevel != 0xdeadbeef) if (phymsglevel != 0xdeadbeef)
phyhal_msg_level = phymsglevel; phyhal_msg_level = phymsglevel;
...@@ -1727,11 +1727,11 @@ bool wl_alloc_dma_resources(wl_info_t *wl, uint addrwidth) ...@@ -1727,11 +1727,11 @@ bool wl_alloc_dma_resources(wl_info_t *wl, uint addrwidth)
return TRUE; return TRUE;
} }
uint32 BCMFASTPATH wl_intrsoff(wl_info_t *wl) u32 BCMFASTPATH wl_intrsoff(wl_info_t *wl)
{ {
#if defined(WLC_LOW) #if defined(WLC_LOW)
unsigned long flags; unsigned long flags;
uint32 status; u32 status;
INT_LOCK(wl, flags); INT_LOCK(wl, flags);
status = wlc_intrsoff(wl->wlc); status = wlc_intrsoff(wl->wlc);
...@@ -1742,7 +1742,7 @@ uint32 BCMFASTPATH wl_intrsoff(wl_info_t *wl) ...@@ -1742,7 +1742,7 @@ uint32 BCMFASTPATH wl_intrsoff(wl_info_t *wl)
#endif /* WLC_LOW */ #endif /* WLC_LOW */
} }
void wl_intrsrestore(wl_info_t *wl, uint32 macintmask) void wl_intrsrestore(wl_info_t *wl, u32 macintmask)
{ {
#if defined(WLC_LOW) #if defined(WLC_LOW)
unsigned long flags; unsigned long flags;
...@@ -2052,9 +2052,9 @@ static int wl_linux_watchdog(void *ctx) ...@@ -2052,9 +2052,9 @@ static int wl_linux_watchdog(void *ctx)
} }
struct wl_fw_hdr { struct wl_fw_hdr {
uint32 offset; u32 offset;
uint32 len; u32 len;
uint32 idx; u32 idx;
}; };
#ifdef WLC_HIGH_ONLY #ifdef WLC_HIGH_ONLY
...@@ -2249,7 +2249,7 @@ static void wl_rpc_dispatch_schedule(void *ctx, struct rpc_buf *buf) ...@@ -2249,7 +2249,7 @@ static void wl_rpc_dispatch_schedule(void *ctx, struct rpc_buf *buf)
bcm_xdr_buf_init(&b, bcm_rpc_buf_data(wl->rpc_th, buf), bcm_xdr_buf_init(&b, bcm_rpc_buf_data(wl->rpc_th, buf),
bcm_rpc_buf_len_get(wl->rpc_th, buf)); bcm_rpc_buf_len_get(wl->rpc_th, buf));
err = bcm_xdr_unpack_uint32(&b, &rpc_id); err = bcm_xdr_unpack_u32(&b, &rpc_id);
ASSERT(!err); ASSERT(!err);
WL_TRACE(("%s: Dispatch id %s\n", __func__, WL_TRACE(("%s: Dispatch id %s\n", __func__,
WLC_RPC_ID_LOOKUP(rpc_name_tbl, rpc_id))); WLC_RPC_ID_LOOKUP(rpc_name_tbl, rpc_id)));
...@@ -2283,7 +2283,7 @@ char *wl_firmwares[WL_MAX_FW] = { ...@@ -2283,7 +2283,7 @@ char *wl_firmwares[WL_MAX_FW] = {
}; };
#ifdef WLC_LOW #ifdef WLC_LOW
int wl_ucode_init_buf(wl_info_t *wl, void **pbuf, uint32 idx) int wl_ucode_init_buf(wl_info_t *wl, void **pbuf, u32 idx)
{ {
int i, entry; int i, entry;
const u8 *pdata; const u8 *pdata;
...@@ -2309,7 +2309,7 @@ int wl_ucode_init_buf(wl_info_t *wl, void **pbuf, uint32 idx) ...@@ -2309,7 +2309,7 @@ int wl_ucode_init_buf(wl_info_t *wl, void **pbuf, uint32 idx)
return -1; return -1;
} }
int wl_ucode_init_uint(wl_info_t *wl, uint32 *data, uint32 idx) int wl_ucode_init_uint(wl_info_t *wl, u32 *data, u32 idx)
{ {
int i, entry; int i, entry;
const u8 *pdata; const u8 *pdata;
...@@ -2321,7 +2321,7 @@ int wl_ucode_init_uint(wl_info_t *wl, uint32 *data, uint32 idx) ...@@ -2321,7 +2321,7 @@ int wl_ucode_init_uint(wl_info_t *wl, uint32 *data, uint32 idx)
if (hdr->idx == idx) { if (hdr->idx == idx) {
pdata = wl->fw.fw_bin[i]->data + hdr->offset; pdata = wl->fw.fw_bin[i]->data + hdr->offset;
ASSERT(hdr->len == 4); ASSERT(hdr->len == 4);
*data = *((uint32 *) pdata); *data = *((u32 *) pdata);
return 0; return 0;
} }
} }
......
drivers/staging/brcm80211/sys/wl_ucode.h
浏览文件 @ 66cbd3ab
...@@ -18,7 +18,7 @@ ...@@ -18,7 +18,7 @@
typedef struct d11init { typedef struct d11init {
u16 addr; u16 addr;
u16 size; u16 size;
uint32 value; u32 value;
} d11init_t; } d11init_t;
extern d11init_t *d11lcn0bsinitvals24; extern d11init_t *d11lcn0bsinitvals24;
...@@ -30,9 +30,9 @@ extern d11init_t *d11lcn2initvals24; ...@@ -30,9 +30,9 @@ extern d11init_t *d11lcn2initvals24;
extern d11init_t *d11n0absinitvals16; extern d11init_t *d11n0absinitvals16;
extern d11init_t *d11n0bsinitvals16; extern d11init_t *d11n0bsinitvals16;
extern d11init_t *d11n0initvals16; extern d11init_t *d11n0initvals16;
extern uint32 *bcm43xx_16_mimo; extern u32 *bcm43xx_16_mimo;
extern uint32 bcm43xx_16_mimosz; extern u32 bcm43xx_16_mimosz;
extern uint32 *bcm43xx_24_lcn; extern u32 *bcm43xx_24_lcn;
extern uint32 bcm43xx_24_lcnsz; extern u32 bcm43xx_24_lcnsz;
extern uint32 *bcm43xx_bommajor; extern u32 *bcm43xx_bommajor;
extern uint32 *bcm43xx_bomminor; extern u32 *bcm43xx_bomminor;
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