提交 6261ff96 编写于 作者: L liweihang 提交者: Xie XiuQi

net/RDMA: change back code about set_default_reset_request

driver inclusion
category: bugfix
bugzilla: NA
CVE: NA

Two previous patch "net: hns3: delay setting of reset level for hw errors
until slot_reset is called" and "RDMA/hns: modification for the changed
set_default_reset_request interface" is hard to upstream to community
because they belong to two different repositories. We modify patch of
hns to avoid changing the set_default_reset_request(), at the same time,
we change back related code in roce.
Signed-off-by: Nliweihang <liweihang@huawei.com>
Reviewed-by: Nlipeng <lipeng321@huawei.com>
Reviewed-by: NYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 915ba65e
......@@ -5581,7 +5581,6 @@ static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
{
struct hns_roce_dev *hr_dev = dev_id;
struct device *dev = hr_dev->dev;
unsigned long reset_level = 0;
int int_work = 0;
__le32 int_st;
__le32 int_en;
......@@ -5602,10 +5601,8 @@ static irqreturn_t hns_roce_v2_msix_interrupt_abn(int irq, void *dev_id)
le32_to_cpu(int_st));
/* Set reset level for the following reset_event() call */
if (ops->set_default_reset_request) {
set_bit(HNAE3_FUNC_RESET, &reset_level);
ops->set_default_reset_request(ae_dev, &reset_level);
}
if (ops->set_default_reset_request)
ops->set_default_reset_request(ae_dev, HNAE3_FUNC_RESET);
if (ops->reset_event)
ops->reset_event(pdev, NULL);
......
......@@ -470,9 +470,10 @@ struct hnae3_ae_ops {
u16 vlan, u8 qos, __be16 proto);
int (*enable_hw_strip_rxvtag)(struct hnae3_handle *handle, bool enable);
void (*reset_event)(struct pci_dev *pdev, struct hnae3_handle *handle);
enum hnae3_reset_type
(*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,
unsigned long *rst_type);
enum hnae3_reset_type (*get_reset_level)(struct hnae3_ae_dev *ae_dev,
unsigned long *addr);
void (*set_default_reset_request)(struct hnae3_ae_dev *ae_dev,
enum hnae3_reset_type rst_type);
void (*get_channels)(struct hnae3_handle *handle,
struct ethtool_channels *ch);
void (*get_tqps_and_rss_info)(struct hnae3_handle *h,
......
......@@ -2020,24 +2020,23 @@ static pci_ers_result_t hns3_error_detected(struct pci_dev *pdev,
static pci_ers_result_t hns3_slot_reset(struct pci_dev *pdev)
{
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
struct device *dev = &pdev->dev;
const struct hnae3_ae_ops *ops = ae_dev->ops;
enum hnae3_reset_type reset_type;
struct device *dev = &pdev->dev;
if (!ae_dev || !ae_dev->ops)
return PCI_ERS_RESULT_NONE;
/* request the reset */
if (ae_dev->ops->reset_event) {
if (ops->reset_event) {
if (!ae_dev->override_pci_need_reset) {
reset_type =
ae_dev->ops->set_default_reset_request(ae_dev,
reset_type = ops->get_reset_level(ae_dev,
&ae_dev->hw_err_reset_req);
if (reset_type != HNAE3_NONE_RESET) {
dev_info(dev,
"requesting reset due to PCI error\n");
ae_dev->ops->reset_event(pdev, NULL);
}
ops->set_default_reset_request(ae_dev, reset_type);
dev_info(dev, "requesting reset due to PCI error\n");
ops->reset_event(pdev, NULL);
}
return PCI_ERS_RESULT_RECOVERED;
}
......
......@@ -3168,10 +3168,11 @@ static void hclge_do_reset(struct hclge_dev *hdev)
}
}
enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
unsigned long *addr)
{
enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
struct hclge_dev *hdev = ae_dev->priv;
/* return the highest priority reset level amongst all */
if (test_bit(HNAE3_IMP_RESET, addr)) {
......@@ -3516,7 +3517,7 @@ static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
return;
else if (hdev->default_reset_request)
hdev->reset_level =
hclge_get_reset_level(hdev,
hclge_get_reset_level(ae_dev,
&hdev->default_reset_request);
else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ)))
hdev->reset_level = HNAE3_FUNC_RESET;
......@@ -3532,18 +3533,12 @@ static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
hdev->reset_level++;
}
static enum hnae3_reset_type
hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
unsigned long *rst_type)
static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
enum hnae3_reset_type rst_type)
{
struct hclge_dev *hdev = ae_dev->priv;
enum hnae3_reset_type reset_type;
reset_type = hclge_get_reset_level(hdev, rst_type);
if (reset_type != HNAE3_NONE_RESET)
set_bit(reset_type, &hdev->default_reset_request);
return reset_type;
set_bit(rst_type, &hdev->default_reset_request);
}
static void hclge_reset_timer(struct timer_list *t)
......@@ -3568,6 +3563,8 @@ bool hclge_reset_done(struct hnae3_handle *handle, bool done)
static void hclge_reset_subtask(struct hclge_dev *hdev)
{
struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
/* check if there is any ongoing reset in the hardware. This status can
* be checked from reset_pending. If there is then, we need to wait for
* hardware to complete reset.
......@@ -3578,12 +3575,12 @@ static void hclge_reset_subtask(struct hclge_dev *hdev)
* now.
*/
hdev->last_reset_time = jiffies;
hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_pending);
if (hdev->reset_type != HNAE3_NONE_RESET)
hclge_reset(hdev);
/* check if we got any *new* reset requests to be honored */
hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
hdev->reset_type = hclge_get_reset_level(ae_dev, &hdev->reset_request);
if (hdev->reset_type != HNAE3_NONE_RESET)
hclge_do_reset(hdev);
......@@ -8946,11 +8943,16 @@ static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
/* Log and clear the hw errors those already occurred */
hclge_handle_all_hns_hw_errors(ae_dev);
/* request delayed reset for the error recovery because an immediate
* global reset on a PF affecting pending initialization of other PFs
*/
if (ae_dev->hw_err_reset_req) {
hclge_set_def_reset_request(ae_dev, &ae_dev->hw_err_reset_req);
enum hnae3_reset_type reset_level;
reset_level = hclge_get_reset_level(ae_dev,
&ae_dev->hw_err_reset_req);
hclge_set_def_reset_request(ae_dev, reset_level);
mod_timer(&hdev->reset_timer,
jiffies + HCLGE_RESET_INTERVAL);
}
......@@ -9529,6 +9531,7 @@ struct hnae3_ae_ops hclge_ops = {
.set_vf_vlan_filter = hclge_set_vf_vlan_filter,
.enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
.reset_event = hclge_reset_event,
.get_reset_level = hclge_get_reset_level,
.set_default_reset_request = hclge_set_def_reset_request,
.get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
.set_channels = hclge_set_channels,
......
......@@ -965,6 +965,6 @@ int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
u16 state, u16 vlan_tag, u16 qos,
u16 vlan_proto);
enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
enum hnae3_reset_type hclge_get_reset_level(struct hnae3_ae_dev *ae_dev,
unsigned long *addr);
#endif
......@@ -1604,18 +1604,12 @@ static void hclgevf_reset_event(struct pci_dev *pdev,
hdev->last_reset_time = jiffies;
}
static enum hnae3_reset_type
hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
unsigned long *rst_type)
static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
enum hnae3_reset_type rst_type)
{
struct hclgevf_dev *hdev = ae_dev->priv;
enum hnae3_reset_type reset_type;
reset_type = hclgevf_get_reset_level(hdev, rst_type);
if (reset_type != HNAE3_NONE_RESET)
set_bit(reset_type, &hdev->default_reset_request);
return reset_type;
set_bit(rst_type, &hdev->default_reset_request);
}
static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev)
......
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