net/hinic: Add support for X86 Arch

driver inclusion
category: feature
bugzilla: 4472

-----------------------------------------------------------------------

Add support for X86 Arch.
Add the best default interrupt aggregation parameter and LRO parameter on
 x86 platform.
Signed-off-by: NChiqijun <chiqijun@huawei.com>
Reviewed-by: NZengweiliang <zengweiliang.zengweiliang@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

drivers/net/ethernet/huawei/Kconfig

@@ -5,7 +5,6 @@
 config NET_VENDOR_HUAWEI
 	bool "Huawei devices"
 	default y
-	depends on ARM64
 	---help---
 	  If you have a network (Ethernet) card belonging to this class, say Y.
 	  Note that the answer to this question doesn't directly affect the

drivers/net/ethernet/huawei/hinic/hinic_hwif.c

@@ -368,7 +368,12 @@ void hinic_free_db_addr(void *hwdev, void __iomem *db_base,
 	hwif = ((struct hinic_hwdev *)hwdev)->hwif;
 	idx = DB_IDX(db_base, hwif->db_base);
 
+#if defined(__aarch64__)
 	/* No need to unmap */
+#else
+	if (dwqe_base && hwif->chip_mode == CHIP_MODE_NORMAL)
+		io_mapping_unmap(dwqe_base);
+#endif
 
 	free_db_idx(hwif, idx);
 }
@@ -398,7 +403,12 @@ int hinic_alloc_db_addr(void *hwdev, void __iomem **db_base,
 
 	offset = ((u64)idx) << PAGE_SHIFT;
 
+#if defined(__aarch64__)
 	*dwqe_base = hwif->dwqe_mapping + offset;
+#else
+	*dwqe_base = io_mapping_map_wc(hwif->dwqe_mapping, offset,
+				       HINIC_DB_PAGE_SIZE);
+#endif
 
 	if (!(*dwqe_base)) {
 		hinic_free_db_addr(hwdev, *db_base, NULL);

drivers/net/ethernet/huawei/hinic/hinic_hwif.h

@@ -58,7 +58,11 @@ struct hinic_hwif {
 	u64				db_base_phy;
 	u8 __iomem			*db_base;
 
+#if defined(__aarch64__)
 	void __iomem			*dwqe_mapping;
+#else
+	struct io_mapping		*dwqe_mapping;
+#endif
 	struct hinic_free_db_area	free_db_area;
 
 	struct hinic_func_attr		attr;

drivers/net/ethernet/huawei/hinic/hinic_lld.c

@@ -114,7 +114,11 @@ struct hinic_pcidev {
 	u64 db_base_phy;
 	void __iomem *db_base;
 
+#if defined(__aarch64__)
 	void __iomem *dwqe_mapping;
+#else
+	struct io_mapping *dwqe_mapping;
+#endif
 	/* lock for attach/detach uld */
 	struct mutex pdev_mutex;
 	struct hinic_sriov_info sriov_info;
@@ -1874,9 +1878,15 @@ static int mapping_bar(struct pci_dev *pdev, struct hinic_pcidev *pci_adapter)
 
 	dwqe_addr = pci_adapter->db_base_phy + db_dwqe_size;
 
+#if defined(__aarch64__)
 	/* arm do not support call ioremap_wc() */
 	pci_adapter->dwqe_mapping = __ioremap(dwqe_addr, db_dwqe_size,
 					      __pgprot(PROT_DEVICE_nGnRnE));
+#else
+	pci_adapter->dwqe_mapping = io_mapping_create_wc(dwqe_addr,
+							 db_dwqe_size);
+
+#endif
 	if (!pci_adapter->dwqe_mapping) {
 		sdk_err(&pci_adapter->pcidev->dev, "Failed to io_mapping_create_wc\n");
 		goto mapping_dwqe_err;
@@ -1898,8 +1908,13 @@ static int mapping_bar(struct pci_dev *pdev, struct hinic_pcidev *pci_adapter)
 
 static void unmapping_bar(struct hinic_pcidev *pci_adapter)
 {
-	if (pci_adapter->chip_mode == CHIP_MODE_NORMAL)
+	if (pci_adapter->chip_mode == CHIP_MODE_NORMAL) {
+#if defined(__aarch64__)
 		iounmap(pci_adapter->dwqe_mapping);
+#else
+		io_mapping_free(pci_adapter->dwqe_mapping);
+#endif
+	}
 
 	iounmap(pci_adapter->db_base);
 	iounmap(pci_adapter->intr_reg_base);

drivers/net/ethernet/huawei/hinic/hinic_main.c

@@ -2908,7 +2908,13 @@ static void adaptive_configuration_init(struct hinic_nic_dev *nic_dev)
 
 	nic_dev->env_info.os = HINIC_OS_HUAWEI;
 
+#if defined(__aarch64__)
 	nic_dev->env_info.cpu = HINIC_CPU_ARM_GENERIC;
+#elif defined(__x86_64__)
+	nic_dev->env_info.cpu = HINIC_CPU_X86_GENERIC;
+#else
+	nic_dev->env_info.cpu = HINIC_CPU_UNKNOWN;
+#endif
 
 	nic_info(&nic_dev->pdev->dev,
 		 "Board type %u, OS type %u, CPU type %u\n",

drivers/net/ethernet/huawei/hinic/hinic_nic_cfg.h

@@ -56,6 +56,7 @@
 #define HINIC_LRO_RX_TIMER_DEFAULT_PG_10GE	10
 #define HINIC_LRO_RX_TIMER_DEFAULT_PG_100GE 8
 
+#if defined(__aarch64__)
 #define HINIC_LOWEST_LATENCY		1
 #define HINIC_RX_RATE_LOW		400000
 #define HINIC_RX_COAL_TIME_LOW		20
@@ -67,6 +68,19 @@
 #define HINIC_TX_RATE_THRESH		35000
 #define HINIC_RX_RATE_LOW_VM		400000
 #define HINIC_RX_PENDING_LIMIT_HIGH_VM	50
+#else
+#define HINIC_LOWEST_LATENCY		1
+#define HINIC_RX_RATE_LOW		400000
+#define HINIC_RX_COAL_TIME_LOW		16
+#define HINIC_RX_PENDING_LIMIT_LOW	2
+#define HINIC_RX_RATE_HIGH		1000000
+#define HINIC_RX_COAL_TIME_HIGH		225
+#define HINIC_RX_PENDING_LIMIT_HIGH	8
+#define HINIC_RX_RATE_THRESH		50000
+#define HINIC_TX_RATE_THRESH		50000
+#define HINIC_RX_RATE_LOW_VM		100000
+#define HINIC_RX_PENDING_LIMIT_HIGH_VM	87
+#endif
 
 enum hinic_board_type {
 	HINIC_BOARD_UNKNOWN        = 0,