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raspberrypi-kernel
提交 5d49f498 编写于 作者: A Abhijeet Kolekar 提交者： John W. Linville
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iwl3945: use iwl-io.h and delete iwl-3945-io.h 

The patch deletes iwl-3945-io.h and uses iwl-io.h functions.
Signed-off-by: NAbhijeet Kolekar <abhijeet.kolekar@intel.com>
Signed-off-by: NZhu Yi <yi.zhu@intel.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
上级 4a8a4322
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Showing with 197 addition and 601 deletion
drivers/net/wireless/iwlwifi/iwl-3945-io.h 已删除 100644 → 0
浏览文件 @ 4a8a4322
/******************************************************************************
*
* Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
*
* Portions of this file are derived from the ipw3945 project.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
* The full GNU General Public License is included in this distribution in the
* file called LICENSE.
*
* Contact Information:
* Intel Linux Wireless <ilw@linux.intel.com>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*
*****************************************************************************/
#ifndef __iwl3945_io_h__
#define __iwl3945_io_h__
#include <linux/io.h>
#include "iwl-debug.h"
/*
* IO, register, and NIC memory access functions
*
* NOTE on naming convention and macro usage for these
*
* A single _ prefix before a an access function means that no state
* check or debug information is printed when that function is called.
*
* A double __ prefix before an access function means that state is checked
* and the current line number is printed in addition to any other debug output.
*
* The non-prefixed name is the #define that maps the caller into a
* #define that provides the caller's __LINE__ to the double prefix version.
*
* If you wish to call the function without any debug or state checking,
* you should use the single _ prefix version (as is used by dependent IO
* routines, for example _iwl3945_read_direct32 calls the non-check version of
* _iwl3945_read32.)
*
* These declarations are *extremely* useful in quickly isolating code deltas
* which result in misconfiguration of the hardware I/O. In combination with
* git-bisect and the IO debug level you can quickly determine the specific
* commit which breaks the IO sequence to the hardware.
*
*/
#define _iwl3945_write32(priv, ofs, val) iowrite32((val), (priv)->hw_base + (ofs))
#ifdef CONFIG_IWL3945_DEBUG
static inline void __iwl3945_write32(const char *f, u32 l, struct iwl_priv *priv,
u32 ofs, u32 val)
{
IWL_DEBUG_IO("write32(0x%08X, 0x%08X) - %s %d\n", ofs, val, f, l);
_iwl3945_write32(priv, ofs, val);
}
#define iwl3945_write32(priv, ofs, val) \
__iwl3945_write32(__FILE__, __LINE__, priv, ofs, val)
#else
#define iwl3945_write32(priv, ofs, val) _iwl3945_write32(priv, ofs, val)
#endif
#define _iwl3945_read32(priv, ofs) ioread32((priv)->hw_base + (ofs))
#ifdef CONFIG_IWL3945_DEBUG
static inline u32 __iwl3945_read32(char *f, u32 l, struct iwl_priv *priv, u32 ofs)
{
IWL_DEBUG_IO("read_direct32(0x%08X) - %s %d\n", ofs, f, l);
return _iwl3945_read32(priv, ofs);
}
#define iwl3945_read32(priv, ofs)__iwl3945_read32(__FILE__, __LINE__, priv, ofs)
#else
#define iwl3945_read32(p, o) _iwl3945_read32(p, o)
#endif
static inline int _iwl3945_poll_bit(struct iwl_priv *priv, u32 addr,
u32 bits, u32 mask, int timeout)
{
int i = 0;
do {
if ((_iwl3945_read32(priv, addr) & mask) == (bits & mask))
return i;
udelay(10);
i += 10;
} while (i < timeout);
return -ETIMEDOUT;
}
#ifdef CONFIG_IWL3945_DEBUG
static inline int __iwl3945_poll_bit(const char *f, u32 l,
struct iwl_priv *priv, u32 addr,
u32 bits, u32 mask, int timeout)
{
int ret = _iwl3945_poll_bit(priv, addr, bits, mask, timeout);
IWL_DEBUG_IO("poll_bit(0x%08X, 0x%08X, 0x%08X) - %s- %s %d\n",
addr, bits, mask,
unlikely(ret == -ETIMEDOUT) ? "timeout" : "", f, l);
return ret;
}
#define iwl3945_poll_bit(priv, addr, bits, mask, timeout) \
__iwl3945_poll_bit(__FILE__, __LINE__, priv, addr, bits, mask, timeout)
#else
#define iwl3945_poll_bit(p, a, b, m, t) _iwl3945_poll_bit(p, a, b, m, t)
#endif
static inline void _iwl3945_set_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
_iwl3945_write32(priv, reg, _iwl3945_read32(priv, reg) | mask);
}
#ifdef CONFIG_IWL3945_DEBUG
static inline void __iwl3945_set_bit(const char *f, u32 l,
struct iwl_priv *priv, u32 reg, u32 mask)
{
u32 val = _iwl3945_read32(priv, reg) | mask;
IWL_DEBUG_IO("set_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
_iwl3945_write32(priv, reg, val);
}
#define iwl3945_set_bit(p, r, m) __iwl3945_set_bit(__FILE__, __LINE__, p, r, m)
#else
#define iwl3945_set_bit(p, r, m) _iwl3945_set_bit(p, r, m)
#endif
static inline void _iwl3945_clear_bit(struct iwl_priv *priv, u32 reg, u32 mask)
{
_iwl3945_write32(priv, reg, _iwl3945_read32(priv, reg) & ~mask);
}
#ifdef CONFIG_IWL3945_DEBUG
static inline void __iwl3945_clear_bit(const char *f, u32 l,
struct iwl_priv *priv, u32 reg, u32 mask)
{
u32 val = _iwl3945_read32(priv, reg) & ~mask;
IWL_DEBUG_IO("clear_bit(0x%08X, 0x%08X) = 0x%08X\n", reg, mask, val);
_iwl3945_write32(priv, reg, val);
}
#define iwl3945_clear_bit(p, r, m) __iwl3945_clear_bit(__FILE__, __LINE__, p, r, m)
#else
#define iwl3945_clear_bit(p, r, m) _iwl3945_clear_bit(p, r, m)
#endif
static inline int _iwl3945_grab_nic_access(struct iwl_priv *priv)
{
int ret;
#ifdef CONFIG_IWL3945_DEBUG
if (atomic_read(&priv->restrict_refcnt))
return 0;
#endif
/* this bit wakes up the NIC */
_iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
ret = _iwl3945_poll_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
(CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 50);
if (ret < 0) {
IWL_ERROR("MAC is in deep sleep!\n");
return -EIO;
}
#ifdef CONFIG_IWL3945_DEBUG
atomic_inc(&priv->restrict_refcnt);
#endif
return 0;
}
#ifdef CONFIG_IWL3945_DEBUG
static inline int __iwl3945_grab_nic_access(const char *f, u32 l,
struct iwl_priv *priv)
{
if (atomic_read(&priv->restrict_refcnt))
IWL_DEBUG_INFO("Grabbing access while already held at "
"line %d.\n", l);
IWL_DEBUG_IO("grabbing nic access - %s %d\n", f, l);
return _iwl3945_grab_nic_access(priv);
}
#define iwl3945_grab_nic_access(priv) \
__iwl3945_grab_nic_access(__FILE__, __LINE__, priv)
#else
#define iwl3945_grab_nic_access(priv) \
_iwl3945_grab_nic_access(priv)
#endif
static inline void _iwl3945_release_nic_access(struct iwl_priv *priv)
{
#ifdef CONFIG_IWL3945_DEBUG
if (atomic_dec_and_test(&priv->restrict_refcnt))
#endif
_iwl3945_clear_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
}
#ifdef CONFIG_IWL3945_DEBUG
static inline void __iwl3945_release_nic_access(const char *f, u32 l,
struct iwl_priv *priv)
{
if (atomic_read(&priv->restrict_refcnt) <= 0)
IWL_ERROR("Release unheld nic access at line %d.\n", l);
IWL_DEBUG_IO("releasing nic access - %s %d\n", f, l);
_iwl3945_release_nic_access(priv);
}
#define iwl3945_release_nic_access(priv) \
__iwl3945_release_nic_access(__FILE__, __LINE__, priv)
#else
#define iwl3945_release_nic_access(priv) \
_iwl3945_release_nic_access(priv)
#endif
static inline u32 _iwl3945_read_direct32(struct iwl_priv *priv, u32 reg)
{
return _iwl3945_read32(priv, reg);
}
#ifdef CONFIG_IWL3945_DEBUG
static inline u32 __iwl3945_read_direct32(const char *f, u32 l,
struct iwl_priv *priv, u32 reg)
{
u32 value = _iwl3945_read_direct32(priv, reg);
if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access not held from %s %d\n", f, l);
IWL_DEBUG_IO("read_direct32(0x%4X) = 0x%08x - %s %d \n", reg, value,
f, l);
return value;
}
#define iwl3945_read_direct32(priv, reg) \
__iwl3945_read_direct32(__FILE__, __LINE__, priv, reg)
#else
#define iwl3945_read_direct32 _iwl3945_read_direct32
#endif
static inline void _iwl3945_write_direct32(struct iwl_priv *priv,
u32 reg, u32 value)
{
_iwl3945_write32(priv, reg, value);
}
#ifdef CONFIG_IWL3945_DEBUG
static void __iwl3945_write_direct32(u32 line,
struct iwl_priv *priv, u32 reg, u32 value)
{
if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access not held from line %d\n", line);
_iwl3945_write_direct32(priv, reg, value);
}
#define iwl3945_write_direct32(priv, reg, value) \
__iwl3945_write_direct32(__LINE__, priv, reg, value)
#else
#define iwl3945_write_direct32 _iwl3945_write_direct32
#endif
static inline void iwl3945_write_reg_buf(struct iwl_priv *priv,
u32 reg, u32 len, u32 *values)
{
u32 count = sizeof(u32);
if ((priv != NULL) && (values != NULL)) {
for (; 0 < len; len -= count, reg += count, values++)
_iwl3945_write_direct32(priv, reg, *values);
}
}
static inline int _iwl3945_poll_direct_bit(struct iwl_priv *priv,
u32 addr, u32 mask, int timeout)
{
return _iwl3945_poll_bit(priv, addr, mask, mask, timeout);
}
#ifdef CONFIG_IWL3945_DEBUG
static inline int __iwl3945_poll_direct_bit(const char *f, u32 l,
struct iwl_priv *priv,
u32 addr, u32 mask, int timeout)
{
int ret = _iwl3945_poll_direct_bit(priv, addr, mask, timeout);
if (unlikely(ret == -ETIMEDOUT))
IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) - "
"timedout - %s %d\n", addr, mask, f, l);
else
IWL_DEBUG_IO("poll_direct_bit(0x%08X, 0x%08X) = 0x%08X "
"- %s %d\n", addr, mask, ret, f, l);
return ret;
}
#define iwl3945_poll_direct_bit(priv, addr, mask, timeout) \
__iwl3945_poll_direct_bit(__FILE__, __LINE__, priv, addr, mask, timeout)
#else
#define iwl3945_poll_direct_bit _iwl3945_poll_direct_bit
#endif
static inline u32 _iwl3945_read_prph(struct iwl_priv *priv, u32 reg)
{
_iwl3945_write_direct32(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
rmb();
return _iwl3945_read_direct32(priv, HBUS_TARG_PRPH_RDAT);
}
#ifdef CONFIG_IWL3945_DEBUG
static inline u32 __iwl3945_read_prph(u32 line, struct iwl_priv *priv, u32 reg)
{
if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access not held from line %d\n", line);
return _iwl3945_read_prph(priv, reg);
}
#define iwl3945_read_prph(priv, reg) \
__iwl3945_read_prph(__LINE__, priv, reg)
#else
#define iwl3945_read_prph _iwl3945_read_prph
#endif
static inline void _iwl3945_write_prph(struct iwl_priv *priv,
u32 addr, u32 val)
{
_iwl3945_write_direct32(priv, HBUS_TARG_PRPH_WADDR,
((addr & 0x0000FFFF) | (3 << 24)));
wmb();
_iwl3945_write_direct32(priv, HBUS_TARG_PRPH_WDAT, val);
}
#ifdef CONFIG_IWL3945_DEBUG
static inline void __iwl3945_write_prph(u32 line, struct iwl_priv *priv,
u32 addr, u32 val)
{
if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access from line %d\n", line);
_iwl3945_write_prph(priv, addr, val);
}
#define iwl3945_write_prph(priv, addr, val) \
__iwl3945_write_prph(__LINE__, priv, addr, val);
#else
#define iwl3945_write_prph _iwl3945_write_prph
#endif
#define _iwl3945_set_bits_prph(priv, reg, mask) \
_iwl3945_write_prph(priv, reg, (_iwl3945_read_prph(priv, reg) | mask))
#ifdef CONFIG_IWL3945_DEBUG
static inline void __iwl3945_set_bits_prph(u32 line, struct iwl_priv *priv,
u32 reg, u32 mask)
{
if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access not held from line %d\n", line);
_iwl3945_set_bits_prph(priv, reg, mask);
}
#define iwl3945_set_bits_prph(priv, reg, mask) \
__iwl3945_set_bits_prph(__LINE__, priv, reg, mask)
#else
#define iwl3945_set_bits_prph _iwl3945_set_bits_prph
#endif
#define _iwl3945_set_bits_mask_prph(priv, reg, bits, mask) \
_iwl3945_write_prph(priv, reg, ((_iwl3945_read_prph(priv, reg) & mask) | bits))
#ifdef CONFIG_IWL3945_DEBUG
static inline void __iwl3945_set_bits_mask_prph(u32 line,
struct iwl_priv *priv, u32 reg, u32 bits, u32 mask)
{
if (!atomic_read(&priv->restrict_refcnt))
IWL_ERROR("Nic access not held from line %d\n", line);
_iwl3945_set_bits_mask_prph(priv, reg, bits, mask);
}
#define iwl3945_set_bits_mask_prph(priv, reg, bits, mask) \
__iwl3945_set_bits_mask_prph(__LINE__, priv, reg, bits, mask)
#else
#define iwl3945_set_bits_mask_prph _iwl3945_set_bits_mask_prph
#endif
static inline void iwl3945_clear_bits_prph(struct iwl_priv
*priv, u32 reg, u32 mask)
{
u32 val = _iwl3945_read_prph(priv, reg);
_iwl3945_write_prph(priv, reg, (val & ~mask));
}
static inline u32 iwl3945_read_targ_mem(struct iwl_priv *priv, u32 addr)
{
iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, addr);
rmb();
return iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
}
static inline void iwl3945_write_targ_mem(struct iwl_priv *priv, u32 addr, u32 val)
{
iwl3945_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
wmb();
iwl3945_write_direct32(priv, HBUS_TARG_MEM_WDAT, val);
}
static inline void iwl3945_write_targ_mem_buf(struct iwl_priv *priv, u32 addr,
u32 len, u32 *values)
{
iwl3945_write_direct32(priv, HBUS_TARG_MEM_WADDR, addr);
wmb();
for (; 0 < len; len -= sizeof(u32), values++)
iwl3945_write_direct32(priv, HBUS_TARG_MEM_WDAT, *values);
}
#endif
drivers/net/wireless/iwlwifi/iwl-3945.c
浏览文件 @ 5d49f498
......@@ -156,26 +156,26 @@ void iwl3945_disable_events(struct iwl_priv *priv)
return;
}
ret = iwl3945_grab_nic_access(priv);
ret = iwl_grab_nic_access(priv);
if (ret) {
IWL_WARNING("Can not read from adapter at this time.\n");
return;
}
disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
iwl3945_release_nic_access(priv);
disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
iwl_release_nic_access(priv);
if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
disable_ptr);
ret = iwl3945_grab_nic_access(priv);
ret = iwl_grab_nic_access(priv);
for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
iwl3945_write_targ_mem(priv,
iwl_write_targ_mem(priv,
disable_ptr + (i * sizeof(u32)),
evt_disable[i]);
iwl3945_release_nic_access(priv);
iwl_release_nic_access(priv);
} else {
IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
......@@ -925,7 +925,7 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl3945_grab_nic_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
......@@ -937,23 +937,23 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
rc = pci_read_config_dword(priv->pci_dev,
PCI_POWER_SOURCE, &val);
if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
~APMG_PS_CTRL_MSK_PWR_SRC);
iwl3945_release_nic_access(priv);
iwl_release_nic_access(priv);
iwl3945_poll_bit(priv, CSR_GPIO_IN,
iwl_poll_bit(priv, CSR_GPIO_IN,
CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
CSR_GPIO_IN_BIT_AUX_POWER, 5000);
} else
iwl3945_release_nic_access(priv);
iwl_release_nic_access(priv);
} else {
iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
~APMG_PS_CTRL_MSK_PWR_SRC);
iwl3945_release_nic_access(priv);
iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
iwl_release_nic_access(priv);
iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
}
spin_unlock_irqrestore(&priv->lock, flags);
......@@ -967,18 +967,18 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl3945_grab_nic_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
iwl3945_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
iwl3945_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
priv->shared_phys +
offsetof(struct iwl3945_shared, rx_read_ptr[0]));
iwl3945_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
iwl3945_write_direct32(priv, FH39_RCSR_CONFIG(0),
iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
......@@ -989,9 +989,9 @@ static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
/* fake read to flush all prev I/O */
iwl3945_read_direct32(priv, FH39_RSSR_CTRL);
iwl_read_direct32(priv, FH39_RSSR_CTRL);
iwl3945_release_nic_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -1003,30 +1003,30 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl3945_grab_nic_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
/* bypass mode */
iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
/* RA 0 is active */
iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
/* all 6 fifo are active */
iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
iwl3945_write_direct32(priv, FH39_TSSR_CBB_BASE,
iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
priv->shared_phys);
iwl3945_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
......@@ -1035,7 +1035,7 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
iwl3945_release_nic_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -1087,12 +1087,12 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
iwl3945_power_init_handle(priv);
spin_lock_irqsave(&priv->lock, flags);
iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
rc = iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
rc = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
if (rc < 0) {
spin_unlock_irqrestore(&priv->lock, flags);
......@@ -1100,18 +1100,18 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
return rc;
}
rc = iwl3945_grab_nic_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
iwl3945_write_prph(priv, APMG_CLK_EN_REG,
iwl_write_prph(priv, APMG_CLK_EN_REG,
APMG_CLK_VAL_DMA_CLK_RQT |
APMG_CLK_VAL_BSM_CLK_RQT);
udelay(20);
iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
iwl3945_release_nic_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
/* Determine HW type */
......@@ -1127,17 +1127,17 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
IWL_DEBUG_INFO("RTP type \n");
else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
IWL_DEBUG_INFO("3945 RADIO-MB type\n");
iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
} else {
IWL_DEBUG_INFO("3945 RADIO-MM type\n");
iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
}
if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) {
IWL_DEBUG_INFO("SKU OP mode is mrc\n");
iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
} else
IWL_DEBUG_INFO("SKU OP mode is basic\n");
......@@ -1145,24 +1145,24 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) {
IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
priv->eeprom39.board_revision);
iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
} else {
IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
priv->eeprom39.board_revision);
iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
}
if (priv->eeprom39.almgor_m_version <= 1) {
iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
priv->eeprom39.almgor_m_version);
} else {
IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
priv->eeprom39.almgor_m_version);
iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
}
spin_unlock_irqrestore(&priv->lock, flags);
......@@ -1194,13 +1194,13 @@ int iwl3945_hw_nic_init(struct iwl_priv *priv)
iwl3945_rx_queue_update_write_ptr(priv, rxq);
*/
rc = iwl3945_grab_nic_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
iwl3945_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
iwl3945_release_nic_access(priv);
iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
......@@ -1233,24 +1233,24 @@ void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
if (iwl3945_grab_nic_access(priv)) {
if (iwl_grab_nic_access(priv)) {
spin_unlock_irqrestore(&priv->lock, flags);
iwl3945_hw_txq_ctx_free(priv);
return;
}
/* stop SCD */
iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
/* reset TFD queues */
for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
iwl3945_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
iwl3945_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1000);
}
iwl3945_release_nic_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
iwl3945_hw_txq_ctx_free(priv);
......@@ -1265,16 +1265,16 @@ int iwl3945_hw_nic_stop_master(struct iwl_priv *priv)
spin_lock_irqsave(&priv->lock, flags);
/* set stop master bit */
iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
reg_val = iwl_read32(priv, CSR_GP_CNTRL);
if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
(reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
IWL_DEBUG_INFO("Card in power save, master is already "
"stopped\n");
else {
rc = iwl3945_poll_direct_bit(priv, CSR_RESET,
rc = iwl_poll_direct_bit(priv, CSR_RESET,
CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
if (rc < 0) {
spin_unlock_irqrestore(&priv->lock, flags);
......@@ -1297,37 +1297,37 @@ int iwl3945_hw_nic_reset(struct iwl_priv *priv)
spin_lock_irqsave(&priv->lock, flags);
iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
iwl3945_poll_direct_bit(priv, CSR_GP_CNTRL,
iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
rc = iwl3945_grab_nic_access(priv);
rc = iwl_grab_nic_access(priv);
if (!rc) {
iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
iwl_write_prph(priv, APMG_CLK_CTRL_REG,
APMG_CLK_VAL_BSM_CLK_RQT);
udelay(10);
iwl3945_set_bit(priv, CSR_GP_CNTRL,
iwl_set_bit(priv, CSR_GP_CNTRL,
CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
0xFFFFFFFF);
/* enable DMA */
iwl3945_write_prph(priv, APMG_CLK_EN_REG,
iwl_write_prph(priv, APMG_CLK_EN_REG,
APMG_CLK_VAL_DMA_CLK_RQT |
APMG_CLK_VAL_BSM_CLK_RQT);
udelay(10);
iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_RESET_REQ);
udelay(5);
iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_RESET_REQ);
iwl3945_release_nic_access(priv);
iwl_release_nic_access(priv);
}
/* Clear the 'host command active' bit... */
......@@ -1358,7 +1358,7 @@ static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
int iwl3945_hw_get_temperature(struct iwl_priv *priv)
{
return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
return iwl_read32(priv, CSR_UCODE_DRV_GP2);
}
/**
......@@ -2290,19 +2290,19 @@ int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
rc = iwl3945_grab_nic_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
iwl3945_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
rc = iwl3945_poll_direct_bit(priv, FH39_RSSR_STATUS,
iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
if (rc < 0)
IWL_ERROR("Can't stop Rx DMA.\n");
iwl3945_release_nic_access(priv);
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......@@ -2319,24 +2319,24 @@ int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl3945_tx_queue *txq
shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
spin_lock_irqsave(&priv->lock, flags);
rc = iwl3945_grab_nic_access(priv);
rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
iwl3945_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
iwl3945_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
iwl3945_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
iwl3945_release_nic_access(priv);
iwl_release_nic_access(priv);
/* fake read to flush all prev. writes */
iwl3945_read32(priv, FH39_TSSR_CBB_BASE);
iwl_read32(priv, FH39_TSSR_CBB_BASE);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
......
drivers/net/wireless/iwlwifi/iwl-3945.h
浏览文件 @ 5d49f498
......@@ -397,6 +397,6 @@ extern const struct iwl_channel_info *iwl3945_get_channel_info(
extern int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate);
/* Requires full declaration of iwl_priv before including */
#include "iwl-3945-io.h"
#include "iwl-io.h"
#endif
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