提交 57527f8d 编写于 作者: S Sujith Manoharan 提交者: John W. Linville

ath9k_hw: Program filter coefficients correctly

2484 Mhz (Japan) usage requires filter coefficients to
be programmed in the CCK TX FIR registers. This is required
for AR9331, AR9485 and AR9462. Fix this and also remove
a few useless macros and a duplicate variable.
Signed-off-by: NSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
上级 f3684343
...@@ -35,12 +35,6 @@ ...@@ -35,12 +35,6 @@
*/ */
static void ar9003_hw_init_mode_regs(struct ath_hw *ah) static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
{ {
#define AR9462_BB_CTX_COEFJ(x) \
ar9462_##x##_baseband_core_txfir_coeff_japan_2484
#define AR9462_BBC_TXIFR_COEFFJ \
ar9462_2p0_baseband_core_txfir_coeff_japan_2484
if (AR_SREV_9330_11(ah)) { if (AR_SREV_9330_11(ah)) {
/* mac */ /* mac */
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
...@@ -70,6 +64,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -70,6 +64,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9331_modes_lowest_ob_db_tx_gain_1p1); ar9331_modes_lowest_ob_db_tx_gain_1p1);
/* Japan 2484 Mhz CCK */
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
/* additional clock settings */ /* additional clock settings */
if (ah->is_clk_25mhz) if (ah->is_clk_25mhz)
INIT_INI_ARRAY(&ah->iniAdditional, INIT_INI_ARRAY(&ah->iniAdditional,
...@@ -106,6 +104,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -106,6 +104,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9331_modes_lowest_ob_db_tx_gain_1p2); ar9331_modes_lowest_ob_db_tx_gain_1p2);
/* Japan 2484 Mhz CCK */
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
/* additional clock settings */ /* additional clock settings */
if (ah->is_clk_25mhz) if (ah->is_clk_25mhz)
INIT_INI_ARRAY(&ah->iniAdditional, INIT_INI_ARRAY(&ah->iniAdditional,
...@@ -180,6 +182,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -180,6 +182,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
INIT_INI_ARRAY(&ah->iniModesTxGain, INIT_INI_ARRAY(&ah->iniModesTxGain,
ar9485_modes_lowest_ob_db_tx_gain_1_1); ar9485_modes_lowest_ob_db_tx_gain_1_1);
/* Japan 2484 Mhz CCK */
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
/* Load PCIE SERDES settings from INI */ /* Load PCIE SERDES settings from INI */
/* Awake Setting */ /* Awake Setting */
...@@ -229,9 +235,7 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -229,9 +235,7 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9462_modes_fast_clock_2p0); ar9462_modes_fast_clock_2p0);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484, INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
AR9462_BB_CTX_COEFJ(2p0)); ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
} else if (AR_SREV_9550(ah)) { } else if (AR_SREV_9550(ah)) {
/* mac */ /* mac */
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
......
...@@ -784,7 +784,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, ...@@ -784,7 +784,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
if (chan->channel == 2484) if (chan->channel == 2484)
ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1); ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
......
...@@ -1060,4 +1060,6 @@ static const u32 ar9485_1_1_mac_core[][2] = { ...@@ -1060,4 +1060,6 @@ static const u32 ar9485_1_1_mac_core[][2] = {
{0x000083d0, 0x000301ff}, {0x000083d0, 0x000301ff},
}; };
#define ar9485_1_1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
#endif /* INITVALS_9485_H */ #endif /* INITVALS_9485_H */
...@@ -875,7 +875,6 @@ struct ath_hw { ...@@ -875,7 +875,6 @@ struct ath_hw {
struct ar5416IniArray iniModesTxGain; struct ar5416IniArray iniModesTxGain;
struct ar5416IniArray iniCckfirNormal; struct ar5416IniArray iniCckfirNormal;
struct ar5416IniArray iniCckfirJapan2484; struct ar5416IniArray iniCckfirJapan2484;
struct ar5416IniArray ini_japan2484;
struct ar5416IniArray iniModes_9271_ANI_reg; struct ar5416IniArray iniModes_9271_ANI_reg;
struct ar5416IniArray ini_radio_post_sys2ant; struct ar5416IniArray ini_radio_post_sys2ant;
......
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