提交 56b60b8b 编写于 作者: T Tomasz Figa 提交者: Russell King

ARM: 8265/1: dts: exynos4: Add nodes for L2 cache controller

This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: NTomasz Figa <t.figa@samsung.com>
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
上级 30ad527a
...@@ -81,6 +81,15 @@ ...@@ -81,6 +81,15 @@
reg = <0x10023CA0 0x20>; reg = <0x10023CA0 0x20>;
}; };
l2c: l2-cache-controller@10502000 {
compatible = "arm,pl310-cache";
reg = <0x10502000 0x1000>;
cache-unified;
cache-level = <2>;
arm,tag-latency = <2 2 1>;
arm,data-latency = <2 2 1>;
};
gic: interrupt-controller@10490000 { gic: interrupt-controller@10490000 {
cpu-offset = <0x8000>; cpu-offset = <0x8000>;
}; };
......
...@@ -54,6 +54,20 @@ ...@@ -54,6 +54,20 @@
reg = <0x10023CA0 0x20>; reg = <0x10023CA0 0x20>;
}; };
l2c: l2-cache-controller@10502000 {
compatible = "arm,pl310-cache";
reg = <0x10502000 0x1000>;
cache-unified;
cache-level = <2>;
arm,tag-latency = <2 2 1>;
arm,data-latency = <3 2 1>;
arm,double-linefill = <1>;
arm,double-linefill-incr = <0>;
arm,double-linefill-wrap = <1>;
arm,prefetch-drop = <1>;
arm,prefetch-offset = <7>;
};
clock: clock-controller@10030000 { clock: clock-controller@10030000 {
compatible = "samsung,exynos4412-clock"; compatible = "samsung,exynos4412-clock";
reg = <0x10030000 0x20000>; reg = <0x10030000 0x20000>;
......
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