staging: Add driver to support wanPMC-CxT1E1 card.

Obviously still needs serious attention, but it compiles.

Original author: Rick Dobbs

Add driver to support wanPMC-CxT1E1 card.

This card provides 1-4 ports of T1E1 in PMC form factor.

Note, Rick doesn't want his email showing up as the "From:" author, but
has given his blessing to have the code included in the kernel tree.
Signed-off-by: NBob Beers <bob.beers@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

drivers/staging/Kconfig

@@ -139,5 +139,7 @@ source "drivers/staging/dt3155/Kconfig"
 
 source "drivers/staging/crystalhd/Kconfig"
 
+source "drivers/staging/cxt1e1/Kconfig"
+
 endif # !STAGING_EXCLUDE_BUILD
 endif # STAGING

drivers/staging/Makefile

@@ -51,3 +51,4 @@ obj-$(CONFIG_PCMCIA_NETWAVE)	+= netwave/
 obj-$(CONFIG_FB_SM7XX)		+= sm7xx/
 obj-$(CONFIG_DT3155)		+= dt3155/
 obj-$(CONFIG_CRYSTALHD)		+= crystalhd/
+obj-$(CONFIG_CXT1E1)		+= cxt1e1/

drivers/staging/cxt1e1/Kconfig

+config CXT1E1
+	tristate "SBE wanPMC-C[421]E1T1 hardware support"
+	depends on HDLC && PCI
+	---help---
+      This driver supports the SBE wanPMC-CxT1E1 1, 2 and 4 port T3
+      channelized stream WAN adapter card which contains a HDLC/Transparent
+      mode controller.
+
+      If you want to compile this driver as a module
+      say M here and read <file:Documentation/modules.txt>.
+      The module will be called 'cxt1e1'.
+
+      If unsure, say N.
+
+config SBE_PMCC4_NCOMM
+	bool "SBE PMCC4 NCOMM support"
+	depends on CXT1E1
+	---help---
+      SBE supplies optional support for NCOMM products.
+
+      If you have purchased this optional support you must say Y or M
+      here to allow the driver to operate with the NCOMM product.

drivers/staging/cxt1e1/Makefile

+obj-$(CONFIG_CXT1E1)	+= cxt1e1.o
+
+EXTRA_CFLAGS += -DSBE_PMCC4_ENABLE
+EXTRA_CFLAGS += -DSBE_ISR_TASKLET
+EXTRA_CFLAGS += -DSBE_INCLUDE_SYMBOLS
+
+cxt1e1-objs += 	\
+  ossiRelease.o 	\
+  musycc.o 		\
+  pmcc4_drv.o 		\
+  comet.o 		\
+  linux.o 		\
+  functions.o 		\
+  hwprobe.o 		\
+  sbeproc.o 		\
+  pmc93x6_eeprom.o 	\
+  sbecrc.o 		\
+  comet_tables.o 	\
+  sbeid.o

drivers/staging/cxt1e1/comet.h

+/*
+ * $Id: comet.h,v 1.3 2005/09/28 00:10:07 rickd PMCC4_3_1B $
+ */
+
+#ifndef _INC_COMET_H_
+#define _INC_COMET_H_
+
+/*-----------------------------------------------------------------------------
+ * comet.h -
+ *
+ * Copyright (C) 2005  SBE, Inc.
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ * For further information, contact via email: support@sbei.com
+ * SBE, Inc.  San Ramon, California  U.S.A.
+ *-----------------------------------------------------------------------------
+ * RCS info:
+ * RCS revision: $Revision: 1.3 $
+ * Last changed on $Date: 2005/09/28 00:10:07 $
+ * Changed by $Author: rickd $
+ *-----------------------------------------------------------------------------
+ * $Log: comet.h,v $
+ * Revision 1.3  2005/09/28 00:10:07  rickd
+ * Add RCS header. Switch to structure usage.
+ *
+ * Revision 1.2  2005/04/28 23:43:03  rickd
+ * Add RCS tracking heading.
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+#if defined(__FreeBSD__) || defined (__NetBSD__)
+#include <sys/types.h>
+#else
+#include <linux/types.h>
+#endif
+
+
+#define VINT32  volatile u_int32_t
+
+struct s_comet_reg
+{
+    VINT32 gbl_cfg;      /* 00  Global Cfg */
+    VINT32 clkmon;       /* 01  Clk Monitor */
+    VINT32 rx_opt;       /* 02  RX Options */
+    VINT32 rx_line_cfg;  /* 03  RX Line Interface Cfg */
+    VINT32 tx_line_cfg;  /* 04  TX Line Interface Cfg */
+    VINT32 tx_frpass;    /* 05  TX Framing & Bypass Options */
+    VINT32 tx_time;      /* 06  TX Timing Options */
+    VINT32 intr_1;       /* 07  Intr Source #1 */
+    VINT32 intr_2;       /* 08  Intr Source #2 */
+    VINT32 intr_3;       /* 09  Intr Source #3 */
+    VINT32 mdiag;        /* 0A  Master Diagnostics */
+    VINT32 mtest;        /* 0B  Master Test */
+    VINT32 adiag;        /* 0C  Analog Diagnostics */
+    VINT32 rev_id;       /* 0D  Rev/Chip Id/Global PMON Update */
+#define pmon  rev_id
+    VINT32 reset;        /* 0E  Reset */
+    VINT32 prgd_phctl;   /* 0F  PRGD Positioning/Ctl & HDLC Ctl */
+    VINT32 cdrc_cfg;     /* 10  CDRC Cfg */
+    VINT32 cdrc_ien;     /* 11  CDRC Intr Enable */
+    VINT32 cdrc_ists;    /* 12  CDRC Intr Sts */
+    VINT32 cdrc_alos;    /* 13  CDRC Alternate Loss of Signal */
+
+    VINT32 rjat_ists;    /* 14  RJAT Intr Sts */
+    VINT32 rjat_n1clk;   /* 15  RJAT Reference Clk Divisor (N1) Ctl */
+    VINT32 rjat_n2clk;   /* 16  RJAT Output Clk Divisor (N2) Ctl */
+    VINT32 rjat_cfg;     /* 17  RJAT Cfg */
+
+    VINT32 tjat_ists;    /* 18  TJAT Intr Sts */
+    VINT32 tjat_n1clk;   /* 19  TJAT Reference Clk Divisor (N1) Ctl */
+    VINT32 tjat_n2clk;   /* 1A  TJAT Output Clk Divisor (N2) Ctl */
+    VINT32 tjat_cfg;     /* 1B  TJAT Cfg */
+
+    VINT32 rx_elst_cfg;      /* 1C  RX-ELST Cfg */
+    VINT32 rx_elst_ists;     /* 1D  RX-ELST Intr Sts */
+    VINT32 rx_elst_idle;     /* 1E  RX-ELST Idle Code */
+    VINT32 _rx_elst_res1f;   /* 1F     RX-ELST Reserved */
+
+    VINT32 tx_elst_cfg;      /* 20  TX-ELST Cfg */
+    VINT32 tx_elst_ists;     /* 21  TX-ELST Intr Sts */
+    VINT32 _tx_elst_res22;   /* 22     TX-ELST Reserved */
+    VINT32 _tx_elst_res23;   /* 23     TX-ELST Reserved */
+    VINT32 __res24;          /* 24     Reserved */
+    VINT32 __res25;          /* 25     Reserved */
+    VINT32 __res26;          /* 26     Reserved */
+    VINT32 __res27;          /* 27     Reserved */
+
+    VINT32 rxce1_ctl;        /* 28  RXCE RX Data Link 1 Ctl */
+    VINT32 rxce1_bits;       /* 29  RXCE RX Data Link 1 Bit Select */
+    VINT32 rxce2_ctl;        /* 2A  RXCE RX Data Link 2 Ctl */
+    VINT32 rxce2_bits;       /* 2B  RXCE RX Data Link 2 Bit Select */
+    VINT32 rxce3_ctl;        /* 2C  RXCE RX Data Link 3 Ctl */
+    VINT32 rxce3_bits;       /* 2D  RXCE RX Data Link 3 Bit Select */
+    VINT32 _rxce_res2E;      /* 2E     RXCE Reserved */
+    VINT32 _rxce_res2F;      /* 2F     RXCE Reserved */
+
+    VINT32 brif_cfg;         /* 30  BRIF RX Backplane Cfg */
+    VINT32 brif_fpcfg;       /* 31  BRIF RX Backplane Frame Pulse Cfg */
+    VINT32 brif_pfcfg;       /* 32  BRIF RX Backplane Parity/F-Bit Cfg */
+    VINT32 brif_tsoff;       /* 33  BRIF RX Backplane Time Slot Offset */
+    VINT32 brif_boff;        /* 34  BRIF RX Backplane Bit Offset */
+    VINT32 _brif_res35;      /* 35     BRIF RX Backplane Reserved */
+    VINT32 _brif_res36;      /* 36     BRIF RX Backplane Reserved */
+    VINT32 _brif_res37;      /* 37     BRIF RX Backplane Reserved */
+
+    VINT32 txci1_ctl;        /* 38  TXCI TX Data Link 1 Ctl */
+    VINT32 txci1_bits;       /* 39  TXCI TX Data Link 2 Bit Select */
+    VINT32 txci2_ctl;        /* 3A  TXCI TX Data Link 1 Ctl */
+    VINT32 txci2_bits;       /* 3B  TXCI TX Data Link 2 Bit Select */
+    VINT32 txci3_ctl;        /* 3C  TXCI TX Data Link 1 Ctl */
+    VINT32 txci3_bits;       /* 3D  TXCI TX Data Link 2 Bit Select */
+    VINT32 _txci_res3E;      /* 3E     TXCI Reserved */
+    VINT32 _txci_res3F;      /* 3F     TXCI Reserved */
+
+    VINT32 btif_cfg;         /* 40  BTIF TX Backplane Cfg */
+    VINT32 btif_fpcfg;       /* 41  BTIF TX Backplane Frame Pulse Cfg */
+    VINT32 btif_pcfgsts;     /* 42  BTIF TX Backplane Parity Cfg & Sts */
+    VINT32 btif_tsoff;       /* 43  BTIF TX Backplane Time Slot Offset */
+    VINT32 btif_boff;        /* 44  BTIF TX Backplane Bit Offset */
+    VINT32 _btif_res45;      /* 45     BTIF TX Backplane Reserved */
+    VINT32 _btif_res46;      /* 46     BTIF TX Backplane Reserved */
+    VINT32 _btif_res47;      /* 47     BTIF TX Backplane Reserved */
+    VINT32 t1_frmr_cfg;      /* 48  T1 FRMR Cfg */
+    VINT32 t1_frmr_ien;      /* 49  T1 FRMR Intr Enable */
+    VINT32 t1_frmr_ists;     /* 4A  T1 FRMR Intr Sts */
+    VINT32 __res_4B;         /* 4B     Reserved */
+    VINT32 ibcd_cfg;         /* 4C  IBCD Cfg */
+    VINT32 ibcd_ies;         /* 4D  IBCD Intr Enable/Sts */
+    VINT32 ibcd_act;         /* 4E  IBCD Activate Code */
+    VINT32 ibcd_deact;       /* 4F  IBCD Deactivate Code */
+
+    VINT32 sigx_cfg;         /* 50  SIGX Cfg/Change of Signaling State */
+    VINT32 sigx_acc_cos;     /* 51  SIGX uP Access Sts/Change of Signaling State */
+    VINT32 sigx_iac_cos;     /* 52  SIGX Channel Indirect
+                              * Addr/Ctl/Change of Signaling State */
+    VINT32 sigx_idb_cos;     /* 53  SIGX Channel Indirect Data
+                              * Buffer/Change of Signaling State */
+
+    VINT32 t1_xbas_cfg;      /* 54  T1 XBAS Cfg */
+    VINT32 t1_xbas_altx;     /* 55  T1 XBAS Alarm TX */
+    VINT32 t1_xibc_ctl;      /* 56  T1 XIBC Ctl */
+    VINT32 t1_xibc_lbcode;   /* 57  T1 XIBC Loopback Code */
+
+    VINT32 pmon_ies;         /* 58  PMON Intr Enable/Sts */
+    VINT32 pmon_fberr;       /* 59  PMON Framing Bit Err Cnt */
+    VINT32 pmon_feb_lsb;     /* 5A  PMON OFF/COFA/Far End Block Err Cnt (LSB) */
+    VINT32 pmon_feb_msb;     /* 5B  PMON OFF/COFA/Far End Block Err Cnt (MSB) */
+    VINT32 pmon_bed_lsb;     /* 5C  PMON Bit/Err/CRCE Cnt (LSB) */
+    VINT32 pmon_bed_msb;     /* 5D  PMON Bit/Err/CRCE Cnt (MSB) */
+    VINT32 pmon_lvc_lsb;     /* 5E  PMON LVC Cnt (LSB) */
+    VINT32 pmon_lvc_msb;     /* 5F  PMON LVC Cnt (MSB) */
+
+    VINT32 t1_almi_cfg;      /* 60  T1 ALMI Cfg */
+    VINT32 t1_almi_ien;      /* 61  T1 ALMI Intr Enable */
+    VINT32 t1_almi_ists;     /* 62  T1 ALMI Intr Sts */
+    VINT32 t1_almi_detsts;   /* 63  T1 ALMI Alarm Detection Sts */
+
+    VINT32 _t1_pdvd_res64;   /* 64     T1 PDVD Reserved */
+    VINT32 t1_pdvd_ies;      /* 65  T1 PDVD Intr Enable/Sts */
+    VINT32 _t1_xboc_res66;   /* 66     T1 XBOC Reserved */
+    VINT32 t1_xboc_code;     /* 67  T1 XBOC Code */
+    VINT32 _t1_xpde_res68;   /* 68     T1 XPDE Reserved */
+    VINT32 t1_xpde_ies;      /* 69  T1 XPDE Intr Enable/Sts */
+
+    VINT32 t1_rboc_ena;      /* 6A  T1 RBOC Enable */
+    VINT32 t1_rboc_sts;      /* 6B  T1 RBOC Code Sts */
+
+    VINT32 t1_tpsc_cfg;      /* 6C  TPSC Cfg */
+    VINT32 t1_tpsc_sts;      /* 6D  TPSC uP Access Sts */
+    VINT32 t1_tpsc_ciaddr;   /* 6E  TPSC Channel Indirect
+                                          * Addr/Ctl */
+    VINT32 t1_tpsc_cidata;   /* 6F  TPSC Channel Indirect Data
+                                          * Buffer */
+    VINT32 t1_rpsc_cfg;      /* 70  RPSC Cfg */
+    VINT32 t1_rpsc_sts;      /* 71  RPSC uP Access Sts */
+    VINT32 t1_rpsc_ciaddr;   /* 72  RPSC Channel Indirect
+                                          * Addr/Ctl */
+    VINT32 t1_rpsc_cidata;   /* 73  RPSC Channel Indirect Data
+                                          * Buffer */
+    VINT32 __res74;          /* 74     Reserved */
+    VINT32 __res75;          /* 75     Reserved */
+    VINT32 __res76;          /* 76     Reserved */
+    VINT32 __res77;          /* 77     Reserved */
+
+    VINT32 t1_aprm_cfg;      /* 78  T1 APRM Cfg/Ctl */
+    VINT32 t1_aprm_load;     /* 79  T1 APRM Manual Load */
+    VINT32 t1_aprm_ists;     /* 7A  T1 APRM Intr Sts */
+    VINT32 t1_aprm_1sec_2;   /* 7B  T1 APRM One Second Content Octet 2 */
+    VINT32 t1_aprm_1sec_3;   /* 7C  T1 APRM One Second Content Octet 3 */
+    VINT32 t1_aprm_1sec_4;   /* 7D  T1 APRM One Second Content Octet 4 */
+    VINT32 t1_aprm_1sec_5;   /* 7E  T1 APRM One Second Content MSB (Octect 5) */
+    VINT32 t1_aprm_1sec_6;   /* 7F  T1 APRM One Second Content MSB (Octect 6) */
+
+    VINT32 e1_tran_cfg;      /* 80  E1 TRAN Cfg */
+    VINT32 e1_tran_txalarm;  /* 81  E1 TRAN TX Alarm/Diagnostic Ctl */
+    VINT32 e1_tran_intctl;   /* 82  E1 TRAN International Ctl */
+    VINT32 e1_tran_extrab;   /* 83  E1 TRAN Extra Bits Ctl */
+    VINT32 e1_tran_ien;      /* 84  E1 TRAN Intr Enable */
+    VINT32 e1_tran_ists;     /* 85  E1 TRAN Intr Sts */
+    VINT32 e1_tran_nats;     /* 86  E1 TRAN National Bit Codeword
+                                          * Select */
+    VINT32 e1_tran_nat;      /* 87  E1 TRAN National Bit Codeword */
+    VINT32 __res88;          /* 88     Reserved */
+    VINT32 __res89;          /* 89     Reserved */
+    VINT32 __res8A;          /* 8A     Reserved */
+    VINT32 __res8B;          /* 8B     Reserved */
+
+    VINT32 _t1_frmr_res8C;   /* 8C     T1 FRMR Reserved */
+    VINT32 _t1_frmr_res8D;   /* 8D     T1 FRMR Reserved */
+    VINT32 __res8E;          /* 8E     Reserved */
+    VINT32 __res8F;          /* 8F     Reserved */
+
+    VINT32 e1_frmr_aopts;    /* 90  E1 FRMR Frame Alignment Options */
+    VINT32 e1_frmr_mopts;    /* 91  E1 FRMR Maintenance Mode Options */
+    VINT32 e1_frmr_ien;      /* 92  E1 FRMR Framing Sts Intr Enable */
+    VINT32 e1_frmr_mien;     /* 93  E1 FRMR Maintenance/Alarm Sts Intr Enable */
+    VINT32 e1_frmr_ists;     /* 94  E1 FRMR Framing Sts Intr Indication */
+    VINT32 e1_frmr_mists;    /* 95  E1 FRMR Maintenance/Alarm Sts Indication Enable */
+    VINT32 e1_frmr_sts;      /* 96  E1 FRMR Framing Sts */
+    VINT32 e1_frmr_masts;    /* 97  E1 FRMR Maintenance/Alarm Sts */
+    VINT32 e1_frmr_nat_bits; /* 98  E1 FRMR International/National Bits */
+    VINT32 e1_frmr_crc_lsb;  /* 99  E1 FRMR CRC Err Cnt - LSB */
+    VINT32 e1_frmr_crc_msb;  /* 9A  E1 FRMR CRC Err Cnt - MSB */
+    VINT32 e1_frmr_nat_ien;  /* 9B  E1 FRMR National Bit Codeword Intr Enables */
+    VINT32 e1_frmr_nat_ists; /* 9C  E1 FRMR National Bit Codeword Intr/Sts */
+    VINT32 e1_frmr_nat;      /* 9D  E1 FRMR National Bit Codewords */
+    VINT32 e1_frmr_fp_ien;   /* 9E  E1 FRMR Frame Pulse/Alarm Intr Enables */
+    VINT32 e1_frmr_fp_ists;  /* 9F  E1 FRMR Frame Pulse/Alarm Intr/Sts */
+
+    VINT32 __resA0;          /* A0     Reserved */
+    VINT32 __resA1;          /* A1     Reserved */
+    VINT32 __resA2;          /* A2     Reserved */
+    VINT32 __resA3;          /* A3     Reserved */
+    VINT32 __resA4;          /* A4     Reserved */
+    VINT32 __resA5;          /* A5     Reserved */
+    VINT32 __resA6;          /* A6     Reserved */
+    VINT32 __resA7;          /* A7     Reserved */
+
+    VINT32 tdpr1_cfg;        /* A8  TDPR #1 Cfg */
+    VINT32 tdpr1_utl;        /* A9  TDPR #1 Upper TX Threshold */
+    VINT32 tdpr1_ltl;        /* AA  TDPR #1 Lower TX Threshold */
+    VINT32 tdpr1_ien;        /* AB  TDPR #1 Intr Enable */
+    VINT32 tdpr1_ists;       /* AC  TDPR #1 Intr Sts/UDR Clear */
+    VINT32 tdpr1_data;       /* AD  TDPR #1 TX Data */
+    VINT32 __resAE;          /* AE     Reserved */
+    VINT32 __resAF;          /* AF     Reserved */
+    VINT32 tdpr2_cfg;        /* B0  TDPR #2 Cfg */
+    VINT32 tdpr2_utl;        /* B1  TDPR #2 Upper TX Threshold */
+    VINT32 tdpr2_ltl;        /* B2  TDPR #2 Lower TX Threshold */
+    VINT32 tdpr2_ien;        /* B3  TDPR #2 Intr Enable */
+    VINT32 tdpr2_ists;       /* B4  TDPR #2 Intr Sts/UDR Clear */
+    VINT32 tdpr2_data;       /* B5  TDPR #2 TX Data */
+    VINT32 __resB6;          /* B6     Reserved */
+    VINT32 __resB7;          /* B7     Reserved1 */
+    VINT32 tdpr3_cfg;        /* B8  TDPR #3 Cfg */
+    VINT32 tdpr3_utl;        /* B9  TDPR #3 Upper TX Threshold */
+    VINT32 tdpr3_ltl;        /* BA  TDPR #3 Lower TX Threshold */
+    VINT32 tdpr3_ien;        /* BB  TDPR #3 Intr Enable */
+    VINT32 tdpr3_ists;       /* BC  TDPR #3 Intr Sts/UDR Clear */
+    VINT32 tdpr3_data;       /* BD  TDPR #3 TX Data */
+    VINT32 __resBE;          /* BE     Reserved */
+    VINT32 __resBF;          /* BF     Reserved */
+
+    VINT32 rdlc1_cfg;        /* C0  RDLC #1 Cfg */
+    VINT32 rdlc1_intctl;     /* C1  RDLC #1 Intr Ctl */
+    VINT32 rdlc1_sts;        /* C2  RDLC #1 Sts */
+    VINT32 rdlc1_data;       /* C3  RDLC #1 Data */
+    VINT32 rdlc1_paddr;      /* C4  RDLC #1 Primary Addr Match */
+    VINT32 rdlc1_saddr;      /* C5  RDLC #1 Secondary Addr Match */
+    VINT32 __resC6;          /* C6     Reserved */
+    VINT32 __resC7;          /* C7     Reserved */
+    VINT32 rdlc2_cfg;        /* C8  RDLC #2 Cfg */
+    VINT32 rdlc2_intctl;     /* C9  RDLC #2 Intr Ctl */
+    VINT32 rdlc2_sts;        /* CA  RDLC #2 Sts */
+    VINT32 rdlc2_data;       /* CB  RDLC #2 Data */
+    VINT32 rdlc2_paddr;      /* CC  RDLC #2 Primary Addr Match */
+    VINT32 rdlc2_saddr;      /* CD  RDLC #2 Secondary Addr Match */
+    VINT32 __resCE;          /* CE     Reserved */
+    VINT32 __resCF;          /* CF     Reserved */
+    VINT32 rdlc3_cfg;        /* D0  RDLC #3 Cfg */
+    VINT32 rdlc3_intctl;     /* D1  RDLC #3 Intr Ctl */
+    VINT32 rdlc3_sts;        /* D2  RDLC #3 Sts */
+    VINT32 rdlc3_data;       /* D3  RDLC #3 Data */
+    VINT32 rdlc3_paddr;      /* D4  RDLC #3 Primary Addr Match */
+    VINT32 rdlc3_saddr;      /* D5  RDLC #3 Secondary Addr Match */
+
+    VINT32 csu_cfg;          /* D6  CSU Cfg */
+    VINT32 _csu_resD7;       /* D7     CSU Reserved */
+
+    VINT32 rlps_idata3;      /* D8  RLPS Indirect Data, 24-31 */
+    VINT32 rlps_idata2;      /* D9  RLPS Indirect Data, 16-23 */
+    VINT32 rlps_idata1;      /* DA  RLPS Indirect Data, 8-15 */
+    VINT32 rlps_idata0;      /* DB  RLPS Indirect Data, 0-7 */
+    VINT32 rlps_eqvr;        /* DC  RLPS Equalizer Voltage Reference
+                              *    (E1 missing) */
+    VINT32 _rlps_resDD;      /* DD     RLPS Reserved */
+    VINT32 _rlps_resDE;      /* DE     RLPS Reserved */
+    VINT32 _rlps_resDF;      /* DF     RLPS Reserved */
+
+    VINT32 prgd_ctl;         /* E0  PRGD Ctl */
+    VINT32 prgd_ies;         /* E1  PRGD Intr Enable/Sts */
+    VINT32 prgd_shift_len;   /* E2  PRGD Shift Length */
+    VINT32 prgd_tap;         /* E3  PRGD Tap */
+    VINT32 prgd_errin;       /* E4  PRGD Err Insertion */
+    VINT32 _prgd_resE5;      /* E5     PRGD Reserved */
+    VINT32 _prgd_resE6;      /* E6     PRGD Reserved */
+    VINT32 _prgd_resE7;      /* E7     PRGD Reserved */
+    VINT32 prgd_patin1;      /* E8  PRGD Pattern Insertion #1 */
+    VINT32 prgd_patin2;      /* E9  PRGD Pattern Insertion #2 */
+    VINT32 prgd_patin3;      /* EA  PRGD Pattern Insertion #3 */
+    VINT32 prgd_patin4;      /* EB  PRGD Pattern Insertion #4 */
+    VINT32 prgd_patdet1;     /* EC  PRGD Pattern Detector #1 */
+    VINT32 prgd_patdet2;     /* ED  PRGD Pattern Detector #2 */
+    VINT32 prgd_patdet3;     /* EE  PRGD Pattern Detector #3 */
+    VINT32 prgd_patdet4;     /* EF  PRGD Pattern Detector #4 */
+
+    VINT32 xlpg_cfg;         /* F0  XLPG Line Driver Cfg */
+    VINT32 xlpg_ctlsts;      /* F1  XLPG Ctl/Sts */
+    VINT32 xlpg_pwave_addr;  /* F2  XLPG Pulse Waveform Storage Write Addr */
+    VINT32 xlpg_pwave_data;  /* F3  XLPG Pulse Waveform Storage Data */
+    VINT32 xlpg_atest_pctl;  /* F4  XLPG Analog Test Positive Ctl */
+    VINT32 xlpg_atest_nctl;  /* F5  XLPG Analog Test Negative Ctl */
+    VINT32 xlpg_fdata_sel;   /* F6  XLPG Fuse Data Select */
+    VINT32 _xlpg_resF7;      /* F7     XLPG Reserved */
+
+    VINT32 rlps_cfgsts;      /* F8  RLPS Cfg & Sts */
+    VINT32 rlps_alos_thresh; /* F9  RLPS ALOS Detection/Clearance Threshold */
+    VINT32 rlps_alos_dper;   /* FA  RLPS ALOS Detection Period */
+    VINT32 rlps_alos_cper;   /* FB  RLPS ALOS Clearance Period */
+    VINT32 rlps_eq_iaddr;    /* FC  RLPS Equalization Indirect Addr */
+    VINT32 rlps_eq_rwsel;    /* FD  RLPS Equalization Read/WriteB Select */
+    VINT32 rlps_eq_ctlsts;   /* FE  RLPS Equalizer Loop Sts & Ctl */
+    VINT32 rlps_eq_cfg;      /* FF  RLPS Equalizer Cfg */
+};
+
+typedef struct s_comet_reg comet_t;
+
+/* 00AH: MDIAG Register bit definitions */
+#define COMET_MDIAG_ID5        0x40
+#define COMET_MDIAG_LBMASK     0x3F
+#define COMET_MDIAG_PAYLB      0x20
+#define COMET_MDIAG_LINELB     0x10
+#define COMET_MDIAG_RAIS       0x08
+#define COMET_MDIAG_DDLB       0x04
+#define COMET_MDIAG_TXMFP      0x02
+#define COMET_MDIAG_TXLOS      0x01
+#define COMET_MDIAG_LBOFF      0x00
+
+#undef VINT32
+
+#ifdef __KERNEL__
+extern void
+init_comet (void *, comet_t *, u_int32_t, int, u_int8_t);
+#endif
+
+#endif                          /* _INC_COMET_H_ */

drivers/staging/cxt1e1/comet_tables.h

+/*
+ * $Id: comet_tables.h,v 1.5 2006/01/02 22:37:31 rickd PMCC4_3_1B $
+ */
+
+#ifndef _INC_COMET_TBLS_H_
+#define _INC_COMET_TBLS_H_
+
+/*-----------------------------------------------------------------------------
+ * comet_tables.h - Waveform Tables for the PM4351 'COMET'
+ *
+ * Copyright (C) 2005  SBE, Inc.
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ * For further information, contact via email: support@sbei.com
+ * SBE, Inc.  San Ramon, California  U.S.A.
+ *-----------------------------------------------------------------------------
+ * RCS info:
+ * RCS revision: $Revision: 1.5 $
+ * Last changed on $Date: 2006/01/02 22:37:31 $
+ * Changed by $Author: rickd $
+ *-----------------------------------------------------------------------------
+ * $Log: comet_tables.h,v $
+ * Revision 1.5  2006/01/02 22:37:31  rickd
+ * Double indexed arrays need sizings to avoid CC errors under
+ * gcc 4.0.0
+ *
+ * Revision 1.4  2005/10/17 23:55:28  rickd
+ * The 75 Ohm transmit waveform is not supported on PMCC4.
+ *
+ * Revision 1.3  2005/09/28 00:10:08  rickd
+ * Add GNU License info. Structures moved to -C- file.
+ *
+ * Revision 1.2  2005/04/28 23:43:04  rickd
+ * Add RCS tracking heading.
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+/*****************************************************************************
+*
+*  Array names:
+*
+*       TWVLongHaul0DB
+*       TWVLongHaul7_5DB
+*       TWVLongHaul15DB
+*       TWVLongHaul22_5DB
+*       TWVShortHaul0
+*       TWVShortHaul1
+*       TWVShortHaul2
+*       TWVShortHaul3
+*       TWVShortHaul4
+*       TWVShortHaul5
+*       TWV_E1_120Ohm
+*       TWV_E1_75Ohm    <not supported>
+*       T1_Equalizer
+*       E1_Equalizer
+*
+*****************************************************************************/
+
+extern u_int8_t TWVLongHaul0DB[25][5];      /* T1 Long Haul 0 DB */
+extern u_int8_t TWVLongHaul7_5DB[25][5];    /* T1 Long Haul 7.5 DB */
+extern u_int8_t TWVLongHaul15DB[25][5];     /* T1 Long Haul 15 DB */
+extern u_int8_t TWVLongHaul22_5DB[25][5];   /* T1 Long Haul 22.5 DB */
+extern u_int8_t TWVShortHaul0[25][5];       /* T1 Short Haul 0-110 ft */
+extern u_int8_t TWVShortHaul1[25][5];       /* T1 Short Haul 110-220 ft */
+extern u_int8_t TWVShortHaul2[25][5];       /* T1 Short Haul 220-330 ft */
+extern u_int8_t TWVShortHaul3[25][5];       /* T1 Short Haul 330-440 ft */
+extern u_int8_t TWVShortHaul4[25][5];       /* T1 Short Haul 440-550 ft */
+extern u_int8_t TWVShortHaul5[25][5];       /* T1 Short Haul 550-660 ft */
+extern u_int8_t TWV_E1_75Ohm[25][5];        /* E1 75 Ohm */
+extern u_int8_t TWV_E1_120Ohm[25][5];       /* E1 120 Ohm */
+extern u_int32_t T1_Equalizer[256];    /* T1 Receiver Equalizer */
+extern u_int32_t E1_Equalizer[256];    /* E1 Receiver Equalizer */
+
+#endif                          /* _INC_COMET_TBLS_H_ */

drivers/staging/cxt1e1/functions.c

+/* Copyright (C) 2003-2005  SBE, Inc.
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ */
+
+#include <linux/slab.h>
+#include <asm/io.h>
+#include <asm/byteorder.h>
+#include <linux/netdevice.h>
+#include <linux/delay.h>
+#include <linux/hdlc.h>
+#include "pmcc4_sysdep.h"
+#include "sbecom_inline_linux.h"
+#include "libsbew.h"
+#include "pmcc4.h"
+
+
+#ifdef SBE_INCLUDE_SYMBOLS
+#define STATIC
+#else
+#define STATIC  static
+#endif
+
+#if defined(CONFIG_SBE_HDLC_V7) || defined(CONFIG_SBE_WAN256T3_HDLC_V7) || \
+    defined(CONFIG_SBE_HDLC_V7_MODULE) || defined(CONFIG_SBE_WAN256T3_HDLC_V7_MODULE)
+#define _v7_hdlc_  1
+#else
+#define _v7_hdlc_  0
+#endif
+
+#if _v7_hdlc_
+#define V7(x) (x ## _v7)
+extern int  hdlc_netif_rx_v7 (hdlc_device *, struct sk_buff *);
+extern int  register_hdlc_device_v7 (hdlc_device *);
+extern int  unregister_hdlc_device_v7 (hdlc_device *);
+
+#else
+#define V7(x) x
+#endif
+
+
+#ifndef USE_MAX_INT_DELAY
+static int  dummy = 0;
+
+#endif
+
+extern int  log_level;
+extern int  drvr_state;
+
+
+#if 1
+u_int32_t
+pci_read_32 (u_int32_t *p)
+{
+#ifdef FLOW_DEBUG
+    u_int32_t   v;
+
+    FLUSH_PCI_READ ();
+    v = le32_to_cpu (*p);
+    if (log_level >= LOG_DEBUG)
+        printk ("pci_read : %x = %x\n", (u_int32_t) p, v);
+    return v;
+#else
+    FLUSH_PCI_READ ();              /* */
+    return le32_to_cpu (*p);
+#endif
+}
+
+void
+pci_write_32 (u_int32_t *p, u_int32_t v)
+{
+#ifdef FLOW_DEBUG
+    if (log_level >= LOG_DEBUG)
+        printk ("pci_write: %x = %x\n", (u_int32_t) p, v);
+#endif
+    *p = cpu_to_le32 (v);
+    FLUSH_PCI_WRITE ();             /* This routine is called from routines
+                                     * which do multiple register writes
+                                     * which themselves need flushing between
+                                     * writes in order to guarantee write
+                                     * ordering.  It is less code-cumbersome
+                                     * to flush here-in then to investigate
+                                     * and code the many other register
+                                     * writing routines. */
+}
+#endif
+
+
+void
+pci_flush_write (ci_t * ci)
+{
+    volatile u_int32_t v;
+
+    /* issue a PCI read to flush PCI write thru bridge */
+    v = *(u_int32_t *) &ci->reg->glcd;  /* any address would do */
+
+    /*
+     * return nothing, this just reads PCI bridge interface to flush
+     * previously written data
+     */
+}
+
+
+STATIC void
+watchdog_func (unsigned long arg)
+{
+    struct watchdog *wd = (void *) arg;
+
+    if (drvr_state != SBE_DRVR_AVAILABLE)
+    {
+        if (log_level >= LOG_MONITOR)
+            printk (KERN_WARNING "watchdog_func: drvr not available (%x)\n", drvr_state);
+        return;
+    }
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
+    /* Initialize the tq entry only the first time */
+    if (wd->init_tq)
+    {
+        wd->init_tq = 0;
+        wd->tq.routine = wd->func;
+        wd->tq.sync = 0;
+        wd->tq.data = wd->softc;
+    }
+    schedule_task (&wd->tq);
+#else
+    schedule_work (&wd->work);
+#endif
+    mod_timer (&wd->h, jiffies + wd->ticks);
+}
+
+int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *), void *c, int usec)
+{
+    wdp->func = f;
+    wdp->softc = c;
+    wdp->ticks = (HZ) * (usec / 1000) / 1000;
+    INIT_WORK(&wdp->work, (void *)f);
+    init_timer (&wdp->h);
+    {
+        ci_t       *ci = (ci_t *) c;
+
+        wdp->h.data = (unsigned long) &ci->wd;
+    }
+    wdp->h.function = watchdog_func;
+    return 0;
+}
+
+void
+OS_uwait (int usec, char *description)
+{
+    int         tmp;
+
+    if (usec >= 1000)
+    {
+        mdelay (usec / 1000);
+        /* now delay residual */
+        tmp = (usec / 1000) * 1000; /* round */
+        tmp = usec - tmp;           /* residual */
+        if (tmp)
+        {                           /* wait on residual */
+            udelay (tmp);
+        }
+    } else
+    {
+        udelay (usec);
+    }
+}
+
+/* dummy short delay routine called as a subroutine so that compiler
+ * does not optimize/remove its intent (a short delay)
+ */
+
+void
+OS_uwait_dummy (void)
+{
+#ifndef USE_MAX_INT_DELAY
+    dummy++;
+#else
+    udelay (1);
+#endif
+}
+
+
+void
+OS_sem_init (void *sem, int state)
+{
+    switch (state)
+    {
+        case SEM_TAKEN:
+        init_MUTEX_LOCKED ((struct semaphore *) sem);
+        break;
+    case SEM_AVAILABLE:
+        init_MUTEX ((struct semaphore *) sem);
+        break;
+    default:                        /* otherwise, set sem.count to state's
+                                     * value */
+        sema_init (sem, state);
+        break;
+    }
+}
+
+
+int
+sd_line_is_ok (void *user)
+{
+    struct net_device *ndev = (struct net_device *) user;
+
+    return (netif_carrier_ok (ndev));
+}
+
+void
+sd_line_is_up (void *user)
+{
+    struct net_device *ndev = (struct net_device *) user;
+
+    netif_carrier_on (ndev);
+    return;
+}
+
+void
+sd_line_is_down (void *user)
+{
+    struct net_device *ndev = (struct net_device *) user;
+
+    netif_carrier_off (ndev);
+    return;
+}
+
+void
+sd_disable_xmit (void *user)
+{
+    struct net_device *dev = (struct net_device *) user;
+
+    netif_stop_queue (dev);
+    return;
+}
+
+void
+sd_enable_xmit (void *user)
+{
+    struct net_device *dev = (struct net_device *) user;
+
+    netif_wake_queue (dev);
+    return;
+}
+
+int
+sd_queue_stopped (void *user)
+{
+    struct net_device *ndev = (struct net_device *) user;
+
+    return (netif_queue_stopped (ndev));
+}
+
+void sd_recv_consume(void *token, size_t len, void *user)
+{
+    struct net_device *ndev = user;
+    struct sk_buff *skb = token;
+
+    skb->dev = ndev;
+    skb_put (skb, len);
+    skb->protocol = hdlc_type_trans(skb, ndev);
+    netif_rx(skb);
+}
+
+
+/**
+ ** Read some reserved location w/in the COMET chip as a usable
+ ** VMETRO trigger point or other trace marking event.
+ **/
+
+#include "comet.h"
+
+extern ci_t *CI;                /* dummy pointer to board ZERO's data */
+void
+VMETRO_TRACE (void *x)
+{
+    u_int32_t   y = (u_int32_t) x;
+
+    pci_write_32 ((u_int32_t *) &CI->cpldbase->leds, y);
+}
+
+
+void
+VMETRO_TRIGGER (ci_t * ci, int x)
+{
+    comet_t    *comet;
+    volatile u_int32_t data;
+
+    comet = ci->port[0].cometbase;  /* default to COMET # 0 */
+
+    switch (x)
+    {
+    default:
+    case 0:
+        data = pci_read_32 ((u_int32_t *) &comet->__res24);     /* 0x90 */
+        break;
+    case 1:
+        data = pci_read_32 ((u_int32_t *) &comet->__res25);     /* 0x94 */
+        break;
+    case 2:
+        data = pci_read_32 ((u_int32_t *) &comet->__res26);     /* 0x98 */
+        break;
+    case 3:
+        data = pci_read_32 ((u_int32_t *) &comet->__res27);     /* 0x9C */
+        break;
+    case 4:
+        data = pci_read_32 ((u_int32_t *) &comet->__res88);     /* 0x220 */
+        break;
+    case 5:
+        data = pci_read_32 ((u_int32_t *) &comet->__res89);     /* 0x224 */
+        break;
+    case 6:
+        data = pci_read_32 ((u_int32_t *) &comet->__res8A);     /* 0x228 */
+        break;
+    case 7:
+        data = pci_read_32 ((u_int32_t *) &comet->__res8B);     /* 0x22C */
+        break;
+    case 8:
+        data = pci_read_32 ((u_int32_t *) &comet->__resA0);     /* 0x280 */
+        break;
+    case 9:
+        data = pci_read_32 ((u_int32_t *) &comet->__resA1);     /* 0x284 */
+        break;
+    case 10:
+        data = pci_read_32 ((u_int32_t *) &comet->__resA2);     /* 0x288 */
+        break;
+    case 11:
+        data = pci_read_32 ((u_int32_t *) &comet->__resA3);     /* 0x28C */
+        break;
+    case 12:
+        data = pci_read_32 ((u_int32_t *) &comet->__resA4);     /* 0x290 */
+        break;
+    case 13:
+        data = pci_read_32 ((u_int32_t *) &comet->__resA5);     /* 0x294 */
+        break;
+    case 14:
+        data = pci_read_32 ((u_int32_t *) &comet->__resA6);     /* 0x298 */
+        break;
+    case 15:
+        data = pci_read_32 ((u_int32_t *) &comet->__resA7);     /* 0x29C */
+        break;
+    case 16:
+        data = pci_read_32 ((u_int32_t *) &comet->__res74);     /* 0x1D0 */
+        break;
+    case 17:
+        data = pci_read_32 ((u_int32_t *) &comet->__res75);     /* 0x1D4 */
+        break;
+    case 18:
+        data = pci_read_32 ((u_int32_t *) &comet->__res76);     /* 0x1D8 */
+        break;
+    case 19:
+        data = pci_read_32 ((u_int32_t *) &comet->__res77);     /* 0x1DC */
+        break;
+    }
+}
+
+
+/***  End-of-File  ***/

drivers/staging/cxt1e1/hwprobe.c

+/* Copyright (C) 2007  One Stop Systems
+ * Copyright (C) 2003-2005  SBE, Inc.
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ */
+
+#include <linux/netdevice.h>
+#include <linux/hdlc.h>
+#include <linux/if_arp.h>
+#include <asm/uaccess.h>
+#include <linux/rtnetlink.h>
+#include <linux/pci.h>
+#include "pmcc4_sysdep.h"
+#include "sbecom_inline_linux.h"
+#include "libsbew.h"
+#include "pmcc4_private.h"
+#include "pmcc4.h"
+#include "pmcc4_ioctls.h"
+#include "pmc93x6_eeprom.h"
+#ifdef CONFIG_PROC_FS
+#include "sbeproc.h"
+#endif
+
+#ifdef SBE_INCLUDE_SYMBOLS
+#define STATIC
+#else
+#define STATIC  static
+#endif
+
+extern int  log_level;
+extern int  error_flag;
+extern int  drvr_state;
+
+/* forward references */
+void        c4_stopwd (ci_t *);
+struct net_device * __init c4_add_dev (hdw_info_t *, int, unsigned long, unsigned long, int, int);
+
+
+struct s_hdw_info hdw_info[MAX_BOARDS];
+
+
+void        __init
+show_two (hdw_info_t * hi, int brdno)
+{
+    ci_t       *ci;
+    struct pci_dev *pdev;
+    char       *bid;
+    char       *bp, banner[80];
+    char        sn[6];
+
+    bp = banner;
+    memset (banner, 0, 80);         /* clear print buffer */
+
+    ci = (ci_t *)(netdev_priv(hi->ndev));
+    bid = sbeid_get_bdname (ci);
+    switch (hi->promfmt)
+    {
+    case PROM_FORMAT_TYPE1:
+        memcpy (sn, (FLD_TYPE1 *) (hi->mfg_info.pft1.Serial), 6);
+        break;
+    case PROM_FORMAT_TYPE2:
+        memcpy (sn, (FLD_TYPE2 *) (hi->mfg_info.pft2.Serial), 6);
+        break;
+    default:
+        memset (sn, 0, 6);
+        break;
+    }
+
+    sprintf (banner, "%s: %s  S/N %06X, MUSYCC Rev %02X",
+             hi->devname, bid,
+             ((sn[3] << 16) & 0xff0000) |
+              ((sn[4] << 8) & 0x00ff00) |
+              (sn[5] & 0x0000ff),
+             (u_int8_t) hi->revid[0]);
+
+    printk ("%s\n", banner);
+
+    pdev = hi->pdev[0];
+    printk ("%s: %s at v/p=%lx/%lx (%02x:%02x.%x) irq %d\n",
+            hi->devname, "MUSYCC",
+            (unsigned long) hi->addr_mapped[0], hi->addr[0],
+            hi->pci_busno, (u_int8_t) PCI_SLOT (pdev->devfn),
+            (u_int8_t) PCI_FUNC (pdev->devfn), pdev->irq);
+
+    pdev = hi->pdev[1];
+    printk ("%s: %s at v/p=%lx/%lx (%02x:%02x.%x) irq %d\n",
+            hi->devname, "EBUS  ",
+            (unsigned long) hi->addr_mapped[1], hi->addr[1],
+            hi->pci_busno, (u_int8_t) PCI_SLOT (pdev->devfn),
+            (u_int8_t) PCI_FUNC (pdev->devfn), pdev->irq);
+}
+
+
+void        __init
+hdw_sn_get (hdw_info_t * hi, int brdno)
+{
+    /* obtain hardware EEPROM information */
+    long        addr;
+
+    addr = (long) hi->addr_mapped[1] + EEPROM_OFFSET;
+
+    /* read EEPROM with largest known format size... */
+    pmc_eeprom_read_buffer (addr, 0, (char *) hi->mfg_info.data, sizeof (FLD_TYPE2));
+
+#if 0
+    {
+        unsigned char *ucp = (unsigned char *) &hi->mfg_info.data;
+
+        printk ("eeprom[00]:  %02x %02x %02x %02x  %02x %02x %02x %02x\n",
+                *(ucp + 0), *(ucp + 1), *(ucp + 2), *(ucp + 3), *(ucp + 4), *(ucp + 5), *(ucp + 6), *(ucp + 7));
+        printk ("eeprom[08]:  %02x %02x %02x %02x  %02x %02x %02x %02x\n",
+                *(ucp + 8), *(ucp + 9), *(ucp + 10), *(ucp + 11), *(ucp + 12), *(ucp + 13), *(ucp + 14), *(ucp + 15));
+        printk ("eeprom[16]:  %02x %02x %02x %02x  %02x %02x %02x %02x\n",
+                *(ucp + 16), *(ucp + 17), *(ucp + 18), *(ucp + 19), *(ucp + 20), *(ucp + 21), *(ucp + 22), *(ucp + 23));
+        printk ("eeprom[24]:  %02x %02x %02x %02x  %02x %02x %02x %02x\n",
+                *(ucp + 24), *(ucp + 25), *(ucp + 26), *(ucp + 27), *(ucp + 28), *(ucp + 29), *(ucp + 30), *(ucp + 31));
+        printk ("eeprom[32]:  %02x %02x %02x %02x  %02x %02x %02x %02x\n",
+                *(ucp + 32), *(ucp + 33), *(ucp + 34), *(ucp + 35), *(ucp + 36), *(ucp + 37), *(ucp + 38), *(ucp + 39));
+        printk ("eeprom[40]:  %02x %02x %02x %02x  %02x %02x %02x %02x\n",
+                *(ucp + 40), *(ucp + 41), *(ucp + 42), *(ucp + 43), *(ucp + 44), *(ucp + 45), *(ucp + 46), *(ucp + 47));
+    }
+#endif
+#if 0
+    printk ("sn: %x %x %x %x %x %x\n",
+            hi->mfg_info.Serial[0],
+            hi->mfg_info.Serial[1],
+            hi->mfg_info.Serial[2],
+            hi->mfg_info.Serial[3],
+            hi->mfg_info.Serial[4],
+            hi->mfg_info.Serial[5]);
+#endif
+
+    if ((hi->promfmt = pmc_verify_cksum (&hi->mfg_info.data)) == PROM_FORMAT_Unk)
+    {
+        /* bad crc, data is suspect */
+        if (log_level >= LOG_WARN)
+            printk ("%s: EEPROM cksum error\n", hi->devname);
+        hi->mfg_info_sts = EEPROM_CRCERR;
+    } else
+        hi->mfg_info_sts = EEPROM_OK;
+}
+
+
+void        __init
+prep_hdw_info (void)
+{
+    hdw_info_t *hi;
+    int         i;
+
+    for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++)
+    {
+        hi->pci_busno = 0xff;
+        hi->pci_slot = 0xff;
+        hi->pci_pin[0] = 0;
+        hi->pci_pin[1] = 0;
+        hi->ndev = 0;
+        hi->addr[0] = 0L;
+        hi->addr[1] = 0L;
+        hi->addr_mapped[0] = 0L;
+        hi->addr_mapped[1] = 0L;
+    }
+}
+
+void
+cleanup_ioremap (void)
+{
+    hdw_info_t *hi;
+    int         i;
+
+    for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++)
+    {
+        if (hi->pci_slot == 0xff)
+            break;
+        if (hi->addr_mapped[0])
+        {
+            iounmap ((void *) (hi->addr_mapped[0]));
+            release_mem_region ((long) hi->addr[0], hi->len[0]);
+            hi->addr_mapped[0] = 0;
+        }
+        if (hi->addr_mapped[1])
+        {
+            iounmap ((void *) (hi->addr_mapped[1]));
+            release_mem_region ((long) hi->addr[1], hi->len[1]);
+            hi->addr_mapped[1] = 0;
+        }
+    }
+}
+
+
+void
+cleanup_devs (void)
+{
+    hdw_info_t *hi;
+    int         i;
+
+    for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++)
+    {
+        if (hi->pci_slot == 0xff || !hi->ndev)
+            break;
+        c4_stopwd(netdev_priv(hi->ndev));
+#ifdef CONFIG_PROC_FS
+        sbecom_proc_brd_cleanup(netdev_priv(hi->ndev));
+#endif
+        unregister_netdev (hi->ndev);
+        free_irq (hi->pdev[0]->irq, hi->ndev);
+#ifdef CONFIG_SBE_PMCC4_NCOMM
+        free_irq (hi->pdev[1]->irq, hi->ndev);
+#endif
+        OS_kfree (hi->ndev);
+    }
+}
+
+
+STATIC int  __init
+c4_hdw_init (struct pci_dev * pdev, int found)
+{
+    hdw_info_t *hi;
+    int         i;
+    int         fun, slot;
+    unsigned char busno = 0xff;
+
+    /* our MUSYCC chip supports two functions, 0 & 1 */
+    if ((fun = PCI_FUNC (pdev->devfn)) > 1)
+    {
+        printk (KERN_WARNING "%s: unexpected devfun: 0x%x\n", THIS_MODULE->name, pdev->devfn);
+        return 0;
+    }
+    if (pdev->bus)                  /* obtain bus number */
+        busno = pdev->bus->number;
+    else
+        busno = 0;                  /* default for system PCI inconsistency */
+    slot = pdev->devfn & ~0x07;
+
+    /*
+     * Functions 0 & 1 for a given board (identified by same bus(busno) and
+     * slot(slot)) are placed into the same 'hardware' structure.  The first
+     * part of the board's functionality will be placed into an unpopulated
+     * element, identified by "slot==(0xff)".  The second part of a board's
+     * functionality will match the previously loaded slot/busno.
+     */
+    for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++)
+    {
+        /*
+         * match with board's first found interface, otherwise this is first
+         * found
+         */
+        if ((hi->pci_slot == 0xff) ||   /* new board */
+            ((hi->pci_slot == slot) && (hi->bus == pdev->bus)))
+            break;                  /* found for-loop exit */
+    }
+    if (i == MAX_BOARDS)            /* no match in above loop means MAX
+                                     * exceeded */
+    {
+        printk (KERN_WARNING "%s: exceeded number of allowed devices (>%d)?\n",
+                THIS_MODULE->name, MAX_BOARDS);
+        return 0;
+    }
+    if (pdev->bus)
+        hi->pci_busno = pdev->bus->number;
+    else
+        hi->pci_busno = 0;          /* default for system PCI inconsistency */
+    hi->pci_slot = slot;
+    pci_read_config_byte (pdev, PCI_INTERRUPT_PIN, &hi->pci_pin[fun]);
+    pci_read_config_byte (pdev, PCI_REVISION_ID, &hi->revid[fun]);
+    hi->bus = pdev->bus;
+    hi->addr[fun] = pci_resource_start (pdev, 0);
+    hi->len[fun] = pci_resource_end (pdev, 0) - hi->addr[fun] + 1;
+    hi->pdev[fun] = pdev;
+
+    {
+        /*
+         * create device name from module name, plus add the appropriate
+         * board number
+         */
+        char       *cp = hi->devname;
+
+        strcpy (cp, THIS_MODULE->name);
+        cp += strlen (cp);          /* reposition */
+        *cp++ = '-';
+        *cp++ = '0' + (found / 2);  /* there are two found interfaces per
+                                     * board */
+        *cp = 0;                    /* termination */
+    }
+
+    return 1;
+}
+
+
+status_t    __init
+c4hw_attach_all (void)
+{
+    hdw_info_t *hi;
+    struct pci_dev *pdev = NULL;
+    int         found = 0, i, j;
+
+    error_flag = 0;
+    prep_hdw_info ();
+    /*** scan PCI bus for all possible boards */
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
+    while ((pdev = pci_get_device (PCI_VENDOR_ID_CONEXANT,
+                                   PCI_DEVICE_ID_CN8474,
+                                   pdev)))
+#else
+    while ((pdev = pci_find_device (PCI_VENDOR_ID_CONEXANT,
+                                    PCI_DEVICE_ID_CN8474,
+                                    pdev)))
+#endif
+    {
+        if (c4_hdw_init (pdev, found))
+            found++;
+    }
+    if (!found)
+    {
+        printk (KERN_WARNING "%s: No boards found.\n", THIS_MODULE->name);
+        return ENODEV;
+    }
+    /* sanity check for consistant hardware found */
+    for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++)
+    {
+        if (hi->pci_slot != 0xff && (!hi->addr[0] || !hi->addr[1]))
+        {
+            printk (KERN_WARNING "%s: something very wrong with pci_get_device.\n", hi->devname);
+            return EIO;
+        }
+    }
+    /* bring board's memory regions on/line */
+    for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++)
+    {
+        if (hi->pci_slot == 0xff)
+            break;
+        for (j = 0; j < 2; j++)
+        {
+            if (request_mem_region (hi->addr[j], hi->len[j], hi->devname) == 0)
+            {
+                printk (KERN_WARNING "%s: memory in use, addr=0x%lx, len=0x%lx ?\n",
+                        hi->devname, hi->addr[j], hi->len[j]);
+                cleanup_ioremap ();
+                return ENOMEM;
+            }
+            hi->addr_mapped[j] = (unsigned long) ioremap (hi->addr[j], hi->len[j]);
+            if (!hi->addr_mapped[j])
+            {
+                printk (KERN_WARNING "%s: ioremap fails, addr=0x%lx, len=0x%lx ?\n",
+                        hi->devname, hi->addr[j], hi->len[j]);
+                cleanup_ioremap ();
+                return ENOMEM;
+            }
+#ifdef SBE_MAP_DEBUG
+            printk (KERN_WARNING "%s: io remapped from phys %x to virt %x\n",
+                    hi->devname, (u_int32_t) hi->addr[j], (u_int32_t) hi->addr_mapped[j]);
+#endif
+        }
+    }
+
+    drvr_state = SBE_DRVR_AVAILABLE;
+
+    /* Have now memory mapped all boards.  Now allow board's access to system */
+    for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++)
+    {
+        if (hi->pci_slot == 0xff)
+            break;
+        if (pci_enable_device (hi->pdev[0]) ||
+            pci_enable_device (hi->pdev[1]))
+        {
+            drvr_state = SBE_DRVR_DOWN;
+            printk (KERN_WARNING "%s: failed to enable card %d slot %d\n",
+                    hi->devname, i, hi->pci_slot);
+            cleanup_devs ();
+            cleanup_ioremap ();
+            return EIO;
+        }
+        pci_set_master (hi->pdev[0]);
+        pci_set_master (hi->pdev[1]);
+        if (!(hi->ndev = c4_add_dev (hi, i, (long) hi->addr_mapped[0],
+                                     (long) hi->addr_mapped[1],
+                                     hi->pdev[0]->irq,
+                                     hi->pdev[1]->irq)))
+        {
+            drvr_state = SBE_DRVR_DOWN;
+            cleanup_ioremap ();
+            /* NOTE: c4_add_dev() does its own device cleanup */
+#if 0
+            cleanup_devs ();
+#endif
+            return error_flag;      /* error_flag set w/in add_dev() */
+        }
+        show_two (hi, i);           /* displays found information */
+    }
+    return 0;
+}
+
+/***  End-of-File  ***/

drivers/staging/cxt1e1/ossiRelease.c

+/*
+ * $Id: ossiRelease.c,v 1.2 2008/05/08 20:14:03 rdobbs PMCC4_3_1B $
+ */
+
+/*-----------------------------------------------------------------------------
+ * ossiRelease.c -
+ *
+ * This string will be embedded into the executable and will track the
+ * release.  The embedded string may be displayed using the following:
+ *
+ *      strings <filename> | grep \$Rel
+ *
+ * Copyright (C) 2002-2008  One Stop Systems, Inc.
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ * For further information, contact via email: support@onestopsystems.com
+ * One Stop Systems, Inc.  Escondido, California  U.S.A.
+ *
+ *-----------------------------------------------------------------------------
+ * RCS info:
+ * RCS revision: $Revision: 1.2 $
+ * Last changed on $Date: 2008/05/08 20:14:03 $
+ * Changed by $Author: rdobbs $
+ *-----------------------------------------------------------------------------
+ */
+
+
+char pmcc4_OSSI_release[] = "$Release: PMCC4_3_1B,  Copyright (c) 2008 One Stop Systems$";
+
+/***  End-of-File  ***/

drivers/staging/cxt1e1/pmc93x6_eeprom.h

+/*
+ * $Id: pmc93x6_eeprom.h,v 1.1 2005/09/28 00:10:08 rickd PMCC4_3_1B $
+ */
+
+#ifndef _INC_PMC93X6_EEPROM_H_
+#define _INC_PMC93X6_EEPROM_H_
+
+/*-----------------------------------------------------------------------------
+ * pmc93x6_eeprom.h -
+ *
+ * Copyright (C) 2002-2004  SBE, Inc.
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ * For further information, contact via email: support@sbei.com
+ * SBE, Inc.  San Ramon, California  U.S.A.
+ *-----------------------------------------------------------------------------
+ * RCS info:
+ *-----------------------------------------------------------------------------
+ * $Log: pmc93x6_eeprom.h,v $
+ * Revision 1.1  2005/09/28 00:10:08  rickd
+ * pmc_verify_cksum return value is char.
+ *
+ * Revision 1.0  2005/05/04 17:20:51  rickd
+ * Initial revision
+ *
+ * Revision 1.0  2005/04/22 23:48:48  rickd
+ * Initial revision
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+#if defined (__FreeBSD__) || defined (__NetBSD__)
+#include <sys/types.h>
+#else
+#include <linux/types.h>
+#endif
+
+#ifdef __KERNEL__
+
+#include "pmcc4_private.h"
+
+void        pmc_eeprom_read_buffer (long, long, char *, int);
+void        pmc_eeprom_write_buffer (long, long, char *, int);
+void        pmc_init_seeprom (u_int32_t, u_int32_t);
+char        pmc_verify_cksum (void *);
+
+#endif    /*** __KERNEL__ ***/
+
+#endif
+
+/*** End-of-File ***/

drivers/staging/cxt1e1/pmcc4_defs.h

+/*
+ * $Id: pmcc4_defs.h,v 1.0 2005/09/28 00:10:09 rickd PMCC4_3_1B $
+ */
+
+#ifndef _INC_PMCC4_DEFS_H_
+#define _INC_PMCC4_DEFS_H_
+
+/*-----------------------------------------------------------------------------
+ * c4_defs.h -
+ *
+ *   Implementation elements of the wanPMC-C4T1E1 device driver
+ *
+ * Copyright (C) 2005  SBE, Inc.
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ * For further information, contact via email: support@sbei.com
+ * SBE, Inc.  San Ramon, California  U.S.A.
+ *-----------------------------------------------------------------------------
+ * RCS info:
+ * RCS revision: $Revision: 1.0 $
+ * Last changed on $Date: 2005/09/28 00:10:09 $
+ * Changed by $Author: rickd $
+ *-----------------------------------------------------------------------------
+ * $Log: pmcc4_defs.h,v $
+ * Revision 1.0  2005/09/28 00:10:09  rickd
+ * Initial revision
+ *
+ *-----------------------------------------------------------------------------
+ */
+
+
+#define MAX_BOARDS          8
+#define MAX_CHANS_USED      128
+
+#ifdef  SBE_PMCC4_ENABLE
+#define MUSYCC_NPORTS       4     /* CN8474 */
+#endif
+#ifdef SBE_WAN256T3_ENABLE
+#define MUSYCC_NPORTS       8     /* CN8478 */
+#endif
+#define MUSYCC_NCHANS       32    /* actually, chans per port */
+
+#define MUSYCC_NIQD         0x1000    /* power of 2 */
+#define MUSYCC_MRU          2048  /* default */
+#define MUSYCC_MTU          2048  /* default */
+#define MUSYCC_TXDESC_MIN   10    /* HDLC mode default */
+#define MUSYCC_RXDESC_MIN   18    /* HDLC mode default */
+#define MUSYCC_TXDESC_TRANS 4     /* Transparent mode minumum # of TX descriptors */
+#define MUSYCC_RXDESC_TRANS 12    /* Transparent mode minumum # of RX descriptors */
+
+#define MAX_DEFAULT_IFQLEN  32    /* network qlen */
+
+
+#define SBE_IFACETMPL        "pmcc4-%d"
+#ifdef IFNAMSIZ
+#define SBE_IFACETMPL_SIZE    IFNAMSIZ
+#else
+#define SBE_IFACETMPL_SIZE    16
+#endif
+
+/* we want the PMCC4 watchdog to fire off every 250ms */
+#define WATCHDOG_TIMEOUT      250000
+
+/* if we restart the watchdog every 250ms, then we'll time out
+ * an additional 300ms later */
+#define WATCHDOG_UTIMEOUT     (WATCHDOG_TIMEOUT+300000)
+
+#if !defined(SBE_ISR_TASKLET) && !defined(SBE_ISR_IMMEDIATE) && !defined(SBE_ISR_INLINE)
+#define SBE_ISR_TASKLET
+#endif
+
+#endif   /*** _INC_PMCC4_DEFS_H_ ***/
+