提交 50142262 编写于 作者: M Marcel Ziswiler 提交者: Xie XiuQi

ARM: dts: tegra20: restore address order

[ Upstream commit 8188391c127ea34d66f37eda6755d0acb51dc600 ]

Commit 6c468f10 ("ARM: dts: tegra: add Tegra20 NAND flash
controller node") introduced the nand-controller node. However, it got
added at the wrong spot not honoring the address order. Fix this.
Signed-off-by: NMarcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NSasha Levin <sashal@kernel.org>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 1fbc9e51
...@@ -419,19 +419,6 @@ ...@@ -419,19 +419,6 @@
status = "disabled"; status = "disabled";
}; };
gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xd0000000 0xfffffff>;
clocks = <&tegra_car TEGRA20_CLK_NOR>;
clock-names = "gmi";
resets = <&tegra_car 42>;
reset-names = "gmi";
status = "disabled";
};
nand-controller@70008000 { nand-controller@70008000 {
compatible = "nvidia,tegra20-nand"; compatible = "nvidia,tegra20-nand";
reg = <0x70008000 0x100>; reg = <0x70008000 0x100>;
...@@ -447,6 +434,19 @@ ...@@ -447,6 +434,19 @@
status = "disabled"; status = "disabled";
}; };
gmi@70009000 {
compatible = "nvidia,tegra20-gmi";
reg = <0x70009000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0xd0000000 0xfffffff>;
clocks = <&tegra_car TEGRA20_CLK_NOR>;
clock-names = "gmi";
resets = <&tegra_car 42>;
reset-names = "gmi";
status = "disabled";
};
pwm: pwm@7000a000 { pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm"; compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>; reg = <0x7000a000 0x100>;
......
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