提交 4f43143f 编写于 作者: P Paul Mackerras
# #
# Automatically generated make config: don't edit # Automatically generated make config: don't edit
# Linux kernel version: 2.6.24-rc4 # Linux kernel version: 2.6.24-rc6
# Thu Dec 6 16:49:03 2007 # Fri Dec 28 11:01:53 2007
# #
CONFIG_PPC64=y CONFIG_PPC64=y
...@@ -256,7 +256,7 @@ CONFIG_PCI_DOMAINS=y ...@@ -256,7 +256,7 @@ CONFIG_PCI_DOMAINS=y
CONFIG_PCI_SYSCALL=y CONFIG_PCI_SYSCALL=y
# CONFIG_PCIEPORTBUS is not set # CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y CONFIG_ARCH_SUPPORTS_MSI=y
# CONFIG_PCI_MSI is not set CONFIG_PCI_MSI=y
CONFIG_PCI_LEGACY=y CONFIG_PCI_LEGACY=y
# CONFIG_PCI_DEBUG is not set # CONFIG_PCI_DEBUG is not set
CONFIG_PCCARD=y CONFIG_PCCARD=y
...@@ -663,7 +663,25 @@ CONFIG_PATA_PCMCIA=y ...@@ -663,7 +663,25 @@ CONFIG_PATA_PCMCIA=y
# CONFIG_PATA_VIA is not set # CONFIG_PATA_VIA is not set
# CONFIG_PATA_WINBOND is not set # CONFIG_PATA_WINBOND is not set
CONFIG_PATA_PLATFORM=y CONFIG_PATA_PLATFORM=y
# CONFIG_MD is not set CONFIG_MD=y
CONFIG_BLK_DEV_MD=y
CONFIG_MD_LINEAR=y
CONFIG_MD_RAID0=y
CONFIG_MD_RAID1=y
CONFIG_MD_RAID10=y
CONFIG_MD_RAID456=y
CONFIG_MD_RAID5_RESHAPE=y
# CONFIG_MD_MULTIPATH is not set
# CONFIG_MD_FAULTY is not set
CONFIG_BLK_DEV_DM=y
# CONFIG_DM_DEBUG is not set
CONFIG_DM_CRYPT=y
# CONFIG_DM_SNAPSHOT is not set
# CONFIG_DM_MIRROR is not set
# CONFIG_DM_ZERO is not set
# CONFIG_DM_MULTIPATH is not set
# CONFIG_DM_DELAY is not set
# CONFIG_DM_UEVENT is not set
# CONFIG_FUSION is not set # CONFIG_FUSION is not set
# #
...@@ -1686,6 +1704,10 @@ CONFIG_XMON_DISASSEMBLY=y ...@@ -1686,6 +1704,10 @@ CONFIG_XMON_DISASSEMBLY=y
# CONFIG_KEYS is not set # CONFIG_KEYS is not set
# CONFIG_SECURITY is not set # CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_XOR_BLOCKS=y
CONFIG_ASYNC_CORE=y
CONFIG_ASYNC_MEMCPY=y
CONFIG_ASYNC_XOR=y
CONFIG_CRYPTO=y CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_BLKCIPHER=y
......
...@@ -61,6 +61,7 @@ struct mce_regs { ...@@ -61,6 +61,7 @@ struct mce_regs {
static struct mce_regs mce_regs[MAX_MCE_REGS]; static struct mce_regs mce_regs[MAX_MCE_REGS];
static int num_mce_regs; static int num_mce_regs;
static int nmi_virq = NO_IRQ;
static void pas_restart(char *cmd) static void pas_restart(char *cmd)
...@@ -189,6 +190,8 @@ static __init void pas_init_IRQ(void) ...@@ -189,6 +190,8 @@ static __init void pas_init_IRQ(void)
unsigned long openpic_addr; unsigned long openpic_addr;
const unsigned int *opprop; const unsigned int *opprop;
int naddr, opplen; int naddr, opplen;
int mpic_flags;
const unsigned int *nmiprop;
struct mpic *mpic; struct mpic *mpic;
mpic_node = NULL; mpic_node = NULL;
...@@ -221,13 +224,26 @@ static __init void pas_init_IRQ(void) ...@@ -221,13 +224,26 @@ static __init void pas_init_IRQ(void)
openpic_addr = of_read_number(opprop, naddr); openpic_addr = of_read_number(opprop, naddr);
printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr); printk(KERN_DEBUG "OpenPIC addr: %lx\n", openpic_addr);
mpic_flags = MPIC_PRIMARY | MPIC_LARGE_VECTORS | MPIC_NO_BIAS;
nmiprop = of_get_property(mpic_node, "nmi-source", NULL);
if (nmiprop)
mpic_flags |= MPIC_ENABLE_MCK;
mpic = mpic_alloc(mpic_node, openpic_addr, mpic = mpic_alloc(mpic_node, openpic_addr,
MPIC_PRIMARY|MPIC_LARGE_VECTORS, mpic_flags, 0, 0, "PASEMI-OPIC");
0, 0, "PASEMI-OPIC");
BUG_ON(!mpic); BUG_ON(!mpic);
mpic_assign_isu(mpic, 0, openpic_addr + 0x10000); mpic_assign_isu(mpic, 0, openpic_addr + 0x10000);
mpic_init(mpic); mpic_init(mpic);
/* The NMI/MCK source needs to be prio 15 */
if (nmiprop) {
nmi_virq = irq_create_mapping(NULL, *nmiprop);
mpic_irq_set_priority(nmi_virq, 15);
set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
mpic_unmask_irq(nmi_virq);
}
of_node_put(mpic_node); of_node_put(mpic_node);
of_node_put(root); of_node_put(root);
} }
...@@ -247,6 +263,14 @@ static int pas_machine_check_handler(struct pt_regs *regs) ...@@ -247,6 +263,14 @@ static int pas_machine_check_handler(struct pt_regs *regs)
srr0 = regs->nip; srr0 = regs->nip;
srr1 = regs->msr; srr1 = regs->msr;
if (mpic_get_mcirq() == nmi_virq) {
printk(KERN_ERR "NMI delivered\n");
debugger(regs);
mpic_end_irq(nmi_virq);
goto out;
}
dsisr = mfspr(SPRN_DSISR); dsisr = mfspr(SPRN_DSISR);
printk(KERN_ERR "Machine Check on CPU %d\n", cpu); printk(KERN_ERR "Machine Check on CPU %d\n", cpu);
printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1); printk(KERN_ERR "SRR0 0x%016lx SRR1 0x%016lx\n", srr0, srr1);
...@@ -310,7 +334,7 @@ static int pas_machine_check_handler(struct pt_regs *regs) ...@@ -310,7 +334,7 @@ static int pas_machine_check_handler(struct pt_regs *regs)
} }
} }
out:
/* SRR1[62] is from MSR[62] if recoverable, so pass that back */ /* SRR1[62] is from MSR[62] if recoverable, so pass that back */
return !!(srr1 & 0x2); return !!(srr1 & 0x2);
} }
......
...@@ -83,6 +83,7 @@ static u32 mpic_infos[][MPIC_IDX_END] = { ...@@ -83,6 +83,7 @@ static u32 mpic_infos[][MPIC_IDX_END] = {
MPIC_CPU_WHOAMI, MPIC_CPU_WHOAMI,
MPIC_CPU_INTACK, MPIC_CPU_INTACK,
MPIC_CPU_EOI, MPIC_CPU_EOI,
MPIC_CPU_MCACK,
MPIC_IRQ_BASE, MPIC_IRQ_BASE,
MPIC_IRQ_STRIDE, MPIC_IRQ_STRIDE,
...@@ -121,6 +122,7 @@ static u32 mpic_infos[][MPIC_IDX_END] = { ...@@ -121,6 +122,7 @@ static u32 mpic_infos[][MPIC_IDX_END] = {
TSI108_CPU_WHOAMI, TSI108_CPU_WHOAMI,
TSI108_CPU_INTACK, TSI108_CPU_INTACK,
TSI108_CPU_EOI, TSI108_CPU_EOI,
TSI108_CPU_MCACK,
TSI108_IRQ_BASE, TSI108_IRQ_BASE,
TSI108_IRQ_STRIDE, TSI108_IRQ_STRIDE,
...@@ -1126,6 +1128,11 @@ struct mpic * __init mpic_alloc(struct device_node *node, ...@@ -1126,6 +1128,11 @@ struct mpic * __init mpic_alloc(struct device_node *node,
mb(); mb();
} }
if (flags & MPIC_ENABLE_MCK)
mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
| MPIC_GREG_GCONF_MCK);
/* Read feature register, calculate num CPUs and, for non-ISU /* Read feature register, calculate num CPUs and, for non-ISU
* MPICs, num sources as well. On ISU MPICs, sources are counted * MPICs, num sources as well. On ISU MPICs, sources are counted
* as ISUs are added * as ISUs are added
...@@ -1272,6 +1279,11 @@ void __init mpic_init(struct mpic *mpic) ...@@ -1272,6 +1279,11 @@ void __init mpic_init(struct mpic *mpic)
mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
| MPIC_GREG_GCONF_8259_PTHROU_DIS); | MPIC_GREG_GCONF_8259_PTHROU_DIS);
if (mpic->flags & MPIC_NO_BIAS)
mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
| MPIC_GREG_GCONF_NO_BIAS);
/* Set current processor priority to 0 */ /* Set current processor priority to 0 */
mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
...@@ -1438,13 +1450,13 @@ void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask) ...@@ -1438,13 +1450,13 @@ void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
} }
unsigned int mpic_get_one_irq(struct mpic *mpic) static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
{ {
u32 src; u32 src;
src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK); src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
#ifdef DEBUG_LOW #ifdef DEBUG_LOW
DBG("%s: get_one_irq(): %d\n", mpic->name, src); DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
#endif #endif
if (unlikely(src == mpic->spurious_vec)) { if (unlikely(src == mpic->spurious_vec)) {
if (mpic->flags & MPIC_SPV_EOI) if (mpic->flags & MPIC_SPV_EOI)
...@@ -1462,6 +1474,11 @@ unsigned int mpic_get_one_irq(struct mpic *mpic) ...@@ -1462,6 +1474,11 @@ unsigned int mpic_get_one_irq(struct mpic *mpic)
return irq_linear_revmap(mpic->irqhost, src); return irq_linear_revmap(mpic->irqhost, src);
} }
unsigned int mpic_get_one_irq(struct mpic *mpic)
{
return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
}
unsigned int mpic_get_irq(void) unsigned int mpic_get_irq(void)
{ {
struct mpic *mpic = mpic_primary; struct mpic *mpic = mpic_primary;
...@@ -1471,6 +1488,14 @@ unsigned int mpic_get_irq(void) ...@@ -1471,6 +1488,14 @@ unsigned int mpic_get_irq(void)
return mpic_get_one_irq(mpic); return mpic_get_one_irq(mpic);
} }
unsigned int mpic_get_mcirq(void)
{
struct mpic *mpic = mpic_primary;
BUG_ON(mpic == NULL);
return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
}
#ifdef CONFIG_SMP #ifdef CONFIG_SMP
void mpic_request_ipis(void) void mpic_request_ipis(void)
......
...@@ -38,9 +38,6 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic) ...@@ -38,9 +38,6 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic)
extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type); extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type);
extern void mpic_set_vector(unsigned int virq, unsigned int vector); extern void mpic_set_vector(unsigned int virq, unsigned int vector);
extern void mpic_end_irq(unsigned int irq);
extern void mpic_mask_irq(unsigned int irq);
extern void mpic_unmask_irq(unsigned int irq);
extern void mpic_set_affinity(unsigned int irq, cpumask_t cpumask); extern void mpic_set_affinity(unsigned int irq, cpumask_t cpumask);
#endif /* _POWERPC_SYSDEV_MPIC_H */ #endif /* _POWERPC_SYSDEV_MPIC_H */
...@@ -22,7 +22,9 @@ ...@@ -22,7 +22,9 @@
#define MPIC_GREG_GLOBAL_CONF_0 0x00020 #define MPIC_GREG_GLOBAL_CONF_0 0x00020
#define MPIC_GREG_GCONF_RESET 0x80000000 #define MPIC_GREG_GCONF_RESET 0x80000000
#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
#define MPIC_GREG_GCONF_NO_BIAS 0x10000000
#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
#define MPIC_GREG_GCONF_MCK 0x08000000
#define MPIC_GREG_GLOBAL_CONF_1 0x00030 #define MPIC_GREG_GLOBAL_CONF_1 0x00030
#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000 #define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000 #define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
...@@ -78,6 +80,7 @@ ...@@ -78,6 +80,7 @@
#define MPIC_CPU_WHOAMI_MASK 0x0000001f #define MPIC_CPU_WHOAMI_MASK 0x0000001f
#define MPIC_CPU_INTACK 0x000a0 #define MPIC_CPU_INTACK 0x000a0
#define MPIC_CPU_EOI 0x000b0 #define MPIC_CPU_EOI 0x000b0
#define MPIC_CPU_MCACK 0x000c0
/* /*
* Per-source registers * Per-source registers
...@@ -141,6 +144,7 @@ ...@@ -141,6 +144,7 @@
#define TSI108_CPU_WHOAMI 0xffffffff #define TSI108_CPU_WHOAMI 0xffffffff
#define TSI108_CPU_INTACK 0x00004 #define TSI108_CPU_INTACK 0x00004
#define TSI108_CPU_EOI 0x00008 #define TSI108_CPU_EOI 0x00008
#define TSI108_CPU_MCACK 0x00004 /* Doesn't really exist here */
/* /*
* Per-source registers * Per-source registers
...@@ -183,6 +187,7 @@ enum { ...@@ -183,6 +187,7 @@ enum {
MPIC_IDX_CPU_WHOAMI, MPIC_IDX_CPU_WHOAMI,
MPIC_IDX_CPU_INTACK, MPIC_IDX_CPU_INTACK,
MPIC_IDX_CPU_EOI, MPIC_IDX_CPU_EOI,
MPIC_IDX_CPU_MCACK,
MPIC_IDX_IRQ_BASE, MPIC_IDX_IRQ_BASE,
MPIC_IDX_IRQ_STRIDE, MPIC_IDX_IRQ_STRIDE,
...@@ -344,6 +349,10 @@ struct mpic ...@@ -344,6 +349,10 @@ struct mpic
#define MPIC_USES_DCR 0x00000080 #define MPIC_USES_DCR 0x00000080
/* MPIC has 11-bit vector fields (or larger) */ /* MPIC has 11-bit vector fields (or larger) */
#define MPIC_LARGE_VECTORS 0x00000100 #define MPIC_LARGE_VECTORS 0x00000100
/* Enable delivery of prio 15 interrupts as MCK instead of EE */
#define MPIC_ENABLE_MCK 0x00000200
/* Disable bias among target selection, spread interrupts evenly */
#define MPIC_NO_BIAS 0x00000400
/* MPIC HW modification ID */ /* MPIC HW modification ID */
#define MPIC_REGSET_MASK 0xf0000000 #define MPIC_REGSET_MASK 0xf0000000
...@@ -447,10 +456,19 @@ extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask); ...@@ -447,10 +456,19 @@ extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
/* Send a message (IPI) to a given target (cpu number or MSG_*) */ /* Send a message (IPI) to a given target (cpu number or MSG_*) */
void smp_mpic_message_pass(int target, int msg); void smp_mpic_message_pass(int target, int msg);
/* Unmask a specific virq */
extern void mpic_unmask_irq(unsigned int irq);
/* Mask a specific virq */
extern void mpic_mask_irq(unsigned int irq);
/* EOI a specific virq */
extern void mpic_end_irq(unsigned int irq);
/* Fetch interrupt from a given mpic */ /* Fetch interrupt from a given mpic */
extern unsigned int mpic_get_one_irq(struct mpic *mpic); extern unsigned int mpic_get_one_irq(struct mpic *mpic);
/* This one gets to the primary mpic */ /* This one gets from the primary mpic */
extern unsigned int mpic_get_irq(void); extern unsigned int mpic_get_irq(void);
/* Fetch Machine Check interrupt from primary mpic */
extern unsigned int mpic_get_mcirq(void);
/* Set the EPIC clock ratio */ /* Set the EPIC clock ratio */
void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio); void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
......
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