driver: roce: update roce driver from driver team

driver inclusion
category: feature

-----------------------------------------

Based on 15c940a5062b17c9c2d30700194f1bd9c3bde72b
("RDMA/hns: Fix coding style related issues")
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>

drivers/infiniband/hw/hns/hns_roce_alloc.c

@@ -113,16 +113,15 @@ void hns_roce_bitmap_free_range(struct hns_roce_bitmap *bitmap,
 				unsigned long obj, int cnt,
 				int rr)
 {
+	unsigned long base = obj & (bitmap->max + bitmap->reserved_top - 1);
 	int i;
 
-	obj &= bitmap->max + bitmap->reserved_top - 1;
-
 	spin_lock(&bitmap->lock);
 	for (i = 0; i < cnt; i++)
-		clear_bit(obj + i, bitmap->table);
+		clear_bit(base + i, bitmap->table);
 
 	if (!rr)
-		bitmap->last = min(bitmap->last, obj);
+		bitmap->last = min(bitmap->last, base);
 	bitmap->top = (bitmap->top + bitmap->max + bitmap->reserved_top)
 		       & bitmap->mask;
 	spin_unlock(&bitmap->lock);
@@ -186,7 +185,7 @@ int hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, u32 max_direct,
 	u32 page_size = 1 << page_shift;
 	u32 order;
 
-	/* SQ/RQ buf lease than one page, SQ + RQ = 8K */
+	/* buf for SQ/RQ both at lease one page, SQ + RQ is 2 pages */
 	if (size <= max_direct) {
 		buf->nbufs = 1;
 		/* Npages calculated by page_size */

drivers/infiniband/hw/hns/hns_roce_cmd.c

@@ -162,7 +162,7 @@ static int hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
 				  u64 out_param, unsigned long in_modifier,
 				  u8 op_modifier, u16 op, unsigned long timeout)
 {
-	int ret = 0;
+	int ret;
 
 	down(&hr_dev->cmd.event_sem);
 	ret = __hns_roce_cmd_mbox_wait(hr_dev, in_param, out_param,

drivers/infiniband/hw/hns/hns_roce_cq.c

@@ -124,7 +124,8 @@ static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent,
 	/* Get CQC memory HEM(Hardware Entry Memory) table */
 	ret = hns_roce_table_get(hr_dev, &cq_table->table, hr_cq->cqn);
 	if (ret) {
-		dev_err(dev, "CQ alloc.Failed to get context mem.\n");
+		dev_err(dev, "CQ(0x%lx) alloc.Failed to get context mem(%d).\n",
+			hr_cq->cqn, ret);
 		goto err_out;
 	}
 
@@ -134,7 +135,8 @@ static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent,
 	ret = radix_tree_insert(&cq_table->tree, hr_cq->cqn, hr_cq);
 	spin_unlock_irq(&cq_table->lock);
 	if (ret) {
-		dev_err(dev, "CQ alloc.Failed to radix_tree_insert.\n");
+		dev_err(dev, "CQ(0x%lx) alloc.Failed to radix_tree_insert.\n",
+			hr_cq->cqn);
 		goto err_put;
 	}
 
@@ -152,7 +154,8 @@ static int hns_roce_cq_alloc(struct hns_roce_dev *hr_dev, int nent,
 	ret = hns_roce_sw2hw_cq(hr_dev, mailbox, hr_cq->cqn);
 	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
 	if (ret) {
-		dev_err(dev, "CQ alloc.Failed to cmd mailbox.\n");
+		dev_err(dev, "CQ(0x%lx) alloc.Failed to cmd mailbox(%d).\n",
+			hr_cq->cqn, ret);
 		goto err_radix;
 	}
 
@@ -246,12 +249,16 @@ static int hns_roce_ib_get_cq_umem(struct hns_roce_dev *hr_dev,
 				(*umem)->page_shift,
 				&buf->hr_mtt);
 	}
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev, "hns_roce_mtt_init error for create cq\n");
 		goto err_buf;
+	}
 
 	ret = hns_roce_ib_umem_write_mtt(hr_dev, &buf->hr_mtt, *umem);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev, "hns_roce_ib_umem_write_mtt error for create cq\n");
 		goto err_mtt;
+	}
 
 	return 0;
 
@@ -282,12 +289,16 @@ static int hns_roce_ib_alloc_cq_buf(struct hns_roce_dev *hr_dev,
 
 	ret = hns_roce_mtt_init(hr_dev, buf->hr_buf.npages,
 				buf->hr_buf.page_shift, &buf->hr_mtt);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev, "hns_roce_mtt_init error for kernel create cq\n");
 		goto err_buf;
+	}
 
 	ret = hns_roce_buf_write_mtt(hr_dev, &buf->hr_mtt, &buf->hr_buf);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev, "hns_roce_ib_umem_write_mtt error for kernel create cq\n");
 		goto err_mtt;
+	}
 
 	return 0;
 
@@ -365,10 +376,19 @@ static int create_kernel_cq(struct hns_roce_dev *hr_dev,
 	struct device *dev = hr_dev->dev;
 	int ret;
 
+	hr_cq->workq =
+		create_singlethread_workqueue("hns_roce_cq_workqueue");
+	if (!hr_cq->workq) {
+		dev_err(dev, "Failed to create cq workqueue!\n");
+		return -ENOMEM;
+	}
+
 	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
 		ret = hns_roce_alloc_db(hr_dev, &hr_cq->db, 1);
-		if (ret)
-			return ret;
+		if (ret) {
+			dev_err(dev, "Failed to alloc db for cq.\n");
+			goto err_workq;
+		}
 
 		hr_cq->set_ci_db = hr_cq->db.db_record;
 		*hr_cq->set_ci_db = 0;
@@ -378,7 +398,7 @@ static int create_kernel_cq(struct hns_roce_dev *hr_dev,
 	/* Init mmt table and write buff address to mtt table */
 	ret = hns_roce_ib_alloc_cq_buf(hr_dev, &hr_cq->hr_buf, cq_entries);
 	if (ret) {
-		dev_err(dev, "Failed to alloc_cq_buf.\n");
+		dev_err(dev, "Failed to alloc cq buf.\n");
 		goto err_db;
 	}
 
@@ -388,6 +408,9 @@ static int create_kernel_cq(struct hns_roce_dev *hr_dev,
 
 	return 0;
 
+err_workq:
+	destroy_workqueue(hr_cq->workq);
+
 err_db:
 	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB)
 		hns_roce_free_db(hr_dev, &hr_cq->db);
@@ -457,13 +480,13 @@ struct ib_cq *hns_roce_ib_create_cq(struct ib_device *ib_dev,
 		ret = create_user_cq(hr_dev, hr_cq, context, udata, &resp, uar,
 				     cq_entries);
 		if (ret) {
-			dev_err(dev, "Create cq fail in user mode!\n");
+			dev_err(dev, "Failed to create cq for user mode!\n");
 			goto err_cq;
 		}
 	} else {
 		ret = create_kernel_cq(hr_dev, hr_cq, uar, cq_entries);
 		if (ret) {
-			dev_err(dev, "Create cq fail in user mode!\n");
+			dev_err(dev, "Failed to create cq for kernel mode!\n");
 			goto err_cq;
 		}
 	}
@@ -545,6 +568,9 @@ int hns_roce_ib_destroy_cq(struct ib_cq *ib_cq)
 						ib_cq->cqe);
 			if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB)
 				hns_roce_free_db(hr_dev, &hr_cq->db);
+
+			flush_workqueue(hr_cq->workq);
+			destroy_workqueue(hr_cq->workq);
 		}
 
 		kfree(hr_cq);

drivers/infiniband/hw/hns/hns_roce_db.c

@@ -79,7 +79,8 @@ static struct hns_roce_db_pgdir *hns_roce_alloc_db_pgdir(
 	if (!pgdir)
 		return NULL;
 
-	bitmap_fill(pgdir->order1, HNS_ROCE_DB_PER_PAGE / 2);
+	bitmap_fill(pgdir->order1,
+		    HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
 	pgdir->bits[0] = pgdir->order0;
 	pgdir->bits[1] = pgdir->order1;
 	pgdir->page = dma_alloc_coherent(dma_device, PAGE_SIZE,
@@ -117,7 +118,7 @@ static int hns_roce_alloc_db_from_pgdir(struct hns_roce_db_pgdir *pgdir,
 	db->u.pgdir	= pgdir;
 	db->index	= i;
 	db->db_record	= pgdir->page + db->index;
-	db->dma		= pgdir->db_dma  + db->index * 4;
+	db->dma		= pgdir->db_dma  + db->index * HNS_ROCE_DB_UNIT_SIZE;
 	db->order	= order;
 
 	return 0;
@@ -171,7 +172,8 @@ void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db)
 	i >>= o;
 	set_bit(i, db->u.pgdir->bits[o]);
 
-	if (bitmap_full(db->u.pgdir->order1, HNS_ROCE_DB_PER_PAGE / 2)) {
+	if (bitmap_full(db->u.pgdir->order1,
+			HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT)) {
 		dma_free_coherent(hr_dev->dev, PAGE_SIZE, db->u.pgdir->page,
 				  db->u.pgdir->db_dma);
 		list_del(&db->u.pgdir->list);

drivers/infiniband/hw/hns/hns_roce_device.h

@@ -37,9 +37,12 @@
 
 #define DRV_NAME "hns_roce"
 
+/* hip08 is a pci device, it includes two version according pci version id */
+#define PCI_REVISION_ID_HIP08_A			0x20
+#define PCI_REVISION_ID_HIP08_B			0x21
+
 #define HNS_ROCE_HW_VER1	('h' << 24 | 'i' << 16 | '0' << 8 | '6')
 
-#define MAC_ADDR_OCTET_NUM			6
 #define HNS_ROCE_MAX_MSG_LEN			0x80000000
 
 #define HNS_ROCE_ALOGN_UP(a, b) ((((a) + (b) - 1) / (b)) * (b))
@@ -48,6 +51,10 @@
 
 #define HNS_ROCE_BA_SIZE			(32 * 4096)
 
+#define BA_BYTE_LEN				8
+
+#define BITS_PER_BYTE				8
+
 /* Hardware specification only for v1 engine */
 #define HNS_ROCE_MIN_CQE_NUM			0x40
 #define HNS_ROCE_MIN_WQE_NUM			0x20
@@ -55,6 +62,8 @@
 /* Hardware specification only for v1 engine */
 #define HNS_ROCE_MAX_INNER_MTPT_NUM		0x7
 #define HNS_ROCE_MAX_MTPT_PBL_NUM		0x100000
+#define HNS_ROCE_MAX_SGE_NUM			2
+
 
 #define HNS_ROCE_EACH_FREE_CQ_WAIT_MSECS	20
 #define HNS_ROCE_MAX_FREE_CQ_WAIT_CNT	\
@@ -64,6 +73,9 @@
 
 #define HNS_ROCE_MAX_IRQ_NUM			128
 
+#define HNS_ROCE_SGE_IN_WQE			2
+#define HNS_ROCE_SGE_SHIFT			4
+
 #define EQ_ENABLE				1
 #define EQ_DISABLE				0
 
@@ -82,6 +94,8 @@
 #define HNS_ROCE_MAX_GID_NUM			16
 #define HNS_ROCE_GID_SIZE			16
 
+#define HNS_ROCE_SGE_SIZE			16
+
 #define HNS_ROCE_HOP_NUM_0			0xff
 
 #define BITMAP_NO_RR				0
@@ -114,6 +128,8 @@
 #define PAGES_SHIFT_24				24
 #define PAGES_SHIFT_32				32
 
+#define HNS_ROCE_PCI_BAR_NR			2
+
 #define HNS_ROCE_IDX_QUE_ENTRY_SZ		4
 
 #define HNS_ROCE_FRMR_MAX_PA			512
@@ -139,6 +155,12 @@ enum hns_roce_qp_state {
 	HNS_ROCE_QP_NUM_STATE,
 };
 
+enum queue_type {
+	HNS_ROCE_SQ,
+	HNS_ROCE_RQ,
+	HNS_ROCE_CQ,
+};
+
 enum hns_roce_event {
 	HNS_ROCE_EVENT_TYPE_PATH_MIG                  = 0x01,
 	HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED           = 0x02,
@@ -220,6 +242,9 @@ enum hns_roce_mtt_type {
 	MTT_TYPE_IDX
 };
 
+#define HNS_ROCE_DB_TYPE_COUNT			2
+#define HNS_ROCE_DB_UNIT_SIZE			4
+
 enum {
 	HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4
 };
@@ -329,7 +354,7 @@ struct hns_roce_hem_table {
 	unsigned long	num_hem;
 	/* HEM entry record obj total num */
 	unsigned long	num_obj;
-	/*Single obj size */
+	/* Single obj size */
 	unsigned long	obj_size;
 	unsigned long	table_chunk_size;
 	int		lowmem;
@@ -368,25 +393,25 @@ struct hns_roce_mr {
 	u64			size; /* Address range of MR */
 	u32			key; /* Key of MR */
 	u32			pd;   /* PD num of MR */
-	u32			access;/* Access permission of MR */
+	u32			access; /* Access permission of MR */
 	u32			npages;
 	int			enabled; /* MR's active status */
 	int			type;	/* MR's register type */
-	u64			*pbl_buf;/* MR's PBL space */
+	u64			*pbl_buf; /* MR's PBL space */
 	dma_addr_t		pbl_dma_addr;	/* MR's PBL space PA */
-	u32			pbl_size;/* PA number in the PBL */
-	u64			pbl_ba;/* page table address */
-	u32			l0_chunk_last_num;/* L0 last number */
-	u32			l1_chunk_last_num;/* L1 last number */
-	u64			**pbl_bt_l2;/* PBL BT L2 */
-	u64			**pbl_bt_l1;/* PBL BT L1 */
-	u64			*pbl_bt_l0;/* PBL BT L0 */
-	dma_addr_t		*pbl_l2_dma_addr;/* PBL BT L2 dma addr */
-	dma_addr_t		*pbl_l1_dma_addr;/* PBL BT L1 dma addr */
-	dma_addr_t		pbl_l0_dma_addr;/* PBL BT L0 dma addr */
-	u32			pbl_ba_pg_sz;/* BT chunk page size */
-	u32			pbl_buf_pg_sz;/* buf chunk page size */
-	u32			pbl_hop_num;/* multi-hop number */
+	u32			pbl_size; /* PA number in the PBL */
+	u64			pbl_ba; /* page table address */
+	u32			l0_chunk_last_num; /* L0 last number */
+	u32			l1_chunk_last_num; /* L1 last number */
+	u64			**pbl_bt_l2; /* PBL BT L2 */
+	u64			**pbl_bt_l1; /* PBL BT L1 */
+	u64			*pbl_bt_l0; /* PBL BT L0 */
+	dma_addr_t		*pbl_l2_dma_addr; /* PBL BT L2 dma addr */
+	dma_addr_t		*pbl_l1_dma_addr; /* PBL BT L1 dma addr */
+	dma_addr_t		pbl_l0_dma_addr; /* PBL BT L0 dma addr */
+	u32			pbl_ba_pg_sz; /* BT chunk page size */
+	u32			pbl_buf_pg_sz; /* buf chunk page size */
+	u32			pbl_hop_num; /* multi-hop number */
 };
 
 struct hns_roce_mr_table {
@@ -409,16 +434,17 @@ struct hns_roce_wq {
 	u32		max_post;
 	int		max_gs;
 	int		offset;
-	int		wqe_shift;/* WQE size */
+	int		wqe_shift; /* WQE size */
 	u32		head;
 	u32		tail;
 	void __iomem	*db_reg_l;
+	struct workqueue_struct *workq;
 };
 
 struct hns_roce_sge {
 	int		sge_cnt;  /* SGE num */
 	int		offset;
-	int		sge_shift;/* SGE size */
+	int		sge_shift; /* SGE size */
 };
 
 struct hns_roce_buf_list {
@@ -437,8 +463,8 @@ struct hns_roce_buf {
 struct hns_roce_db_pgdir {
 	struct list_head	list;
 	DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE);
-	DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / 2);
-	unsigned long		*bits[2];
+	DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT);
+	unsigned long		*bits[HNS_ROCE_DB_TYPE_COUNT];
 	u32			*page;
 	dma_addr_t		db_dma;
 };
@@ -488,6 +514,7 @@ struct hns_roce_cq {
 	u32				vector;
 	atomic_t			refcount;
 	struct completion		free;
+	struct workqueue_struct		*workq;
 };
 
 struct hns_roce_idx_que {
@@ -575,7 +602,7 @@ struct hns_roce_av {
 	u8          hop_limit;
 	__le32      sl_tclass_flowlabel;
 	u8          dgid[HNS_ROCE_GID_SIZE];
-	u8          mac[6];
+	u8          mac[ETH_ALEN];
 	__le16      vlan;
 	bool	    vlan_en;
 };
@@ -666,6 +693,8 @@ struct hns_roce_qp {
 	u8			sl;
 	u8			resp_depth;
 	u8			state;
+	u8			next_state;	/* record for flush cqe */
+	int			attr_mask;	/* record for flush cqe */
 	u32			access_flags;
 	u32                     atomic_rd_en;
 	u32			pkey_index;
@@ -907,6 +936,13 @@ struct hns_roce_work {
 	int event_type;
 	int sub_type;
 };
+
+struct hns_roce_flush_work {
+	struct hns_roce_dev *hr_dev;
+	struct work_struct work;
+	struct hns_roce_qp *hr_qp;
+};
+
 struct hns_roce_stat {
 	int cqn;
 	int srqn;
@@ -979,7 +1015,7 @@ struct hns_roce_hw {
 			  dma_addr_t dma_handle, int nent, u32 vector);
 	int (*set_hem)(struct hns_roce_dev *hr_dev,
 		       struct hns_roce_hem_table *table, int obj, int step_idx);
-	int (*clear_hem)(struct hns_roce_dev *hr_dev,
+	void (*clear_hem)(struct hns_roce_dev *hr_dev,
 			 struct hns_roce_hem_table *table, int obj,
 			 int step_idx);
 	int (*query_qp)(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
@@ -1048,7 +1084,7 @@ struct hns_roce_dev {
 	struct hns_roce_caps	caps;
 	struct radix_tree_root  qp_table_tree;
 
-	unsigned char	dev_addr[HNS_ROCE_MAX_PORTS][MAC_ADDR_OCTET_NUM];
+	unsigned char	dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN];
 	u64			sys_image_guid;
 	u32                     vendor_id;
 	u32                     vendor_part_id;
@@ -1267,6 +1303,8 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *ib_pd,
 				 struct ib_udata *udata);
 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 		       int attr_mask, struct ib_udata *udata);
+void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
+			    struct hns_roce_cq *cq, enum queue_type type);
 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n);
 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n);
 void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n);
@@ -1314,6 +1352,16 @@ int hns_roce_fill_res_entry(struct sk_buff *msg,
 int hns_roce_register_sysfs(struct hns_roce_dev *hr_dev);
 void hns_roce_unregister_sysfs(struct hns_roce_dev *hr_dev);
 
+enum hns_phy_state {
+	HNS_ROCE_PHY_SLEEP		= 1,
+	HNS_ROCE_PHY_POLLING		= 2,
+	HNS_ROCE_PHY_DISABLED		= 3,
+	HNS_ROCE_PHY_TRAINING		= 4,
+	HNS_ROCE_PHY_LINKUP		= 5,
+	HNS_ROCE_PHY_LINKERR		= 6,
+	HNS_ROCE_PHY_TEST		= 7
+};
+
 #ifdef CONFIG_INFINIBAND_HNS_DFX
 enum {
 	RDFX_FUNC_MODIFY_DEVICE,

drivers/infiniband/hw/hns/hns_roce_hem.c

@@ -189,7 +189,7 @@ static int get_hem_table_config(struct hns_roce_dev *hr_dev,
 					     + PAGE_SHIFT);
 		mhop->bt_chunk_size = 1 << (hr_dev->caps.mtt_ba_pg_sz
 					     + PAGE_SHIFT);
-		mhop->ba_l0_num = mhop->bt_chunk_size / 8;
+		mhop->ba_l0_num = mhop->bt_chunk_size / BA_BYTE_LEN;
 		mhop->hop_num = hr_dev->caps.mtt_hop_num;
 		break;
 	case HEM_TYPE_CQE:
@@ -197,7 +197,7 @@ static int get_hem_table_config(struct hns_roce_dev *hr_dev,
 					     + PAGE_SHIFT);
 		mhop->bt_chunk_size = 1 << (hr_dev->caps.cqe_ba_pg_sz
 					     + PAGE_SHIFT);
-		mhop->ba_l0_num = mhop->bt_chunk_size / 8;
+		mhop->ba_l0_num = mhop->bt_chunk_size / BA_BYTE_LEN;
 		mhop->hop_num = hr_dev->caps.cqe_hop_num;
 		break;
 	case HEM_TYPE_SRQWQE:
@@ -205,7 +205,7 @@ static int get_hem_table_config(struct hns_roce_dev *hr_dev,
 					    + PAGE_SHIFT);
 		mhop->bt_chunk_size = 1 << (hr_dev->caps.srqwqe_ba_pg_sz
 					    + PAGE_SHIFT);
-		mhop->ba_l0_num = mhop->bt_chunk_size / 8;
+		mhop->ba_l0_num = mhop->bt_chunk_size / BA_BYTE_LEN;
 		mhop->hop_num = hr_dev->caps.srqwqe_hop_num;
 		break;
 	case HEM_TYPE_IDX:
@@ -213,7 +213,7 @@ static int get_hem_table_config(struct hns_roce_dev *hr_dev,
 				       + PAGE_SHIFT);
 		mhop->bt_chunk_size = 1 << (hr_dev->caps.idx_ba_pg_sz
 				       + PAGE_SHIFT);
-		mhop->ba_l0_num = mhop->bt_chunk_size / 8;
+		mhop->ba_l0_num = mhop->bt_chunk_size / BA_BYTE_LEN;
 		mhop->hop_num = hr_dev->caps.idx_hop_num;
 		break;
 	default:
@@ -246,7 +246,7 @@ int hns_roce_calc_hem_mhop(struct hns_roce_dev *hr_dev,
 	 * MTT/CQE alloc hem for bt pages.
 	 */
 	bt_num = hns_roce_get_bt_num(table->type, mhop->hop_num);
-	chunk_ba_num = mhop->bt_chunk_size / 8;
+	chunk_ba_num = mhop->bt_chunk_size / BA_BYTE_LEN;
 	chunk_size = table->type < HEM_TYPE_MTT ? mhop->buf_chunk_size :
 			      mhop->bt_chunk_size;
 	table_idx = (*obj & (table->num_obj - 1)) /
@@ -286,6 +286,7 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev,
 	struct scatterlist *mem;
 	int order;
 	void *buf;
+	int left;
 
 	WARN_ON(gfp_mask & __GFP_HIGHMEM);
 
@@ -298,8 +299,8 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev,
 	INIT_LIST_HEAD(&hem->chunk_list);
 
 	order = get_order(hem_alloc_size);
-
-	while (npages > 0) {
+	left = npages;
+	while (left > 0) {
 		if (!chunk) {
 			chunk = kmalloc(sizeof(*chunk),
 				gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
@@ -313,7 +314,7 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev,
 			list_add_tail(&chunk->list, &hem->chunk_list);
 		}
 
-		while (1 << order > npages)
+		while (1 << order > left)
 			--order;
 
 		/*
@@ -331,7 +332,7 @@ static struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev,
 
 		++chunk->npages;
 		++chunk->nsg;
-		npages -= 1 << order;
+		left -= 1 << order;
 	}
 
 	return hem;
@@ -475,7 +476,7 @@ static int hns_roce_table_mhop_get(struct hns_roce_dev *hr_dev,
 	buf_chunk_size = mhop.buf_chunk_size;
 	bt_chunk_size = mhop.bt_chunk_size;
 	hop_num = mhop.hop_num;
-	chunk_ba_num = bt_chunk_size / 8;
+	chunk_ba_num = bt_chunk_size / BA_BYTE_LEN;
 
 	bt_num = hns_roce_get_bt_num(table->type, hop_num);
 	switch (bt_num) {
@@ -521,9 +522,11 @@ static int hns_roce_table_mhop_get(struct hns_roce_dev *hr_dev,
 		/* set base address to hardware */
 		if (table->type < HEM_TYPE_MTT) {
 			step_idx = 0;
-			if (hr_dev->hw->set_hem(hr_dev, table, obj, step_idx)) {
+			ret = hr_dev->hw->set_hem(hr_dev, table, obj, step_idx);
+			if (ret) {
+				dev_err(dev, "set HEM base address to HW failed(%d), type = %d\n",
+					ret, table->type);
 				ret = -ENODEV;
-				dev_err(dev, "set HEM base address to HW failed!\n");
 				goto err_dma_alloc_l1;
 			}
 		}
@@ -545,9 +548,11 @@ static int hns_roce_table_mhop_get(struct hns_roce_dev *hr_dev,
 
 		/* set base address to hardware */
 		step_idx = 1;
-		if (hr_dev->hw->set_hem(hr_dev, table, obj, step_idx)) {
+		ret = hr_dev->hw->set_hem(hr_dev, table, obj, step_idx);
+		if (ret) {
+			dev_err(dev, "set HEM base address to HW failed(%d), type = %d\n",
+				ret, table->type);
 			ret = -ENODEV;
-			dev_err(dev, "set HEM base address to HW failed!\n");
 			goto err_alloc_hem_buf;
 		}
 	}
@@ -585,9 +590,11 @@ static int hns_roce_table_mhop_get(struct hns_roce_dev *hr_dev,
 		}
 
 		/* set HEM base address to hardware */
-		if (hr_dev->hw->set_hem(hr_dev, table, obj, step_idx)) {
+		ret = hr_dev->hw->set_hem(hr_dev, table, obj, step_idx);
+		if (ret) {
+			dev_err(dev, "set HEM base address to HW failed(%d), type = %d\n",
+				ret, table->type);
 			ret = -ENODEV;
-			dev_err(dev, "set HEM base address to HW failed!\n");
 			goto err_alloc_hem_buf;
 		}
 	} else if (hop_num == 2) {
@@ -685,7 +692,7 @@ static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev,
 
 	bt_chunk_size = mhop.bt_chunk_size;
 	hop_num = mhop.hop_num;
-	chunk_ba_num = bt_chunk_size / 8;
+	chunk_ba_num = bt_chunk_size / BA_BYTE_LEN;
 
 	bt_num = hns_roce_get_bt_num(table->type, hop_num);
 	switch (bt_num) {
@@ -713,17 +720,12 @@ static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev,
 		return;
 	}
 
-	if (table->type < HEM_TYPE_MTT && hop_num == 1) {
-		if (hr_dev->hw->clear_hem(hr_dev, table, obj, 1))
-			dev_warn(dev, "Clear HEM base address failed.\n");
-	} else if (table->type < HEM_TYPE_MTT && hop_num == 2) {
-		if (hr_dev->hw->clear_hem(hr_dev, table, obj, 2))
-			dev_warn(dev, "Clear HEM base address failed.\n");
-	} else if (table->type < HEM_TYPE_MTT &&
-		   hop_num == HNS_ROCE_HOP_NUM_0) {
-		if (hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
-			dev_warn(dev, "Clear HEM base address failed.\n");
-	}
+	if (table->type < HEM_TYPE_MTT && hop_num == 1)
+		hr_dev->hw->clear_hem(hr_dev, table, obj, 1);
+	else if (table->type < HEM_TYPE_MTT && hop_num == 2)
+		hr_dev->hw->clear_hem(hr_dev, table, obj, 2);
+	else if (table->type < HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0)
+		hr_dev->hw->clear_hem(hr_dev, table, obj, 0);
 
 	/*
 	 * free buffer space chunk for QPC/MTPT/CQC/SRQC/SCC_CTX.
@@ -736,9 +738,8 @@ static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev,
 		start_idx = mhop.l0_idx * chunk_ba_num;
 		if (hns_roce_check_hem_null(table->hem, start_idx,
 					    chunk_ba_num)) {
-			if (table->type < HEM_TYPE_MTT &&
-			    hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
-				dev_warn(dev, "Clear HEM base address failed.\n");
+			if (table->type < HEM_TYPE_MTT)
+				hr_dev->hw->clear_hem(hr_dev, table, obj, 0);
 
 			dma_free_coherent(dev, bt_chunk_size,
 					  table->bt_l0[mhop.l0_idx],
@@ -750,8 +751,7 @@ static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev,
 			    mhop.l1_idx * chunk_ba_num;
 		if (hns_roce_check_hem_null(table->hem, start_idx,
 					    chunk_ba_num)) {
-			if (hr_dev->hw->clear_hem(hr_dev, table, obj, 1))
-				dev_warn(dev, "Clear HEM base address failed.\n");
+			hr_dev->hw->clear_hem(hr_dev, table, obj, 1);
 
 			dma_free_coherent(dev, bt_chunk_size,
 					  table->bt_l1[bt_l1_idx],
@@ -761,9 +761,7 @@ static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev,
 			start_idx = mhop.l0_idx * chunk_ba_num;
 			if (hns_roce_check_bt_null(table->bt_l1, start_idx,
 						   chunk_ba_num)) {
-				if (hr_dev->hw->clear_hem(hr_dev, table, obj,
-							  0))
-					dev_warn(dev, "Clear HEM base address failed.\n");
+				hr_dev->hw->clear_hem(hr_dev, table, obj, 0);
 
 				dma_free_coherent(dev, bt_chunk_size,
 					    table->bt_l0[mhop.l0_idx],
@@ -779,7 +777,6 @@ static void hns_roce_table_mhop_put(struct hns_roce_dev *hr_dev,
 void hns_roce_table_put(struct hns_roce_dev *hr_dev,
 			struct hns_roce_hem_table *table, unsigned long obj)
 {
-	struct device *dev = hr_dev->dev;
 	unsigned long i;
 
 	if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
@@ -794,8 +791,7 @@ void hns_roce_table_put(struct hns_roce_dev *hr_dev,
 
 	if (--table->hem[i]->refcount == 0) {
 		/* Clear HEM base address */
-		if (hr_dev->hw->clear_hem(hr_dev, table, obj, 0))
-			dev_warn(dev, "Clear HEM base address failed.\n");
+		hr_dev->hw->clear_hem(hr_dev, table, obj, 0);
 
 		hns_roce_free_hem(hr_dev, table->hem[i]);
 		table->hem[i] = NULL;
@@ -832,12 +828,14 @@ void *hns_roce_table_find(struct hns_roce_dev *hr_dev,
 		idx_offset = (obj & (table->num_obj - 1)) % obj_per_chunk;
 		dma_offset = offset = idx_offset * table->obj_size;
 	} else {
-		hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop);
+		if (hns_roce_calc_hem_mhop(hr_dev, table, &mhop_obj, &mhop))
+			goto out;
+
 		/* mtt mhop */
 		i = mhop.l0_idx;
 		j = mhop.l1_idx;
 		if (mhop.hop_num == 2)
-			hem_idx = i * (mhop.bt_chunk_size / 8) + j;
+			hem_idx = i * (mhop.bt_chunk_size / BA_BYTE_LEN) + j;
 		else if (mhop.hop_num == 1 ||
 			 mhop.hop_num == HNS_ROCE_HOP_NUM_0)
 			hem_idx = i;
@@ -886,7 +884,9 @@ int hns_roce_table_get_range(struct hns_roce_dev *hr_dev,
 	int ret;
 
 	if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
-		hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop);
+		ret = get_hem_table_config(hr_dev, &mhop, table->type);
+		if (ret)
+			return ret;
 		inc = mhop.bt_chunk_size / table->obj_size;
 	}
 
@@ -916,7 +916,8 @@ void hns_roce_table_put_range(struct hns_roce_dev *hr_dev,
 	unsigned long i;
 
 	if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
-		hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop);
+		if (get_hem_table_config(hr_dev, &mhop, table->type))
+			return;
 		inc = mhop.bt_chunk_size / table->obj_size;
 	}
 
@@ -958,7 +959,7 @@ int hns_roce_init_hem_table(struct hns_roce_dev *hr_dev,
 
 		obj_per_chunk = buf_chunk_size / obj_size;
 		num_hem = (nobj + obj_per_chunk - 1) / obj_per_chunk;
-		bt_chunk_num = bt_chunk_size / 8;
+		bt_chunk_num = bt_chunk_size / BA_BYTE_LEN;
 		if (type >= HEM_TYPE_MTT)
 			num_bt_l0 = bt_chunk_num;
 
@@ -1035,17 +1036,20 @@ static void hns_roce_cleanup_mhop_hem_table(struct hns_roce_dev *hr_dev,
 {
 	struct hns_roce_hem_mhop mhop;
 	u32 buf_chunk_size;
-	int i;
+	int ret;
 	u64 obj;
+	int i;
 
-	hns_roce_calc_hem_mhop(hr_dev, table, NULL, &mhop);
-	buf_chunk_size = table->type < HEM_TYPE_MTT ? mhop.buf_chunk_size :
-					mhop.bt_chunk_size;
+	ret = get_hem_table_config(hr_dev, &mhop, table->type);
+	if (!ret) {
+		buf_chunk_size = table->type < HEM_TYPE_MTT ?
+				 mhop.buf_chunk_size : mhop.bt_chunk_size;
 
-	for (i = 0; i < table->num_hem; ++i) {
-		obj = i * buf_chunk_size / table->obj_size;
-		if (table->hem[i])
-			hns_roce_table_mhop_put(hr_dev, table, obj, 0);
+		for (i = 0; i < table->num_hem; ++i) {
+			obj = i * buf_chunk_size / table->obj_size;
+			if (table->hem[i])
+				hns_roce_table_mhop_put(hr_dev, table, obj, 0);
+		}
 	}
 
 	kfree(table->hem);
@@ -1063,7 +1067,6 @@ static void hns_roce_cleanup_mhop_hem_table(struct hns_roce_dev *hr_dev,
 void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev,
 				struct hns_roce_hem_table *table)
 {
-	struct device *dev = hr_dev->dev;
 	unsigned long i;
 
 	if (hns_roce_check_whether_mhop(hr_dev, table->type)) {
@@ -1073,9 +1076,8 @@ void hns_roce_cleanup_hem_table(struct hns_roce_dev *hr_dev,
 
 	for (i = 0; i < table->num_hem; ++i)
 		if (table->hem[i]) {
-			if (hr_dev->hw->clear_hem(hr_dev, table,
-			    i * table->table_chunk_size / table->obj_size, 0))
-				dev_err(dev, "Clear HEM base address failed.\n");
+			hr_dev->hw->clear_hem(hr_dev, table,
+			    i * table->table_chunk_size / table->obj_size, 0);
 
 			hns_roce_free_hem(hr_dev, table->hem[i]);
 		}

drivers/infiniband/hw/hns/hns_roce_hem.h

@@ -62,16 +62,16 @@ enum {
 	 (sizeof(struct scatterlist)))
 
 #define check_whether_bt_num_3(type, hop_num) \
-	(type < HEM_TYPE_MTT && hop_num == 2)
+	((type) < HEM_TYPE_MTT && (hop_num) == 2)
 
 #define check_whether_bt_num_2(type, hop_num) \
-	((type < HEM_TYPE_MTT && hop_num == 1) || \
-	(type >= HEM_TYPE_MTT && hop_num == 2))
+	(((type) < HEM_TYPE_MTT && (hop_num) == 1) || \
+	((type) >= HEM_TYPE_MTT && (hop_num) == 2))
 
 #define check_whether_bt_num_1(type, hop_num) \
-	((type < HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0) || \
-	(type >= HEM_TYPE_MTT && hop_num == 1) || \
-	(type >= HEM_TYPE_MTT && hop_num == HNS_ROCE_HOP_NUM_0))
+	(((type) < HEM_TYPE_MTT && (hop_num) == HNS_ROCE_HOP_NUM_0) || \
+	((type) >= HEM_TYPE_MTT && (hop_num) == 1) || \
+	((type) >= HEM_TYPE_MTT && (hop_num) == HNS_ROCE_HOP_NUM_0))
 
 enum {
 	 HNS_ROCE_HEM_PAGE_SHIFT = 12,

drivers/infiniband/hw/hns/hns_roce_hw_sysfs_v2.c

@@ -53,17 +53,15 @@ int hns_roce_v2_query_mpt_stat(struct hns_roce_dev *hr_dev,
 {
 	struct hns_roce_v2_mpt_entry *mpt_ctx;
 	struct hns_roce_cmd_mailbox *mailbox;
+	int key = hr_dev->hr_stat.key;
+	int cur_len = 0;
+	char *out = buf;
 	u64 bt0_ba = 0;
 	u64 bt1_ba = 0;
 	int *mpt;
 	int ret;
 	int i;
-	char *buff;
-	int key = hr_dev->hr_stat.key;
 
-	buff = kmalloc(1024, GFP_KERNEL);
-	if (!buff)
-		return -ENOMEM;
 	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
 	if (IS_ERR(mailbox))
 		return PTR_ERR(mailbox);
@@ -98,43 +96,41 @@ int hns_roce_v2_query_mpt_stat(struct hns_roce_dev *hr_dev,
 	else
 		goto err_mailbox;
 
-	*desc += sprintf(buff + *desc, "MPT(0x%x) BT0: 0x%llx\n", key, bt0_ba);
-	*desc += sprintf(buff + *desc, "MPT(0x%x) BT1: 0x%llx\n", key, bt1_ba);
+	hns_roce_v2_sysfs_print(out, cur_len,
+				"MPT(0x%x) BT0: 0x%llx\n", key, bt0_ba);
+	hns_roce_v2_sysfs_print(out, cur_len,
+				"MPT(0x%x) BT1: 0x%llx\n", key, bt1_ba);
 	mpt = (int *)mpt_ctx;
 	for (i = 0; i < (sizeof(*mpt_ctx) >> 2); i += 8) {
-		*desc += sprintf(buff + *desc,
+		hns_roce_v2_sysfs_print(out, cur_len,
 		 "MPT(0x%x): %08x %08x %08x %08x %08x %08x %08x %08x\n",
 			key, *mpt, *(mpt + 1), *(mpt + 2),
 			*(mpt + 3), *(mpt + 4), *(mpt + 5),
 			*(mpt + 6), *(mpt + 7));
 		mpt += 8;
 	}
-	memcpy(buf, buff, *desc);
+	*desc += cur_len;
 
 err_mailbox:
 	kfree(mpt_ctx);
 err_cmd:
 	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
-	kfree(buff);
 
 	return ret;
 }
 int hns_roce_v2_query_srqc_stat(struct hns_roce_dev *hr_dev,
 				char *buf, int *desc)
 {
-	struct hns_roce_cmd_mailbox *mailbox;
 	struct hns_roce_srq_context *srq_context;
+	struct hns_roce_cmd_mailbox *mailbox;
+	int srqn = hr_dev->hr_stat.srqn;
+	int cur_len = 0;
+	char *out = buf;
 	u64 bt0_ba = 0;
 	u64 bt1_ba = 0;
 	int *srqc;
-	int ret;
 	int i = 0;
-	char *buff;
-	int srqn = hr_dev->hr_stat.srqn;
-
-	buff = kmalloc(1024, GFP_KERNEL);
-	if (!buff)
-		return -ENOMEM;
+	int ret;
 
 	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
 	if (IS_ERR(mailbox))
@@ -162,26 +158,25 @@ int hns_roce_v2_query_srqc_stat(struct hns_roce_dev *hr_dev,
 	else
 		goto err_mailbox;
 
-	*desc += sprintf(buff + *desc,
-		 "SRQC(0x%x) BT0: 0x%llx\n", srqn, bt0_ba);
-	*desc += sprintf(buff + *desc,
-		 "SRQC(0x%x) BT1: 0x%llx\n", srqn, bt1_ba);
+	hns_roce_v2_sysfs_print(out, cur_len,
+				"SRQC(0x%x) BT0: 0x%llx\n", srqn, bt0_ba);
+	hns_roce_v2_sysfs_print(out, cur_len,
+				"SRQC(0x%x) BT1: 0x%llx\n", srqn, bt1_ba);
 	srqc = (int *)srq_context;
 	for (i = 0; i < (sizeof(*srq_context) >> 2); i += 8) {
-		*desc += sprintf(buff + *desc,
+		hns_roce_v2_sysfs_print(out, cur_len,
 		 "SRQC(0x%x): %08x %08x %08x %08x %08x %08x %08x %08x\n",
 			srqn, *srqc, *(srqc + 1), *(srqc + 2),
 			*(srqc + 3), *(srqc + 4), *(srqc + 5),
 			*(srqc + 6), *(srqc + 7));
 		srqc += 8;
 	}
-	memcpy(buf, buff, *desc);
+	*desc += cur_len;
 
 err_mailbox:
 	kfree(srq_context);
 err_cmd:
 	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
-	kfree(buff);
 
 	return ret;
 }
@@ -190,17 +185,14 @@ int hns_roce_v2_query_qpc_stat(struct hns_roce_dev *hr_dev,
 {
 	struct hns_roce_cmd_mailbox *mailbox;
 	struct hns_roce_v2_qp_context *qp_context;
+	int qpn = hr_dev->hr_stat.qpn;
+	int cur_len = 0;
+	char *out = buf;
 	u64 bt0_ba = 0;
 	u64 bt1_ba = 0;
 	int *qpc;
-	int ret;
 	int i = 0;
-	char *buff;
-	int qpn = hr_dev->hr_stat.qpn;
-
-	buff = kmalloc(1024, GFP_KERNEL);
-	if (!buff)
-		return -ENOMEM;
+	int ret;
 
 	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
 	if (IS_ERR(mailbox))
@@ -236,24 +228,25 @@ int hns_roce_v2_query_qpc_stat(struct hns_roce_dev *hr_dev,
 	else
 		goto err_mailbox;
 
-	*desc += sprintf(buff + *desc, "QPC(0x%x) BT0: 0x%llx\n", qpn, bt0_ba);
-	*desc += sprintf(buff + *desc, "QPC(0x%x) BT1: 0x%llx\n", qpn, bt1_ba);
+	hns_roce_v2_sysfs_print(out, cur_len,
+				"QPC(0x%x) BT0: 0x%llx\n", qpn, bt0_ba);
+	hns_roce_v2_sysfs_print(out, cur_len,
+				"QPC(0x%x) BT1: 0x%llx\n", qpn, bt1_ba);
 	qpc = (int *)qp_context;
 	for (i = 0; i < (sizeof(*qp_context) >> 2); i += 8) {
-		*desc += sprintf(buff + *desc,
+		hns_roce_v2_sysfs_print(out, cur_len,
 			 "QPC(0x%x): %08x %08x %08x %08x %08x %08x %08x %08x\n",
 			qpn, *qpc, *(qpc + 1), *(qpc + 2),
 			*(qpc + 3), *(qpc + 4), *(qpc + 5),
 			*(qpc + 6), *(qpc + 7));
 		qpc += 8;
 	}
-	memcpy(buf, buff, *desc);
+	*desc += cur_len;
 
 err_mailbox:
 	kfree(qp_context);
 err_cmd:
 	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
-	kfree(buff);
 
 	return ret;
 }
@@ -261,24 +254,18 @@ int hns_roce_v2_query_qpc_stat(struct hns_roce_dev *hr_dev,
 int hns_roce_v2_query_aeqc_stat(struct hns_roce_dev *hr_dev,
 				char *buf, int *desc)
 {
-	struct hns_roce_cmd_mailbox *mailbox;
 	struct hns_roce_eq_context *eq_context;
+	struct hns_roce_cmd_mailbox *mailbox;
+	int aeqn = hr_dev->hr_stat.aeqn;
+	int cur_len = 0;
+	char *out = buf;
+	int i = 0;
 	int *aeqc;
 	int ret;
-	int i = 0;
-	char *buff;
-	int aeqn;
-
-	aeqn = hr_dev->hr_stat.aeqn;
-	buff = kmalloc(1024, GFP_KERNEL);
-	if (!buff)
-		return -ENOMEM;
 
 	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
-	if (IS_ERR(mailbox)) {
-		ret = PTR_ERR(mailbox);
-		goto err_aeqc_buff;
-	}
+	if (IS_ERR(mailbox))
+		return PTR_ERR(mailbox);
 
 	eq_context = kzalloc(sizeof(*eq_context), GFP_KERNEL);
 	if (!eq_context) {
@@ -296,23 +283,20 @@ int hns_roce_v2_query_aeqc_stat(struct hns_roce_dev *hr_dev,
 
 	aeqc = (int *)eq_context;
 	for (i = 0; i < (sizeof(*eq_context) >> 2); i += 8) {
-		*desc += sprintf(buff + *desc,
+		hns_roce_v2_sysfs_print(out, cur_len,
 		 "AEQC(0x%x): %08x %08x %08x %08x %08x %08x %08x %08x\n",
 			aeqn, *aeqc, *(aeqc + 1), *(aeqc + 2),
 			*(aeqc + 3), *(aeqc + 4), *(aeqc + 5),
 			*(aeqc + 6), *(aeqc + 7));
 		aeqc += 8;
 	}
-	memcpy(buf, buff, *desc);
+	*desc += cur_len;
 
 err_mailbox:
 	kfree(eq_context);
 err_context:
 	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
 
-err_aeqc_buff:
-	kfree(buff);
-
 	return ret;
 }
 #define CMD_NUM_QUERY_PKT_CNT	(8)
@@ -330,13 +314,11 @@ int hns_roce_v2_query_pkt_stat(struct hns_roce_dev *hr_dev,
 	struct hns_roce_cmq_desc desc_cnp_tx = {0};
 	struct rdfx_query_cnp_tx_cnt *resp_cnp_tx =
 			(struct rdfx_query_cnp_tx_cnt *)desc_cnp_tx.data;
+	int cur_len = 0;
+	char *out = buf;
 	int status;
 	int i;
-	char *buff;
 
-	buff = kmalloc(1024, GFP_KERNEL);
-	if (!buff)
-		return -ENOMEM;
 	for (i = 0; i < CMD_NUM_QUERY_PKT_CNT; i++) {
 		hns_roce_cmq_setup_basic_desc(&desc[i],
 			HNS_ROCE_OPC_QUEYR_PKT_CNT, true);
@@ -358,7 +340,7 @@ int hns_roce_v2_query_pkt_stat(struct hns_roce_dev *hr_dev,
 	if (status)
 		return status;
 
-	if (hr_dev->pci_dev->revision == 0x21) {
+	if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_B) {
 		hns_roce_cmq_setup_basic_desc(&desc_cnp_rx,
 				HNS_ROCE_OPC_QUEYR_CNP_RX_CNT, true);
 		status = hns_roce_cmq_send(hr_dev, &desc_cnp_rx, 1);
@@ -372,71 +354,69 @@ int hns_roce_v2_query_pkt_stat(struct hns_roce_dev *hr_dev,
 			return status;
 	}
 
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "RX RC PKT : 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[0]->rc_pkt_num, resp_query[1]->rc_pkt_num,
 	 resp_query[2]->rc_pkt_num, resp_query[3]->rc_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "RX UC PKT : 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[0]->uc_pkt_num, resp_query[1]->uc_pkt_num,
 	 resp_query[2]->uc_pkt_num, resp_query[3]->uc_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "RX UD PKT : 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[0]->ud_pkt_num, resp_query[1]->ud_pkt_num,
 	 resp_query[2]->ud_pkt_num, resp_query[3]->ud_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "RX XRC PKT: 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	  resp_query[0]->xrc_pkt_num, resp_query[1]->xrc_pkt_num,
 	  resp_query[2]->xrc_pkt_num, resp_query[3]->xrc_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "RX ALL PKT: 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[0]->total_pkt_num, resp_query[1]->total_pkt_num,
 	 resp_query[2]->total_pkt_num, resp_query[3]->total_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	"RX ERR PKT: 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[0]->error_pkt_num, resp_query[1]->error_pkt_num,
 	 resp_query[2]->error_pkt_num, resp_query[3]->error_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "TX RC PKT : 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[4]->rc_pkt_num, resp_query[5]->rc_pkt_num,
 	 resp_query[6]->rc_pkt_num, resp_query[7]->rc_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "TX UC PKT : 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[4]->uc_pkt_num, resp_query[5]->uc_pkt_num,
 	 resp_query[6]->uc_pkt_num, resp_query[7]->uc_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "TX UD PKT : 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[4]->ud_pkt_num, resp_query[5]->ud_pkt_num,
 	 resp_query[6]->ud_pkt_num, resp_query[7]->ud_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "TX XRC PKT: 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[4]->xrc_pkt_num, resp_query[5]->xrc_pkt_num,
 	 resp_query[6]->xrc_pkt_num, resp_query[7]->xrc_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "TX ALL PKT: 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[4]->total_pkt_num, resp_query[5]->total_pkt_num,
 	 resp_query[6]->total_pkt_num, resp_query[7]->total_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "TX ERR PKT: 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_query[4]->error_pkt_num, resp_query[5]->error_pkt_num,
 	 resp_query[6]->error_pkt_num, resp_query[7]->error_pkt_num);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "CQE       : 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_cqe->port0_cqe, resp_cqe->port1_cqe,
 	 resp_cqe->port2_cqe, resp_cqe->port3_cqe);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 	 "CNP RX    : 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	 resp_cnp_rx->port0_cnp_rx, resp_cnp_rx->port1_cnp_rx,
 	 resp_cnp_rx->port2_cnp_rx, resp_cnp_rx->port3_cnp_rx);
-	*buff_size += sprintf(buff + *buff_size,
+	hns_roce_v2_sysfs_print(out, cur_len,
 		 "CNP TX    : 0x%08x  0x%08x  0x%08x  0x%08x\n",
 	       resp_cnp_tx->port0_cnp_tx, resp_cnp_tx->port1_cnp_tx,
 	       resp_cnp_tx->port2_cnp_tx, resp_cnp_tx->port3_cnp_tx);
 
-	memcpy(buf, buff, *buff_size);
-	kfree(buff);
+	*buff_size += cur_len;
 	return status;
-
 }
 
 int hns_roce_v2_query_ceqc_stat(struct hns_roce_dev *hr_dev,
@@ -444,21 +424,16 @@ int hns_roce_v2_query_ceqc_stat(struct hns_roce_dev *hr_dev,
 {
 	struct hns_roce_cmd_mailbox *mailbox;
 	struct hns_roce_eq_context *eq_context;
+	int ceqn = hr_dev->hr_stat.ceqn;
+	int cur_len = 0;
+	char *out = buf;
 	int *ceqc;
-	int ret;
 	int i = 0;
-	char *buff;
-	int ceqn = hr_dev->hr_stat.ceqn;
+	int ret;
 
-	buff = kmalloc(1024, GFP_KERNEL);
-	if (!buff)
-		return -ENOMEM;
 	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
-
-	if (IS_ERR(mailbox)) {
-		ret = PTR_ERR(mailbox);
-		goto err_ceqc_buff;
-	}
+	if (IS_ERR(mailbox))
+		return PTR_ERR(mailbox);
 
 	eq_context = kzalloc(sizeof(*eq_context), GFP_KERNEL);
 	if (!eq_context) {
@@ -475,22 +450,19 @@ int hns_roce_v2_query_ceqc_stat(struct hns_roce_dev *hr_dev,
 		goto err_mailbox;
 	ceqc = (int *)eq_context;
 	for (i = 0; i < (sizeof(*eq_context) >> 2); i += 8) {
-		*desc += sprintf(buff + *desc,
+		hns_roce_v2_sysfs_print(out, cur_len,
 		 "CEQC(0x%x): %08x %08x %08x %08x %08x %08x %08x %08x\n",
 			ceqn, *ceqc, *(ceqc + 1), *(ceqc + 2),
 			*(ceqc + 3), *(ceqc + 4), *(ceqc + 5),
 			*(ceqc + 6), *(ceqc + 7));
 		ceqc += 8;
 	}
-	memcpy(buf, buff, *desc);
+	*desc += cur_len;
 err_mailbox:
 	kfree(eq_context);
 err_context:
 	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
 
-err_ceqc_buff:
-	kfree(buff);
-
 	return ret;
 }
 
@@ -501,12 +473,10 @@ int hns_roce_v2_query_cmd_stat(struct hns_roce_dev *hr_dev,
 	struct hns_roce_query_mbdb_cnt *resp_cnt =
 				(struct hns_roce_query_mbdb_cnt *)desc_cnt.data;
 	struct hns_roce_cmq_desc desc_dfx;
+	int cur_len = 0;
+	char *out = buf;
 	int status;
-	char *buff;
 
-	buff = kmalloc(1024, GFP_KERNEL);
-	if (!buff)
-		return -ENOMEM;
 	hns_roce_cmq_setup_basic_desc(&desc_cnt,
 			HNS_ROCE_OPC_QUEYR_MBDB_CNT, true);
 	status = hns_roce_cmq_send(hr_dev, &desc_cnt, 1);
@@ -519,21 +489,19 @@ int hns_roce_v2_query_cmd_stat(struct hns_roce_dev *hr_dev,
 	if (status)
 		return status;
 
-
-	*desc += sprintf(buff + *desc, "MB ISSUE CNT   : 0x%08x\n",
-	       resp_cnt->mailbox_issue_cnt);
-	*desc += sprintf(buff + *desc, "MB EXEC CNT    : 0x%08x\n",
-	       resp_cnt->mailbox_exe_cnt);
-	*desc += sprintf(buff + *desc, "DB ISSUE CNT   : 0x%08x\n",
-	       resp_cnt->doorbell_issue_cnt);
-	*desc += sprintf(buff + *desc, "DB EXEC CNT    : 0x%08x\n",
-	       resp_cnt->doorbell_exe_cnt);
-	*desc += sprintf(buff + *desc, "EQDB ISSUE CNT : 0x%08x\n",
-	       resp_cnt->eq_doorbell_issue_cnt);
-	*desc += sprintf(buff + *desc, "EQDB EXEC CNT  : 0x%08x\n",
-	       resp_cnt->eq_doorbell_exe_cnt);
-	memcpy(buf, buff, *desc);
-	kfree(buff);
+	hns_roce_v2_sysfs_print(out, cur_len, "MB ISSUE CNT   : 0x%08x\n",
+				resp_cnt->mailbox_issue_cnt);
+	hns_roce_v2_sysfs_print(out, cur_len, "MB EXEC CNT    : 0x%08x\n",
+				resp_cnt->mailbox_exe_cnt);
+	hns_roce_v2_sysfs_print(out, cur_len, "DB ISSUE CNT   : 0x%08x\n",
+				resp_cnt->doorbell_issue_cnt);
+	hns_roce_v2_sysfs_print(out, cur_len, "DB EXEC CNT    : 0x%08x\n",
+				resp_cnt->doorbell_exe_cnt);
+	hns_roce_v2_sysfs_print(out, cur_len, "EQDB ISSUE CNT : 0x%08x\n",
+				resp_cnt->eq_doorbell_issue_cnt);
+	hns_roce_v2_sysfs_print(out, cur_len, "EQDB EXEC CNT  : 0x%08x\n",
+				resp_cnt->eq_doorbell_exe_cnt);
+	*desc += cur_len;
 	return status;
 }
 
@@ -583,11 +551,13 @@ int hns_roce_v2_query_cqc_stat(struct hns_roce_dev *hr_dev,
 				      char *buf, int *desc)
 {
 	struct hns_roce_v2_cq_context *cq_context;
+	int cqn = hr_dev->hr_stat.cqn;
+	int cur_len = 0;
+	char *out = buf;
 	u64 bt0_ba = 0;
 	u64 bt1_ba = 0;
 	int *cqc;
 	int i, ret;
-	int cqn = hr_dev->hr_stat.cqn;
 
 	cq_context = kzalloc(sizeof(*cq_context), GFP_KERNEL);
 	if (!cq_context)
@@ -596,18 +566,22 @@ int hns_roce_v2_query_cqc_stat(struct hns_roce_dev *hr_dev,
 	ret = hns_roce_v2_query_cqc(hr_dev, &bt0_ba, &bt1_ba, cqn, cq_context);
 	if (ret)
 		goto out;
-	*desc += sprintf(buf + *desc, "CQC(0x%x) BT0: 0x%llx\n", cqn, bt0_ba);
-	*desc += sprintf(buf + *desc, "CQC(0x%x) BT1: 0x%llx\n", cqn, bt1_ba);
+
+	hns_roce_v2_sysfs_print(out, cur_len,
+				"CQC(0x%x) BT0: 0x%llx\n", cqn, bt0_ba);
+	hns_roce_v2_sysfs_print(out, cur_len,
+				"CQC(0x%x) BT1: 0x%llx\n", cqn, bt1_ba);
 
 	cqc = (int *)cq_context;
 	for (i = 0; i < (sizeof(*cq_context) >> 2); i += 8) {
-		*desc += sprintf(buf + *desc,
+		hns_roce_v2_sysfs_print(out, cur_len,
 			 "CQC(0x%x): %08x %08x %08x %08x %08x %08x %08x %08x\n",
 			cqn, *cqc, *(cqc + 1), *(cqc + 2),
 			*(cqc + 3), *(cqc + 4), *(cqc + 5),
 			*(cqc + 6), *(cqc + 7));
 		cqc += 8;
 	}
+	*desc += cur_len;
 out:
 	kfree(cq_context);
 	return ret;

drivers/infiniband/hw/hns/hns_roce_hw_v1.c

@@ -825,7 +825,7 @@ static int hns_roce_v1_rsv_lp_qp(struct hns_roce_dev *hr_dev)
 		attr.dest_qp_num	= hr_qp->qpn;
 		memcpy(rdma_ah_retrieve_dmac(&attr.ah_attr),
 		       hr_dev->dev_addr[port],
-		       MAC_ADDR_OCTET_NUM);
+		       ETH_ALEN);
 
 		memcpy(&dgid.raw, &subnet_prefix, sizeof(u64));
 		memcpy(&dgid.raw[8], hr_dev->dev_addr[port], 3);
@@ -2482,7 +2482,7 @@ int hns_roce_v1_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
 		return ret;
 }
 
-static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
+static void hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
 				 struct hns_roce_hem_table *table, int obj,
 				 int step_idx)
 {
@@ -2513,9 +2513,9 @@ static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
 		break;
 	case HEM_TYPE_SRQC:
 		dev_dbg(dev, "HEM_TYPE_SRQC not support.\n");
-		return -EINVAL;
+		return;
 	default:
-		return 0;
+		return;
 	}
 	roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M,
 		ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj);
@@ -2533,7 +2533,7 @@ static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
 				dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n");
 				spin_unlock_irqrestore(&hr_dev->bt_cmd_lock,
 					flags);
-				return -EBUSY;
+				return;
 			}
 		} else {
 			break;
@@ -2548,7 +2548,7 @@ static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev,
 
 	spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags);
 
-	return 0;
+	return;
 }
 
 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev,

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

@@ -86,6 +86,7 @@
 #define HNS_ROCE_V2_SRQC_ENTRY_SZ		64
 #define HNS_ROCE_V2_MTPT_ENTRY_SZ		64
 #define HNS_ROCE_V2_MTT_ENTRY_SZ		64
+#define HNS_ROCE_V2_IDX_ENTRY_SZ		4
 #define HNS_ROCE_V2_CQE_ENTRY_SIZE		32
 #define HNS_ROCE_V2_SCC_CTX_ENTRY_SZ		32
 #define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ		4096
@@ -100,6 +101,8 @@
 /* Time out for hardware to complete reset */
 #define HNS_ROCE_V2_HW_RST_TIMEOUT		1000
 
+#define HNS_ROCE_V2_HW_RST_COMPLETION_WAIT	20
+
 /* The longest time for software reset process in NIC subsystem, if a timeout
  * occurs, it indicates that the network subsystem has encountered a serious
  * error and cannot be recovered from the reset processing.
@@ -114,6 +117,7 @@
 #define HNS_ROCE_PBL_HOP_NUM			2
 #define HNS_ROCE_EQE_HOP_NUM			2
 #define HNS_ROCE_IDX_HOP_NUM			1
+#define HNS_ROCE_MEM_PAGE_SUPPORT_8K		2
 
 #define HNS_ROCE_V2_GID_INDEX_NUM(d)		(d ? (8) : (256))
 
@@ -401,10 +405,10 @@ struct hns_roce_srq_context {
 	__le32	byte_8_limit_wl;
 	__le32	byte_12_xrcd;
 	__le32	byte_16_pi_ci;
-	__le32	wqe_bt_ba;
+	__le32	wqe_bt_ba; /* Aligned with 8B, so store [:3] */
 	__le32	byte_24_wqe_bt_ba;
 	__le32	byte_28_rqws_pd;
-	__le32	idx_bt_ba;
+	__le32	idx_bt_ba; /* Aligned with 8B, so store [:3] */
 	__le32	rsv_idx_bt_ba;
 	__le32	idx_cur_blk_addr;
 	__le32	byte_44_idxbufpgsz_addr;
@@ -499,7 +503,7 @@ enum hns_roce_v2_qp_state {
 
 struct hns_roce_v2_qp_context {
 	__le32	byte_4_sqpn_tst;
-	__le32	wqe_sge_ba;
+	__le32	wqe_sge_ba; /* Aligned with 8B, so store [:3] */
 	__le32	byte_12_sq_hop;
 	__le32	byte_16_buf_ba_pg_sz;
 	__le32	byte_20_smac_sgid_idx;
@@ -527,7 +531,7 @@ struct hns_roce_v2_qp_context {
 	__le32	rx_rkey_pkt_info;
 	__le64	rx_va;
 	__le32	byte_132_trrl;
-	__le32	trrl_ba;
+	__le32	trrl_ba; /* Aligned with 64B, but store [:4] */
 	__le32	byte_140_raq;
 	__le32	byte_144_raq;
 	__le32	byte_148_raq;
@@ -544,7 +548,7 @@ struct hns_roce_v2_qp_context {
 	__le32	byte_192_ext_sge;
 	__le32	byte_196_sq_psn;
 	__le32	byte_200_sq_max;
-	__le32	irrl_ba;
+	__le32	irrl_ba; /* Aligned with 64B, so store [:6] */
 	__le32	byte_208_irrl;
 	__le32	byte_212_lsn;
 	__le32	sq_timer;
@@ -927,6 +931,10 @@ struct hns_roce_v2_qp_context {
 #define	V2_QPC_BYTE_256_SQ_FLUSH_IDX_S 16
 #define V2_QPC_BYTE_256_SQ_FLUSH_IDX_M GENMASK(31, 16)
 
+#define	V2_QP_RWE_S 1 /* rdma write enable */
+#define	V2_QP_RRE_S 2 /* rdma read enable */
+#define	V2_QP_ATE_S 3 /* rdma atomic enable */
+
 struct hns_roce_v2_cqe {
 	__le32	byte_4;
 	union {
@@ -1003,7 +1011,7 @@ struct hns_roce_v2_mpt_entry {
 	__le32	va_l;
 	__le32	va_h;
 	__le32	pbl_size;
-	__le32	pbl_ba_l;
+	__le32	pbl_ba_l; /* Aligned with 8B, so store [:3] */
 	__le32	byte_48_mode_ba;
 	__le32	pa0_l;
 	__le32	byte_56_pa0_h;
@@ -1284,6 +1292,18 @@ struct hns_roce_pf_func_num {
 #define FUNC_CLEAR_RST_FUN_DONE_S 0
 
 #define HNS_ROCE_V2_FUNC_CLEAR_TIMEOUT_MSECS	(512 * 100)
+#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL	40
+#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT	20
+
+#define QUERY_PF_RES_CMDQ_DESC_NUM			2
+#define QUERY_PF_TIMER_RES_CMDQ_DESC_NUM		2
+#define ALLOC_VF_RES_CMDQ_DESC_NUM			2
+#define CONFIG_LLM_CMDQ_DESC_NUM			2
+
+/* TSQ and RAQ each account for 4B */
+#define QP_EX_DB_SIZE					8
+#define CQ_EX_DB_SIZE					4
+#define TIMEOUT_POLL_QUEUE_NUM				4
 
 struct hns_roce_cfg_llm_a {
 	__le32 base_addr_l;
@@ -1620,6 +1640,9 @@ struct hns_roce_cmq_desc {
 #define HNS_ROCE_HW_RUN_BIT_SHIFT	31
 #define HNS_ROCE_HW_MB_STATUS_MASK	0xFF
 
+#define HNS_ROCE_MB_TAG_S		8
+#define HNS_ROCE_MB_EVENT_EN_S		16
+
 struct hns_roce_v2_cmq_ring {
 	dma_addr_t desc_dma_addr;
 	struct hns_roce_cmq_desc *desc;
@@ -1654,7 +1677,7 @@ struct hns_roce_link_table {
 };
 
 struct hns_roce_link_table_entry {
-	u32 blk_ba0;
+	u32 blk_ba0; /* Aligned with 4KB regardless of kernel page size */
 	u32 blk_ba1_nxt_ptr;
 };
 #define HNS_ROCE_LINK_TABLE_BA1_S 0
@@ -1906,6 +1929,15 @@ struct rdfx_query_cnp_tx_cnt {
 	__le32 rsv[2];
 };
 
+#define HNS_ROCE_V2_SYSFS_BUF_MAX_SIZE		1024
+#define hns_roce_v2_sysfs_print(out, cur, fmt, ...) do {\
+		if (cur < HNS_ROCE_V2_SYSFS_BUF_MAX_SIZE) { \
+			cur += snprintf(out + cur, \
+				HNS_ROCE_V2_SYSFS_BUF_MAX_SIZE - cur,\
+				fmt, ##__VA_ARGS__); \
+		} \
+	} while (0)
+
 int hns_roce_v2_query_mpt_stat(struct hns_roce_dev *hr_dev,
 				char *buf, int *desc);
 int hns_roce_v2_query_srqc_stat(struct hns_roce_dev *hr_dev,
@@ -1936,6 +1968,7 @@ void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc,
 				bool is_read);
 int hns_roce_cmq_send(struct hns_roce_dev *hr_dev,
 				struct hns_roce_cmq_desc *desc, int num);
+
 #ifdef CONFIG_INFINIBAND_HNS_DFX
 #ifdef CONFIG_KERNEL_419
 void rdfx_cp_sq_wqe_buf(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,

drivers/infiniband/hw/hns/hns_roce_main.c

@@ -77,10 +77,10 @@ static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
 	u8 phy_port;
 	u32 i = 0;
 
-	if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
+	if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
 		return 0;
 
-	for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
+	for (i = 0; i < ETH_ALEN; i++)
 		hr_dev->dev_addr[port][i] = addr[i];
 
 	phy_port = hr_dev->iboe.phy_port[port];
@@ -114,6 +114,11 @@ static int hns_roce_add_gid(const union ib_gid *gid,
 	ret = hr_dev->hw->set_gid(hr_dev, port, attr->index,
 				  (union ib_gid *)gid, attr);
 #endif
+
+	if (ret)
+		dev_err(hr_dev->dev, "set gid failed(%d), index = %d", ret,
+			attr->index);
+
 	spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 
 	return ret;
@@ -127,12 +132,19 @@ static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
 	unsigned long flags;
 	int ret;
 
-	if (port >= hr_dev->caps.num_ports)
+	if (port >= hr_dev->caps.num_ports) {
+		dev_err(hr_dev->dev,
+			"Port num %d id large than max port num %d.\n",
+			port, hr_dev->caps.num_ports);
 		return -EINVAL;
+	}
 
 	spin_lock_irqsave(&hr_dev->iboe.lock, flags);
 
 	ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
+	if (ret)
+		dev_warn(hr_dev->dev, "del gid failed(%d), index = %d", ret,
+			 attr->index);
 
 	spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 
@@ -161,6 +173,9 @@ static int hns_roce_add_gid(struct ib_device *device, u8 port_num,
 
 	ret = hr_dev->hw->set_gid(hr_dev, port, index, (union ib_gid *)gid,
 				   attr);
+	if (ret)
+		dev_err(hr_dev->dev, "set gid failed(%d), index = %d",
+			ret, index);
 
 	spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 
@@ -179,12 +194,19 @@ static int hns_roce_del_gid(struct ib_device *device, u8 port_num,
 
 	rdfx_func_cnt(hr_dev, RDFX_FUNC_DEL_GID);
 
-	if (port >= hr_dev->caps.num_ports)
+	if (port >= hr_dev->caps.num_ports) {
+		dev_err(hr_dev->dev,
+			"Port num %d id large than max port num %d.\n",
+			port, hr_dev->caps.num_ports);
 		return -EINVAL;
+	}
 
 	spin_lock_irqsave(&hr_dev->iboe.lock, flags);
 
 	ret = hr_dev->hw->set_gid(hr_dev, port, index, &zgid, &zattr);
+	if (ret)
+		dev_warn(hr_dev->dev, "del gid failed(%d), index = %d", ret,
+			 index);
 
 	spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 
@@ -211,6 +233,9 @@ static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
 	case NETDEV_REGISTER:
 	case NETDEV_CHANGEADDR:
 		ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
+		if (ret)
+			dev_err(dev, "set mac failed(%d), event = %ld\n",
+				ret, event);
 		break;
 	case NETDEV_DOWN:
 		/*
@@ -229,10 +254,10 @@ static int hns_roce_netdev_event(struct notifier_block *self,
 				 unsigned long event, void *ptr)
 {
 	struct net_device *dev = netdev_notifier_info_to_dev(ptr);
-	struct hns_roce_ib_iboe *iboe = NULL;
-	struct hns_roce_dev *hr_dev = NULL;
-	u8 port = 0;
-	int ret = 0;
+	struct hns_roce_ib_iboe *iboe;
+	struct hns_roce_dev *hr_dev;
+	u8 port;
+	int ret;
 
 	hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
 	iboe = &hr_dev->iboe;
@@ -260,8 +285,11 @@ static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
 					    hr_dev->caps.max_mtu);
 		ret = hns_roce_set_mac(hr_dev, i,
 				       hr_dev->iboe.netdevs[i]->dev_addr);
-		if (ret)
+		if (ret) {
+			dev_err(hr_dev->dev, "Port %d set mac failed(%d)\n",
+				i, ret);
 			return ret;
+		}
 	}
 
 	return 0;
@@ -361,7 +389,11 @@ static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
 
 	rdfx_func_cnt(hr_dev, RDFX_FUNC_QUERY_PORT);
 
-	assert(port_num > 0);
+	if (port_num < 1) {
+		dev_err(dev, "invalid port num!\n");
+		return -EINVAL;
+	}
+
 	port = port_num - 1;
 
 	/* props being zeroed by the caller, avoid zeroing it here */
@@ -389,7 +421,8 @@ static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
 	props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
 	props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
 			IB_PORT_ACTIVE : IB_PORT_DOWN;
-	props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
+	props->phys_state = (props->state == IB_PORT_ACTIVE) ?
+			     HNS_ROCE_PHY_LINKUP : HNS_ROCE_PHY_DISABLED;
 
 	spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 
@@ -452,13 +485,15 @@ static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
 static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
 						   struct ib_udata *udata)
 {
-	int ret = 0;
+	int ret;
 	struct hns_roce_ucontext *context;
 	struct hns_roce_ib_alloc_ucontext_resp resp = {};
 	struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 
-	if (!hr_dev->active)
+	if (!hr_dev->active) {
+		dev_err(hr_dev->dev, "alloc uncontext failed, hr_dev is not active\n");
 		return ERR_PTR(-EAGAIN);
+	}
 
 	rdfx_func_cnt(hr_dev, RDFX_FUNC_ALLOC_UCONTEXT);
 
@@ -558,8 +593,10 @@ static int hns_roce_mmap(struct ib_ucontext *context,
 
 	rdfx_func_cnt(hr_dev, RDFX_FUNC_MMAP);
 
-	if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
+	if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0) {
+		dev_err(hr_dev->dev, "mmap failed, unexpected vm area size.\n");
 		return -EINVAL;
+	}
 
 	if (vma->vm_pgoff == 0) {
 		vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
@@ -574,8 +611,10 @@ static int hns_roce_mmap(struct ib_ucontext *context,
 				       hr_dev->uar2_size,
 				       vma->vm_page_prot))
 			return -EAGAIN;
-	} else
+	} else {
+		dev_err(hr_dev->dev, "mmap failed, vm_pgoff is unsupported.\n");
 		return -EINVAL;
+	}
 
 	return hns_roce_set_vma_data(vma, to_hr_ucontext(context));
 }
@@ -589,8 +628,11 @@ static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
 	rdfx_func_cnt(to_hr_dev(ib_dev), RDFX_FUNC_PORT_IMMUTABLE);
 
 	ret = ib_query_port(ib_dev, port_num, &attr);
-	if (ret)
+	if (ret) {
+		dev_err(to_hr_dev(ib_dev)->dev, "ib_query_port failed(%d)!\n",
+			ret);
 		return ret;
+	}
 
 	immutable->pkey_tbl_len = attr.pkey_tbl_len;
 	immutable->gid_tbl_len = attr.gid_tbl_len;
@@ -633,10 +675,10 @@ static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
 
 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
 {
-	int ret;
-	struct hns_roce_ib_iboe *iboe = NULL;
-	struct ib_device *ib_dev = NULL;
 	struct device *dev = hr_dev->dev;
+	struct hns_roce_ib_iboe *iboe;
+	struct ib_device *ib_dev;
+	int ret;
 
 	iboe = &hr_dev->iboe;
 	spin_lock_init(&iboe->lock);
@@ -772,7 +814,7 @@ static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
 
 	ret = hns_roce_setup_mtu_mac(hr_dev);
 	if (ret) {
-		dev_err(dev, "setup_mtu_mac failed!\n");
+		dev_err(dev, "setup_mtu_mac failed, ret = %d\n", ret);
 		goto error_failed_setup_mtu_mac;
 	}
 
@@ -1014,45 +1056,46 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
 
 	ret = hns_roce_init_uar_table(hr_dev);
 	if (ret) {
-		dev_err(dev, "Failed to initialize uar table. aborting\n");
+		dev_err(dev, "Failed to init uar table(%d). aborting\n", ret);
 		return ret;
 	}
 
 	ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
 	if (ret) {
-		dev_err(dev, "Failed to allocate priv_uar.\n");
+		dev_err(dev, "Failed to allocate priv_uar(%d).\n", ret);
 		goto err_uar_table_free;
 	}
 
 	ret = hns_roce_init_pd_table(hr_dev);
 	if (ret) {
-		dev_err(dev, "Failed to init protected domain table.\n");
+		dev_err(dev, "Failed to init pd table(%d).\n", ret);
 		goto err_uar_alloc_free;
 	}
 
 	if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC) {
 		ret = hns_roce_init_xrcd_table(hr_dev);
 		if (ret) {
-			dev_err(dev, "Failed to init protected domain table.\n");
+			dev_err(dev, "Failed to init xrcd table(%d).\n",
+				ret);
 			goto err_pd_table_free;
 		}
 	}
 
 	ret = hns_roce_init_mr_table(hr_dev);
 	if (ret) {
-		dev_err(dev, "Failed to init memory region table.\n");
+		dev_err(dev, "Failed to init mr table(%d).\n", ret);
 		goto err_xrcd_table_free;
 	}
 
 	ret = hns_roce_init_cq_table(hr_dev);
 	if (ret) {
-		dev_err(dev, "Failed to init completion queue table.\n");
+		dev_err(dev, "Failed to init cq table(%d).\n", ret);
 		goto err_mr_table_free;
 	}
 
 	ret = hns_roce_init_qp_table(hr_dev);
 	if (ret) {
-		dev_err(dev, "Failed to init queue pair table.\n");
+		dev_err(dev, "Failed to init qp table(%d).\n", ret);
 		goto err_cq_table_free;
 	}
 
@@ -1060,7 +1103,7 @@ static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
 		ret = hns_roce_init_srq_table(hr_dev);
 		if (ret) {
 			dev_err(dev,
-				"Failed to init share receive queue table.\n");
+				"Failed to init srq table(%d).\n", ret);
 			goto err_qp_table_free;
 		}
 	}
@@ -1115,60 +1158,62 @@ int hns_roce_init(struct hns_roce_dev *hr_dev)
 
 	ret = hns_roce_reset(hr_dev);
 	if (ret) {
-		dev_err(dev, "Reset RoCE engine failed!\n");
+		dev_err(dev, "Reset RoCE engine failed(%d)!\n", ret);
 		return ret;
 	}
 
 	if (hr_dev->hw->cmq_init) {
 		ret = hr_dev->hw->cmq_init(hr_dev);
 		if (ret) {
-			dev_err(dev, "Init RoCE Command Queue failed!\n");
+			dev_err(dev, "Init RoCE cmq failed(%d)!\n", ret);
 			goto error_failed_cmq_init;
 		}
 	}
 
 	ret = hr_dev->hw->hw_profile(hr_dev);
 	if (ret) {
-		dev_err(dev, "Get RoCE engine profile failed!\n");
+		dev_err(dev, "Get RoCE engine profile failed(%d)!\n", ret);
 		goto error_failed_cmd_init;
 	}
 
 	ret = hns_roce_cmd_init(hr_dev);
 	if (ret) {
-		dev_err(dev, "cmd init failed!\n");
+		dev_err(dev, "Cmd init failed(%d)!\n", ret);
 		goto error_failed_cmd_init;
 	}
 
 	ret = hr_dev->hw->init_eq(hr_dev);
 	if (ret) {
-		dev_err(dev, "eq init failed!\n");
+		dev_err(dev, "Eq init failed(%d)!\n", ret);
 		goto error_failed_eq_table;
 	}
 
 	if (hr_dev->cmd_mod) {
 		ret = hns_roce_cmd_use_events(hr_dev);
 		if (ret) {
-			dev_err(dev, "Switch to event-driven cmd failed!\n");
+			dev_err(dev, "Switch to event-driven cmd failed(%d)!\n",
+				ret);
 			goto error_failed_use_event;
 		}
 	}
 
 	ret = hns_roce_init_hem(hr_dev);
 	if (ret) {
-		dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
+		dev_err(dev, "Init HEM(Hardware Entry Memory) failed(%d)!\n",
+			ret);
 		goto error_failed_init_hem;
 	}
 
 	ret = hns_roce_setup_hca(hr_dev);
 	if (ret) {
-		dev_err(dev, "setup hca failed!\n");
+		dev_err(dev, "Setup hca failed(%d)!\n", ret);
 		goto error_failed_setup_hca;
 	}
 
 	if (hr_dev->hw->hw_init) {
 		ret = hr_dev->hw->hw_init(hr_dev);
 		if (ret) {
-			dev_err(dev, "hw_init failed!\n");
+			dev_err(dev, "Hw_init failed!\n");
 			goto error_failed_engine_init;
 		}
 	}

drivers/infiniband/hw/hns/hns_roce_mr.c

@@ -319,11 +319,11 @@ static void hns_roce_loop_free(struct hns_roce_dev *hr_dev,
 			dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i],
 					  mr->pbl_l1_dma_addr[i]);
 
-			for (j = 0; j < pbl_bt_sz / 8; j++) {
+			for (j = 0; j < pbl_bt_sz / BA_BYTE_LEN; j++) {
 				if (i == loop_i && j >= loop_j)
 					break;
 
-				bt_idx = i * pbl_bt_sz / 8 + j;
+				bt_idx = i * pbl_bt_sz / BA_BYTE_LEN + j;
 				dma_free_coherent(dev, pbl_bt_sz,
 						  mr->pbl_bt_l2[bt_idx],
 						  mr->pbl_l2_dma_addr[bt_idx]);
@@ -334,8 +334,8 @@ static void hns_roce_loop_free(struct hns_roce_dev *hr_dev,
 			dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i],
 					  mr->pbl_l1_dma_addr[i]);
 
-			for (j = 0; j < pbl_bt_sz / 8; j++) {
-				bt_idx = i * pbl_bt_sz / 8 + j;
+			for (j = 0; j < pbl_bt_sz / BA_BYTE_LEN; j++) {
+				bt_idx = i * pbl_bt_sz / BA_BYTE_LEN + j;
 				dma_free_coherent(dev, pbl_bt_sz,
 						  mr->pbl_bt_l2[bt_idx],
 						  mr->pbl_l2_dma_addr[bt_idx]);
@@ -360,12 +360,12 @@ static int pbl_1hop_alloc(struct hns_roce_dev *hr_dev, int npages,
 {
 	struct device *dev = hr_dev->dev;
 
-	if (npages > pbl_bt_sz / 8) {
+	if (npages > pbl_bt_sz / BA_BYTE_LEN) {
 		dev_err(dev, "npages %d is larger than buf_pg_sz!",
 			npages);
 		return -EINVAL;
 	}
-	mr->pbl_buf = dma_alloc_coherent(dev, npages * 8,
+	mr->pbl_buf = dma_alloc_coherent(dev, npages * BA_BYTE_LEN,
 					 &(mr->pbl_dma_addr),
 					 GFP_KERNEL);
 	if (!mr->pbl_buf)
@@ -385,21 +385,21 @@ static int pbl_2hop_alloc(struct hns_roce_dev *hr_dev, int npages,
 			       struct hns_roce_mr *mr, u32 pbl_bt_sz)
 {
 	struct device *dev = hr_dev->dev;
-	int npages_allocated;
+	int npages_alloced;
 	u64 pbl_last_bt_num;
 	u64 pbl_bt_cnt = 0;
 	u64 size;
 	int i;
 
-	pbl_last_bt_num = (npages + pbl_bt_sz / 8 - 1) / (pbl_bt_sz / 8);
+	pbl_last_bt_num = DIV_ROUND_UP(npages, pbl_bt_sz / BA_BYTE_LEN);
 
 	/* alloc L1 BT */
-	for (i = 0; i < pbl_bt_sz / 8; i++) {
+	for (i = 0; i < pbl_bt_sz / BA_BYTE_LEN; i++) {
 		if (pbl_bt_cnt + 1 < pbl_last_bt_num) {
 			size = pbl_bt_sz;
 		} else {
-			npages_allocated = i * (pbl_bt_sz / 8);
-			size = (npages - npages_allocated) * 8;
+			npages_alloced = i * (pbl_bt_sz / BA_BYTE_LEN);
+			size = (npages - npages_alloced) * BA_BYTE_LEN;
 		}
 		mr->pbl_bt_l1[i] = dma_alloc_coherent(dev, size,
 					    &(mr->pbl_l1_dma_addr[i]),
@@ -426,7 +426,7 @@ static int pbl_3hop_alloc(struct hns_roce_dev *hr_dev, int npages,
 {
 	struct device *dev = hr_dev->dev;
 	int mr_alloc_done = 0;
-	int npages_allocated;
+	int npages_alloced;
 	u64 pbl_last_bt_num;
 	u64 pbl_bt_cnt = 0;
 	u64 bt_idx;
@@ -434,7 +434,7 @@ static int pbl_3hop_alloc(struct hns_roce_dev *hr_dev, int npages,
 	int i;
 	int j = 0;
 
-	pbl_last_bt_num = (npages + pbl_bt_sz / 8 - 1) / (pbl_bt_sz / 8);
+	pbl_last_bt_num = DIV_ROUND_UP(npages, pbl_bt_sz / BA_BYTE_LEN);
 
 	mr->pbl_l2_dma_addr = kcalloc(pbl_last_bt_num,
 				      sizeof(*mr->pbl_l2_dma_addr),
@@ -449,7 +449,7 @@ static int pbl_3hop_alloc(struct hns_roce_dev *hr_dev, int npages,
 		goto err_kcalloc_bt_l2;
 
 	/* alloc L1, L2 BT */
-	for (i = 0; i < pbl_bt_sz / 8; i++) {
+	for (i = 0; i < pbl_bt_sz / BA_BYTE_LEN; i++) {
 		mr->pbl_bt_l1[i] = dma_alloc_coherent(dev, pbl_bt_sz,
 					    &(mr->pbl_l1_dma_addr[i]),
 					    GFP_KERNEL);
@@ -460,15 +460,15 @@ static int pbl_3hop_alloc(struct hns_roce_dev *hr_dev, int npages,
 
 		*(mr->pbl_bt_l0 + i) = mr->pbl_l1_dma_addr[i];
 
-		for (j = 0; j < pbl_bt_sz / 8; j++) {
-			bt_idx = i * pbl_bt_sz / 8 + j;
+		for (j = 0; j < pbl_bt_sz / BA_BYTE_LEN; j++) {
+			bt_idx = i * pbl_bt_sz / BA_BYTE_LEN + j;
 
 			if (pbl_bt_cnt + 1 < pbl_last_bt_num) {
 				size = pbl_bt_sz;
 			} else {
-				npages_allocated = bt_idx *
-						   (pbl_bt_sz / 8);
-				size = (npages - npages_allocated) * 8;
+				npages_alloced = bt_idx *
+						 (pbl_bt_sz / BA_BYTE_LEN);
+			       size = (npages - npages_alloced) * BA_BYTE_LEN;
 			}
 			mr->pbl_bt_l2[bt_idx] = dma_alloc_coherent(
 				      dev, size,
@@ -525,17 +525,16 @@ static int hns_roce_mhop_alloc(struct hns_roce_dev *hr_dev, int npages,
 	if (mhop_num == HNS_ROCE_HOP_NUM_0)
 		return 0;
 
-	/* hop_num = 1 */
 	if (mhop_num == 1)
 		return pbl_1hop_alloc(hr_dev, npages, mr, pbl_bt_sz);
 
-	mr->pbl_l1_dma_addr = kcalloc(pbl_bt_sz / 8,
+	mr->pbl_l1_dma_addr = kcalloc(pbl_bt_sz / BA_BYTE_LEN,
 				      sizeof(*mr->pbl_l1_dma_addr),
 				      GFP_KERNEL);
 	if (!mr->pbl_l1_dma_addr)
 		return -ENOMEM;
 
-	mr->pbl_bt_l1 = kcalloc(pbl_bt_sz / 8, sizeof(*mr->pbl_bt_l1),
+	mr->pbl_bt_l1 = kcalloc(pbl_bt_sz / BA_BYTE_LEN, sizeof(*mr->pbl_bt_l1),
 				GFP_KERNEL);
 	if (!mr->pbl_bt_l1)
 		goto err_kcalloc_bt_l1;
@@ -583,7 +582,7 @@ static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
 {
 	struct device *dev = hr_dev->dev;
 	unsigned long index = 0;
-	int ret = 0;
+	int ret;
 
 	/* Allocate a key for mr from mr_table */
 	ret = hns_roce_bitmap_alloc(&hr_dev->mr_table.mtpt_bitmap, &index);
@@ -609,7 +608,8 @@ static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
 		mr->pbl_l0_dma_addr = 0;
 	} else {
 		if (!hr_dev->caps.pbl_hop_num) {
-			mr->pbl_buf = dma_alloc_coherent(dev, npages * 8,
+			mr->pbl_buf = dma_alloc_coherent(dev,
+							 npages * BA_BYTE_LEN,
 							 &(mr->pbl_dma_addr),
 							 GFP_KERNEL);
 			if (!mr->pbl_buf)
@@ -626,7 +626,7 @@ static void hns_roce_mhop_free(struct hns_roce_dev *hr_dev,
 			       struct hns_roce_mr *mr)
 {
 	struct device *dev = hr_dev->dev;
-	int npages_allocated;
+	int npages_alloced;
 	int npages;
 	int i, j;
 	u32 pbl_bt_sz;
@@ -640,9 +640,8 @@ static void hns_roce_mhop_free(struct hns_roce_dev *hr_dev,
 	if (mhop_num == HNS_ROCE_HOP_NUM_0)
 		return;
 
-	/* hop_num = 1 */
 	if (mhop_num == 1) {
-		dma_free_coherent(dev, (unsigned int)(npages * 8),
+		dma_free_coherent(dev, (unsigned int)(npages * BA_BYTE_LEN),
 				  mr->pbl_buf, mr->pbl_dma_addr);
 		return;
 	}
@@ -653,12 +652,11 @@ static void hns_roce_mhop_free(struct hns_roce_dev *hr_dev,
 	if (mhop_num == 2) {
 		for (i = 0; i < mr->l0_chunk_last_num; i++) {
 			if (i == mr->l0_chunk_last_num - 1) {
-				npages_allocated = i * (pbl_bt_sz / 8);
+				npages_alloced = i * (pbl_bt_sz / BA_BYTE_LEN);
 
 				dma_free_coherent(dev,
-					      (npages - npages_allocated) * 8,
-					      mr->pbl_bt_l1[i],
-					      mr->pbl_l1_dma_addr[i]);
+					(npages - npages_alloced) * BA_BYTE_LEN,
+				      mr->pbl_bt_l1[i], mr->pbl_l1_dma_addr[i]);
 
 				break;
 			}
@@ -671,16 +669,16 @@ static void hns_roce_mhop_free(struct hns_roce_dev *hr_dev,
 			dma_free_coherent(dev, pbl_bt_sz, mr->pbl_bt_l1[i],
 					  mr->pbl_l1_dma_addr[i]);
 
-			for (j = 0; j < pbl_bt_sz / 8; j++) {
-				bt_idx = i * (pbl_bt_sz / 8) + j;
+			for (j = 0; j < pbl_bt_sz / BA_BYTE_LEN; j++) {
+				bt_idx = i * (pbl_bt_sz / BA_BYTE_LEN) + j;
 
 				if ((i == mr->l0_chunk_last_num - 1)
 				    && j == mr->l1_chunk_last_num - 1) {
-					npages_allocated = bt_idx *
-							   (pbl_bt_sz / 8);
+					npages_alloced = bt_idx *
+						      (pbl_bt_sz / BA_BYTE_LEN);
 
 					dma_free_coherent(dev,
-					      (npages - npages_allocated) * 8,
+					(npages - npages_alloced) * BA_BYTE_LEN,
 					      mr->pbl_bt_l2[bt_idx],
 					      mr->pbl_l2_dma_addr[bt_idx]);
 
@@ -725,7 +723,8 @@ static void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
 			npages = ib_umem_page_count(mr->umem);
 
 		if (!hr_dev->caps.pbl_hop_num)
-			dma_free_coherent(dev, (unsigned int)(npages * 8),
+			dma_free_coherent(dev,
+					  (unsigned int)(npages * BA_BYTE_LEN),
 					  mr->pbl_buf, mr->pbl_dma_addr);
 		else
 			hns_roce_mhop_free(hr_dev, mr);
@@ -750,9 +749,11 @@ static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
 
 	/* Prepare HEM entry memory */
 	ret = hns_roce_table_get(hr_dev, &mr_table->mtpt_table, mtpt_idx);
-	if (ret)
+	if (ret) {
+		dev_err(dev, "get mtpt table(0x%lx) failed, ret = %d",
+			mtpt_idx, ret);
 		return ret;
-
+	}
 	/* Allocate mailbox memory */
 	mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
 	if (IS_ERR(mailbox)) {
@@ -772,7 +773,7 @@ static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
 	ret = hns_roce_sw2hw_mpt(hr_dev, mailbox,
 				 mtpt_idx & (hr_dev->caps.num_mtpts - 1));
 	if (ret) {
-		dev_err(dev, "SW2HW_MPT failed (%d)\n", ret);
+		dev_err(dev, "SW2HW_MPT(0x%lx) failed (%d)\n", mtpt_idx, ret);
 		goto err_page;
 	}
 
@@ -818,6 +819,9 @@ static int hns_roce_write_mtt_chunk(struct hns_roce_dev *hr_dev,
 		bt_page_size = 1 << (hr_dev->caps.idx_ba_pg_sz + PAGE_SHIFT);
 		break;
 	default:
+		dev_err(hr_dev->dev,
+			"Unsupport mtt type %d, write mtt chunk failed\n",
+			mtt->mtt_type);
 		return -EINVAL;
 	}
 
@@ -927,9 +931,11 @@ int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev)
 				   hr_dev->caps.num_mtpts,
 				   hr_dev->caps.num_mtpts - 1,
 				   hr_dev->caps.reserved_mrws, 0);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev,
+			"mtpt bitmap init failed, ret = %d\n", ret);
 		return ret;
-
+	}
 	ret = hns_roce_buddy_init(&mr_table->mtt_buddy,
 				  ilog2(hr_dev->caps.num_mtt_segs));
 	if (ret)
@@ -995,8 +1001,12 @@ struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc)
 	/* Allocate memory region key */
 	ret = hns_roce_mr_alloc(to_hr_dev(pd->device), to_hr_pd(pd)->pdn, 0,
 				~0ULL, acc, 0, mr);
-	if (ret)
+	if (ret) {
+		dev_err(to_hr_dev(pd->device)->dev,
+			"alloc mr failed(%d), pd =0x%lx\n",
+			ret, to_hr_pd(pd)->pdn);
 		goto err_free;
+	}
 
 #ifdef CONFIG_INFINIBAND_HNS_TEST
 	test_set_mr_access(mr);
@@ -1120,6 +1130,7 @@ static int hns_roce_ib_umem_write_mr(struct hns_roce_dev *hr_dev,
 				    (k << umem->page_shift);
 
 			if (!hr_dev->caps.pbl_hop_num) {
+				/* for hip06, page addr is aligned to 4K */
 				mr->pbl_buf[i++] = page_addr >> 12;
 			} else if (hr_dev->caps.pbl_hop_num == 1) {
 				mr->pbl_buf[i++] = page_addr;
@@ -1130,7 +1141,7 @@ static int hns_roce_ib_umem_write_mr(struct hns_roce_dev *hr_dev,
 					mr->pbl_bt_l2[i][j] = page_addr;
 
 				j++;
-				if (j >= (pbl_bt_sz / 8)) {
+				if (j >= (pbl_bt_sz / BA_BYTE_LEN)) {
 					i++;
 					j = 0;
 				}
@@ -1164,6 +1175,7 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
 			       access_flags, 0);
 	if (IS_ERR(mr->umem)) {
 		ret = PTR_ERR(mr->umem);
+		dev_err(dev, " ib_umem_get failed, ret = %d\n", ret);
 		goto err_free;
 	}
 
@@ -1180,7 +1192,8 @@ struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
 	} else {
 		u64 pbl_size = 1;
 
-		bt_size = (1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT)) / 8;
+		bt_size = (1 << (hr_dev->caps.pbl_ba_pg_sz + PAGE_SHIFT)) /
+			  BA_BYTE_LEN;
 		for (i = 0; i < hr_dev->caps.pbl_hop_num; i++)
 			pbl_size *= bt_size;
 		if (n > pbl_size) {
@@ -1243,8 +1256,8 @@ static int rereg_mr_trans(struct ib_mr *ibmr, int flags,
 		if (hr_dev->caps.pbl_hop_num)
 			hns_roce_mhop_free(hr_dev, mr);
 		else
-			dma_free_coherent(dev, npages * 8, mr->pbl_buf,
-					  mr->pbl_dma_addr);
+			dma_free_coherent(dev, npages * BA_BYTE_LEN,
+					  mr->pbl_buf, mr->pbl_dma_addr);
 	}
 	ib_umem_release(mr->umem);
 
@@ -1262,7 +1275,7 @@ static int rereg_mr_trans(struct ib_mr *ibmr, int flags,
 		if (ret)
 			goto release_umem;
 	} else {
-		mr->pbl_buf = dma_alloc_coherent(dev, npages * 8,
+		mr->pbl_buf = dma_alloc_coherent(dev, npages * BA_BYTE_LEN,
 						 &(mr->pbl_dma_addr),
 						 GFP_KERNEL);
 		if (!mr->pbl_buf) {
@@ -1286,7 +1299,7 @@ static int rereg_mr_trans(struct ib_mr *ibmr, int flags,
 			if (hr_dev->caps.pbl_hop_num)
 				hns_roce_mhop_free(hr_dev, mr);
 			else
-				dma_free_coherent(dev, npages * 8,
+				dma_free_coherent(dev, npages * BA_BYTE_LEN,
 						  mr->pbl_buf,
 						  mr->pbl_dma_addr);
 		}

drivers/infiniband/hw/hns/hns_roce_pd.c

@@ -109,7 +109,8 @@ struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev,
 
 		if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) {
 			hns_roce_pd_free(to_hr_dev(ib_dev), pd->pdn);
-			dev_err(dev, "[alloc_pd]ib_copy_to_udata failed!\n");
+			dev_err(dev, "[alloc_pd]ib_copy_to_udata failed, pd - 0x%lx!\n",
+				pd->pdn);
 			kfree(pd);
 			return ERR_PTR(-EFAULT);
 		}
@@ -119,7 +120,8 @@ struct ib_pd *hns_roce_alloc_pd(struct ib_device *ib_dev,
 	if (context) {
 		if (ib_copy_to_udata(udata, &pd->pdn, sizeof(u64))) {
 			hns_roce_pd_free(to_hr_dev(ib_dev), pd->pdn);
-			dev_err(dev, "[alloc_pd]ib_copy_to_udata failed!\n");
+			dev_err(dev, "[alloc_pd]ib_copy_to_udata failed!, pd -0x%lx\n",
+				pd->pdn);
 			kfree(pd);
 			return ERR_PTR(-EFAULT);
 		}
@@ -207,7 +209,7 @@ int hns_roce_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
 int hns_roce_uar_alloc(struct hns_roce_dev *hr_dev, struct hns_roce_uar *uar)
 {
 	struct resource *res;
-	int ret = 0;
+	int ret;
 
 	/* Using bitmap to manager UAR index */
 	ret = hns_roce_bitmap_alloc(&hr_dev->uar_table.bitmap, &uar->logic_idx);
@@ -228,8 +230,8 @@ int hns_roce_uar_alloc(struct hns_roce_dev *hr_dev, struct hns_roce_uar *uar)
 		}
 		uar->pfn = ((res->start) >> PAGE_SHIFT) + uar->index;
 	} else {
-		uar->pfn = ((pci_resource_start(hr_dev->pci_dev, 2))
-			   >> PAGE_SHIFT);
+		uar->pfn = ((pci_resource_start(hr_dev->pci_dev,
+			     HNS_ROCE_PCI_BAR_NR)) >> PAGE_SHIFT);
 	}
 
 	return 0;

drivers/infiniband/hw/hns/hns_roce_qp.c

@@ -42,6 +42,52 @@
 
 #define SQP_NUM				(2 * HNS_ROCE_MAX_PORTS)
 
+static void flush_work_handle(struct work_struct *work)
+{
+	struct hns_roce_flush_work *flush_work = container_of(work,
+					struct hns_roce_flush_work, work);
+	struct hns_roce_qp *hr_qp = flush_work->hr_qp;
+	struct device *dev = flush_work->hr_dev->dev;
+	struct ib_qp_attr attr;
+	int attr_mask;
+	int ret;
+
+	attr_mask = IB_QP_STATE;
+	attr.qp_state = IB_QPS_ERR;
+
+	ret = hns_roce_modify_qp(&hr_qp->ibqp, &attr, attr_mask, NULL);
+	if (ret)
+		dev_err(dev, "Modify qp to err for flush cqe fail(%d)\n", ret);
+
+	kfree(flush_work);
+}
+
+void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *qp,
+		     struct hns_roce_cq *cq, enum queue_type type)
+{
+	struct hns_roce_flush_work *flush_work;
+
+	flush_work = kzalloc(sizeof(struct hns_roce_flush_work), GFP_ATOMIC);
+	if (!flush_work)
+		return;
+
+	flush_work->hr_dev = hr_dev;
+	flush_work->hr_qp = qp;
+	INIT_WORK(&flush_work->work, flush_work_handle);
+	switch (type) {
+	case HNS_ROCE_SQ:
+		queue_work(qp->sq.workq, &flush_work->work);
+		break;
+	case HNS_ROCE_RQ:
+		queue_work(qp->rq.workq, &flush_work->work);
+		break;
+	case HNS_ROCE_CQ:
+		queue_work(cq->workq, &flush_work->work);
+		break;
+	}
+}
+EXPORT_SYMBOL_GPL(init_flush_work);
+
 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
 {
 	struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
@@ -61,6 +107,11 @@ void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
 		return;
 	}
 
+	if (event_type == HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR ||
+	    event_type == HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR ||
+	    event_type == HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR)
+		init_flush_work(hr_dev, qp, NULL, HNS_ROCE_SQ);
+
 	qp->event(qp, (enum hns_roce_event)event_type);
 
 	if (atomic_dec_and_test(&qp->refcount))
@@ -103,7 +154,8 @@ static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp,
 			event.event = IB_EVENT_QP_ACCESS_ERR;
 			break;
 		default:
-			dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n",
+			dev_dbg(ibqp->device->dev.parent,
+				"roce_ib:Unexpected eventtype %d on QP%06lx\n",
 				type, hr_qp->qpn);
 			return;
 		}
@@ -156,7 +208,8 @@ static int hns_roce_gsi_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
 				hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
 	spin_unlock_irq(&qp_table->lock);
 	if (ret) {
-		dev_err(hr_dev->dev, "QPC radix_tree_insert failed\n");
+		dev_err(hr_dev->dev, "QPC radix insert failed, qpn 0x%lx\n",
+			hr_qp->qpn);
 		goto err_put_irrl;
 	}
 
@@ -185,14 +238,14 @@ static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
 	/* Alloc memory for QPC */
 	ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn);
 	if (ret) {
-		dev_err(dev, "QPC table get failed\n");
+		dev_err(dev, "QPC table get failed, qpn 0x%lx\n", hr_qp->qpn);
 		goto err_out;
 	}
 
 	/* Alloc memory for IRRL */
 	ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
 	if (ret) {
-		dev_err(dev, "IRRL table get failed\n");
+		dev_err(dev, "IRRL table get failed, qpn 0x%lx\n", hr_qp->qpn);
 		goto err_put_qp;
 	}
 
@@ -201,7 +254,8 @@ static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
 		ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table,
 					 hr_qp->qpn);
 		if (ret) {
-			dev_err(dev, "TRRL table get failed\n");
+			dev_err(dev, "TRRL table get failed, qpn 0x%lx\n",
+				hr_qp->qpn);
 			goto err_put_irrl;
 		}
 	}
@@ -211,7 +265,8 @@ static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
 		ret = hns_roce_table_get(hr_dev, &qp_table->scc_ctx_table,
 					 hr_qp->qpn);
 		if (ret) {
-			dev_err(dev, "SCC CTX table get failed\n");
+			dev_err(dev, "SCC CTX table get failed, qpn 0x%lx\n",
+				hr_qp->qpn);
 			goto err_put_trrl;
 		}
 	}
@@ -221,7 +276,8 @@ static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
 				hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
 	spin_unlock_irq(&qp_table->lock);
 	if (ret) {
-		dev_err(dev, "QPC radix_tree_insert failed\n");
+		dev_err(dev, "QPC radix_tree_insert failed, qpn - 0x%lx\n",
+			hr_qp->qpn);
 		goto err_put_scc_ctx;
 	}
 
@@ -304,8 +360,8 @@ static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev,
 	/* Check the validity of QP support capacity */
 	if (cap->max_recv_wr > hr_dev->caps.max_wqes ||
 	    cap->max_recv_sge > hr_dev->caps.max_rq_sg) {
-		dev_err(dev, "RQ WR or sge error!max_recv_wr=%d max_recv_sge=%d\n",
-			cap->max_recv_wr, cap->max_recv_sge);
+		dev_err(dev, "RQ(0x%lx) WR or sge error!max_recv_wr=%d max_recv_sge=%d\n",
+			hr_qp->qpn, cap->max_recv_wr, cap->max_recv_sge);
 		return -EINVAL;
 	}
 
@@ -329,13 +385,14 @@ static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev,
 		hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt);
 
 		if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) {
-			dev_err(dev, "while setting rq size, rq.wqe_cnt too large\n");
+			dev_err(dev, "while setting rq(0x%lx) size, rq.wqe_cnt too large\n",
+				hr_qp->qpn);
 			return -EINVAL;
 		}
 
 		max_cnt = max(1U, cap->max_recv_sge);
 		hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt);
-		if (hr_dev->caps.max_rq_sg <= 2)
+		if (hr_dev->caps.max_rq_sg <= HNS_ROCE_MAX_SGE_NUM)
 			hr_qp->rq.wqe_shift =
 					ilog2(hr_dev->caps.max_rq_desc_sz);
 		else
@@ -361,12 +418,14 @@ static int check_sq_size_with_integrity(struct hns_roce_dev *hr_dev,
 	if ((u32)(1 << ucmd->log_sq_bb_count) > hr_dev->caps.max_wqes ||
 	     ucmd->log_sq_stride > max_sq_stride ||
 	     ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) {
-		dev_err(hr_dev->dev, "check SQ size error!\n");
+		dev_err(hr_dev->dev,
+			"check SQ size error!Log sq stride 0x%x\n",
+			ucmd->log_sq_stride);
 		return -EINVAL;
 	}
 
 	if (cap->max_send_sge > hr_dev->caps.max_sq_sg) {
-		dev_err(hr_dev->dev, "SQ sge error! max_send_sge=%d\n",
+		dev_err(hr_dev->dev, "SQ sge error!Max send sge %d\n",
 			cap->max_send_sge);
 		return -EINVAL;
 	}
@@ -386,7 +445,8 @@ static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev,
 
 	ret = check_sq_size_with_integrity(hr_dev, cap, ucmd);
 	if (ret) {
-		dev_err(hr_dev->dev, "Sanity check sq size fail\n");
+		dev_err(hr_dev->dev, "Sanity check sq(0x%lx) size fail\n",
+			hr_qp->qpn);
 		return ret;
 	}
 
@@ -394,33 +454,34 @@ static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev,
 	hr_qp->sq.wqe_shift = ucmd->log_sq_stride;
 
 	max_cnt = max(1U, cap->max_send_sge);
-	if (hr_dev->caps.max_sq_sg <= 2)
+	if (hr_dev->caps.max_sq_sg <= HNS_ROCE_MAX_SGE_NUM)
 		hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
 	else
 		hr_qp->sq.max_gs = max_cnt;
 
-	if (hr_qp->sq.max_gs > 2)
+	if (hr_qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE)
 		hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
-							(hr_qp->sq.max_gs - 2));
+				     (hr_qp->sq.max_gs - HNS_ROCE_SGE_IN_WQE));
 
 	if (hr_qp->ibqp.qp_type == IB_QPT_UD)
 		hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
 							hr_qp->sq.max_gs);
 
-	if ((hr_qp->sq.max_gs > 2) && (hr_dev->pci_dev->revision == 0x20)) {
+	if ((hr_qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE) &&
+	    (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_A)) {
 		if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) {
 			dev_err(hr_dev->dev,
-				"The extended sge cnt error! sge_cnt=%d\n",
-				hr_qp->sge.sge_cnt);
+				"SQ(0x%lx) extended sge cnt error! sge_cnt=%d\n",
+				hr_qp->qpn, hr_qp->sge.sge_cnt);
 			return -EINVAL;
 		}
 	}
 
-	hr_qp->sge.sge_shift = 4;
+	hr_qp->sge.sge_shift = HNS_ROCE_SGE_SHIFT;
 	ex_sge_num = hr_qp->sge.sge_cnt;
 
 	/* Get buf size, SQ and RQ  are aligned to page_szie */
-	if (hr_dev->caps.max_sq_sg <= 2) {
+	if (hr_dev->caps.max_sq_sg <= HNS_ROCE_MAX_SGE_NUM) {
 		hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
 					     hr_qp->rq.wqe_shift), PAGE_SIZE) +
 				   HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
@@ -466,20 +527,22 @@ static int set_extend_sge_param(struct hns_roce_dev *hr_dev,
 {
 	struct device *dev = hr_dev->dev;
 
-	if (hr_qp->sq.max_gs > 2) {
+	if (hr_qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE) {
 		hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
-				     (hr_qp->sq.max_gs - 2));
-		hr_qp->sge.sge_shift = 4;
+				     (hr_qp->sq.max_gs - HNS_ROCE_SGE_IN_WQE));
+		hr_qp->sge.sge_shift = HNS_ROCE_SGE_SHIFT;
 	}
 
 	/* ud sqwqe's sge use extend sge */
-	if (hr_dev->caps.max_sq_sg > 2 && hr_qp->ibqp.qp_type == IB_QPT_GSI) {
+	if (hr_dev->caps.max_sq_sg > HNS_ROCE_SGE_IN_WQE &&
+	    hr_qp->ibqp.qp_type == IB_QPT_GSI) {
 		hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
 				     hr_qp->sq.max_gs);
-		hr_qp->sge.sge_shift = 4;
+		hr_qp->sge.sge_shift = HNS_ROCE_SGE_SHIFT;
 	}
 
-	if ((hr_qp->sq.max_gs > 2) && hr_dev->pci_dev->revision == 0x20) {
+	if ((hr_qp->sq.max_gs > HNS_ROCE_SGE_IN_WQE) &&
+	    hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08_A) {
 		if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) {
 			dev_err(dev, "The extended sge cnt error! sge_cnt=%d\n",
 				hr_qp->sge.sge_cnt);
@@ -522,7 +585,7 @@ static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev,
 
 	/* Get data_seg numbers */
 	max_cnt = max(1U, cap->max_send_sge);
-	if (hr_dev->caps.max_sq_sg <= 2)
+	if (hr_dev->caps.max_sq_sg <= HNS_ROCE_MAX_SGE_NUM)
 		hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
 	else
 		hr_qp->sq.max_gs = max_cnt;
@@ -539,7 +602,8 @@ static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev,
 	size = HNS_ROCE_ALOGN_UP(hr_qp->sq.wqe_cnt << hr_qp->sq.wqe_shift,
 				 page_size);
 
-	if (hr_dev->caps.max_sq_sg > 2 && hr_qp->sge.sge_cnt) {
+	if (hr_dev->caps.max_sq_sg > HNS_ROCE_MAX_SGE_NUM &&
+	    hr_qp->sge.sge_cnt) {
 		hr_qp->sge.sge_cnt = max(page_size/(1 << hr_qp->sge.sge_shift),
 					(u32)hr_qp->sge.sge_cnt);
 		hr_qp->sge.offset = size;
@@ -580,6 +644,35 @@ static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr)
 	return 1;
 }
 
+static void destroy_qp_workqueue(struct hns_roce_qp *hr_qp)
+{
+	destroy_workqueue(hr_qp->rq.workq);
+	destroy_workqueue(hr_qp->sq.workq);
+}
+
+static int create_qp_workqueue(struct hns_roce_dev *hr_dev,
+			       struct hns_roce_qp *hr_qp)
+{
+	struct device *dev = hr_dev->dev;
+
+	hr_qp->sq.workq =
+		create_singlethread_workqueue("hns_roce_sq_workqueue");
+	if (!hr_qp->sq.workq) {
+		dev_err(dev, "Failed to create sq workqueue!\n");
+		return -ENOMEM;
+	}
+
+	hr_qp->rq.workq =
+		create_singlethread_workqueue("hns_roce_rq_workqueue");
+	if (!hr_qp->rq.workq) {
+		dev_err(dev, "Failed to create rq workqueue!\n");
+		destroy_workqueue(hr_qp->sq.workq);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
 static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
 				     struct ib_pd *ib_pd,
 				     struct ib_qp_init_attr *init_attr,
@@ -590,9 +683,9 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
 	struct hns_roce_ib_create_qp ucmd;
 	struct hns_roce_ib_create_qp_resp resp = {};
 	unsigned long qpn = 0;
-	int ret = 0;
 	u32 page_shift;
 	u32 npages;
+	int ret;
 	int i;
 
 	mutex_init(&hr_qp->mutex);
@@ -600,6 +693,7 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
 	spin_lock_init(&hr_qp->rq.lock);
 
 	hr_qp->state = IB_QPS_RESET;
+	hr_qp->next_state = IB_QPS_RESET;
 
 	hr_qp->ibqp.qp_type = init_attr->qp_type;
 
@@ -731,13 +825,15 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
 	} else {
 		if (init_attr->create_flags &
 		    IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
-			dev_err(dev, "init_attr->create_flags error!\n");
+			dev_err(dev, "init_attr->create_flags error(%d)!\n",
+				init_attr->create_flags);
 			ret = -EINVAL;
 			goto err_rq_sge_list;
 		}
 
 		if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) {
-			dev_err(dev, "init_attr->create_flags error!\n");
+			dev_err(dev, "init_attr->create_flags error(%d)!\n",
+				init_attr->create_flags);
 			ret = -EINVAL;
 			goto err_rq_sge_list;
 		}
@@ -793,9 +889,9 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
 			goto err_mtt;
 		}
 
-		hr_qp->sq.wrid = kmalloc_array(hr_qp->sq.wqe_cnt, sizeof(u64),
+		hr_qp->sq.wrid = kcalloc(hr_qp->sq.wqe_cnt, sizeof(u64),
 					       GFP_KERNEL);
-		hr_qp->rq.wrid = kmalloc_array(hr_qp->rq.wqe_cnt, sizeof(u64),
+		hr_qp->rq.wrid = kcalloc(hr_qp->rq.wqe_cnt, sizeof(u64),
 					       GFP_KERNEL);
 		if (!hr_qp->sq.wrid || !hr_qp->rq.wrid) {
 			ret = -ENOMEM;
@@ -819,13 +915,13 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
 		/* In v1 engine, GSI QP context in RoCE engine's register */
 		ret = hns_roce_gsi_qp_alloc(hr_dev, qpn, hr_qp);
 		if (ret) {
-			dev_err(dev, "hns_roce_qp_alloc failed!\n");
+			dev_err(dev, "Failed to alloc gsi qp!\n");
 			goto err_qpn;
 		}
 	} else {
 		ret = hns_roce_qp_alloc(hr_dev, qpn, hr_qp);
 		if (ret) {
-			dev_err(dev, "hns_roce_qp_alloc failed!\n");
+			dev_err(dev, "Failed to alloc qp!\n");
 			goto err_qpn;
 		}
 	}
@@ -945,11 +1041,18 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
 		if (!hr_qp)
 			return ERR_PTR(-ENOMEM);
 
+		ret = create_qp_workqueue(hr_dev, hr_qp);
+		if (ret) {
+			kfree(hr_qp);
+			return ERR_PTR(ret);
+		}
+
 		ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, 0,
 						hr_qp);
 		if (ret) {
 			dev_err(dev, "Create RC QP 0x%06lx failed(%d)\n",
 				hr_qp->qpn, ret);
+			destroy_qp_workqueue(hr_qp);
 			kfree(hr_qp);
 			return ERR_PTR(ret);
 		}
@@ -974,7 +1077,7 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
 		hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
 
 		/* when hw version is v1, the sqpn is allocated */
-		if (hr_dev->caps.max_sq_sg <= 2)
+		if (hr_dev->caps.max_sq_sg <= HNS_ROCE_MAX_SGE_NUM)
 			hr_qp->ibqp.qp_num = HNS_ROCE_MAX_PORTS +
 					     hr_dev->iboe.phy_port[hr_qp->port];
 		else
@@ -983,7 +1086,7 @@ struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
 		ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata,
 						hr_qp->ibqp.qp_num, hr_qp);
 		if (ret) {
-			dev_err(dev, "Create GSI QP failed!\n");
+			dev_err(dev, "Create GSI QP failed(%d)!\n", ret);
 			kfree(hr_sqp);
 			return ERR_PTR(ret);
 		}
@@ -1038,8 +1141,8 @@ static int check_mtu_validate(struct hns_roce_dev *hr_dev,
 	if ((hr_dev->caps.max_mtu >= IB_MTU_2048 &&
 	     attr->path_mtu > hr_dev->caps.max_mtu) ||
 	     attr->path_mtu < IB_MTU_256 || attr->path_mtu > active_mtu) {
-		dev_err(dev, "attr path_mtu(%d)invalid while modify qp",
-			attr->path_mtu);
+		dev_err(dev, "attr path_mtu(%d)invalid while modify qp(0x%lx)",
+			attr->path_mtu, hr_qp->qpn);
 		return -EINVAL;
 	}
 
@@ -1065,7 +1168,8 @@ static int hns_roce_check_qp_attr(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 	if (attr_mask & IB_QP_PKEY_INDEX) {
 		p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
 		if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) {
-			dev_err(dev, "attr pkey_index invalid.attr->pkey_index=%d\n",
+			dev_err(dev,
+				"attr pkey_index invalid.attr->pkey_index=%d\n",
 				attr->pkey_index);
 			return -EINVAL;
 		}
@@ -1079,14 +1183,14 @@ static int hns_roce_check_qp_attr(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 
 	if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 	    attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) {
-		dev_err(dev, "attr max_rd_atomic invalid.attr->max_rd_atomic=%d\n",
+		dev_err(dev, "attr max_rd_atomic(%d) invalid.\n",
 			attr->max_rd_atomic);
 		return -EINVAL;
 	}
 
 	if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 	    attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) {
-		dev_err(dev, "attr max_dest_rd_atomic invalid.attr->max_dest_rd_atomic=%d\n",
+		dev_err(dev, "attr max_dest_rd_atomic(%d) invalid.\n",
 			attr->max_dest_rd_atomic);
 		return -EINVAL;
 	}
@@ -1112,6 +1216,9 @@ int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
 	new_state = attr_mask & IB_QP_STATE ?
 		    attr->qp_state : cur_state;
 
+	hr_qp->next_state = new_state;
+	hr_qp->attr_mask = attr_mask;
+
 	if (ibqp->pd->uobject &&
 	    (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) {
 		if (hr_qp->sdb_en == 1) {
@@ -1244,7 +1351,7 @@ int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
 	INIT_RADIX_TREE(&hr_dev->qp_table_tree, GFP_ATOMIC);
 
 	/* In hw v1, a port include two SQP, six ports total 12 */
-	if (hr_dev->caps.max_sq_sg <= 2)
+	if (hr_dev->caps.max_sq_sg <= HNS_ROCE_MAX_SGE_NUM)
 		reserved_from_bot = SQP_NUM;
 	else
 		reserved_from_bot = hr_dev->caps.reserved_qps;

drivers/infiniband/hw/hns/hns_roce_restrack.c

@@ -443,8 +443,9 @@ static int hns_roce_fill_res_mr_entry(struct sk_buff *msg,
 {
 	struct ib_mr  *ib_mr = container_of(res, struct ib_mr, res);
 	struct hns_roce_dev *hr_dev = to_hr_dev(ib_mr->device);
+	struct hns_roce_mr *hr_mr = to_hr_mr(ib_mr);
 	struct hns_roce_v2_mpt_entry context;
-	int key = hr_dev->hr_stat.key;
+	int key = hr_mr->key;
 	struct nlattr *table_attr;
 	int ret;
 

drivers/infiniband/hw/hns/hns_roce_srq.c

@@ -146,8 +146,11 @@ int hns_roce_srq_alloc(struct hns_roce_dev *hr_dev, u32 pdn, u32 cqn, u16 xrcd,
 	}
 
 	ret = hns_roce_table_get(hr_dev, &srq_table->table, srq->srqn);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev, "SRQ alloc.Failed to get table, srq - 0x%lx.\n",
+			srq->srqn);
 		goto err_out;
+	}
 
 	spin_lock_irq(&srq_table->lock);
 	ret = radix_tree_insert(&srq_table->tree, srq->srqn, srq);
@@ -167,8 +170,11 @@ int hns_roce_srq_alloc(struct hns_roce_dev *hr_dev, u32 pdn, u32 cqn, u16 xrcd,
 
 	ret = hns_roce_sw2hw_srq(hr_dev, mailbox, srq->srqn);
 	hns_roce_free_cmd_mailbox(hr_dev, mailbox);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev, "SW2HW_SRQ(0x%lx) failed(%d).\n",
+			srq->srqn, ret);
 		goto err_radix;
+	}
 
 	refcount_set(&srq->refcount, 1);
 	init_completion(&srq->free);
@@ -235,8 +241,10 @@ static int create_user_srq(struct ib_pd *pd, struct hns_roce_srq *srq,
 	} else
 		ret = hns_roce_mtt_init(hr_dev, ib_umem_page_count(srq->umem),
 					srq->umem->page_shift, &srq->mtt);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev, "mtt init error when create srq\n");
 		goto err_user_buf;
+	}
 
 	ret = hns_roce_ib_umem_write_mtt(hr_dev, &srq->mtt, srq->umem);
 	if (ret)
@@ -246,7 +254,7 @@ static int create_user_srq(struct ib_pd *pd, struct hns_roce_srq *srq,
 	srq->idx_que.umem = ib_umem_get(pd->uobject->context, ucmd.que_addr,
 					srq->idx_que.buf_size, 0, 0);
 	if (IS_ERR(srq->idx_que.umem)) {
-		dev_err(hr_dev->dev, "ib_umem_get error for index queue\n");
+		dev_err(hr_dev->dev, "umem get error for idx que\n");
 		goto err_user_srq_mtt;
 	}
 
@@ -265,7 +273,7 @@ static int create_user_srq(struct ib_pd *pd, struct hns_roce_srq *srq,
 	}
 
 	if (ret) {
-		dev_err(hr_dev->dev, "hns_roce_mtt_init error for idx que\n");
+		dev_err(hr_dev->dev, "mtt init error for idx que\n");
 		goto err_user_idx_mtt;
 	}
 
@@ -273,7 +281,7 @@ static int create_user_srq(struct ib_pd *pd, struct hns_roce_srq *srq,
 					 srq->idx_que.umem);
 	if (ret) {
 		dev_err(hr_dev->dev,
-			"hns_roce_ib_umem_write_mtt error for idx que\n");
+			"write mtt error for idx que\n");
 		goto err_user_idx_buf;
 	}
 
@@ -303,13 +311,13 @@ static int hns_roce_create_idx_que(struct ib_pd *pd, struct hns_roce_srq *srq,
 	int i;
 
 	idx_que->entry_sz = HNS_ROCE_IDX_QUE_ENTRY_SZ;
-	bitmap_num = HNS_ROCE_ALOGN_UP(srq->max, 8 * sizeof(u64));
+	bitmap_num = HNS_ROCE_ALOGN_UP(srq->max, BITS_PER_LONG_LONG);
 
-	idx_que->bitmap = kcalloc(1, bitmap_num / 8, GFP_KERNEL);
+	idx_que->bitmap = kcalloc(1, bitmap_num / BITS_PER_BYTE, GFP_KERNEL);
 	if (!idx_que->bitmap)
 		return -ENOMEM;
 
-	bitmap_num = bitmap_num / (8 * sizeof(u64));
+	bitmap_num = bitmap_num / BITS_PER_LONG_LONG;
 
 	idx_que->buf_size = srq->max * idx_que->entry_sz;
 
@@ -342,8 +350,10 @@ static int create_kernel_srq(struct ib_pd *pd, struct hns_roce_srq *srq,
 
 	ret = hns_roce_mtt_init(hr_dev, srq->buf.npages, srq->buf.page_shift,
 				&srq->mtt);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev, "mtt init error when create srq\n");
 		goto err_kernel_buf;
+	}
 
 	ret = hns_roce_buf_write_mtt(hr_dev, &srq->mtt, &srq->buf);
 	if (ret)
@@ -360,13 +370,17 @@ static int create_kernel_srq(struct ib_pd *pd, struct hns_roce_srq *srq,
 	ret = hns_roce_mtt_init(hr_dev, srq->idx_que.idx_buf.npages,
 				srq->idx_que.idx_buf.page_shift,
 				&srq->idx_que.mtt);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev, "mtt init error for idx que\n");
 		goto err_kernel_create_idx;
+	}
 	/* Write buffer address into the mtt table */
 	ret = hns_roce_buf_write_mtt(hr_dev, &srq->idx_que.mtt,
 				     &srq->idx_que.idx_buf);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev, "write mtt error for idx que\n");
 		goto err_kernel_idx_buf;
+	}
 	srq->wrid = kvmalloc_array(srq->max, sizeof(u64), GFP_KERNEL);
 	if (!srq->wrid) {
 		ret = -ENOMEM;
@@ -438,7 +452,7 @@ struct ib_srq *hns_roce_create_srq(struct ib_pd *pd,
 	srq->max = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1);
 	srq->max_gs = srq_init_attr->attr.max_sge;
 
-	srq_desc_size = max(16, 16 * srq->max_gs);
+	srq_desc_size = max(HNS_ROCE_SGE_SIZE, HNS_ROCE_SGE_SIZE * srq->max_gs);
 
 	srq->wqe_shift = ilog2(srq_desc_size);
 
@@ -470,8 +484,12 @@ struct ib_srq *hns_roce_create_srq(struct ib_pd *pd,
 
 	ret = hns_roce_srq_alloc(hr_dev, to_hr_pd(pd)->pdn, cqn, 0, &srq->mtt,
 				 0, srq);
-	if (ret)
+	if (ret) {
+		dev_err(hr_dev->dev,
+			"failed to alloc srq, cqn - 0x%x, pdn - 0x%lx\n",
+			cqn, to_hr_pd(pd)->pdn);
 		goto err_wrid;
+	}
 
 	srq->event = hns_roce_ib_srq_event;
 	srq->ibsrq.ext.xrc.srq_num = srq->srqn;