提交 3d416d5f 编写于 作者: J Jean-Philippe Brucker 提交者: Xie XiuQi

PCI: Make "PRG Response PASID Required" handling common

hulk inclusion
category: feature
bugzilla: 14369
CVE: NA
-------------------

The PASID ECN to the PCIe spec added a bit in the PRI status register that
allows a Function to declare whether a PRG Response should contain the
PASID prefix or not.

Move the helper that accesses it from amd_iommu into the PCI subsystem,
renaming it to be consistent with the current PCI Express specification
(PRPR - PRG Response PASID Required).

Cc: bhelgaas@google.com
Acked-by: NBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: NJean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: NFang Lijun <fanglijun3@huawei.com>
Reviewed-by: NHanjun Guo <guohanjun@huawei.com>
Reviewed-by: NZhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: NYang Yingliang <yangyingliang@huawei.com>
上级 2b76a993
...@@ -2056,23 +2056,6 @@ static int pdev_iommuv2_enable(struct pci_dev *pdev) ...@@ -2056,23 +2056,6 @@ static int pdev_iommuv2_enable(struct pci_dev *pdev)
return ret; return ret;
} }
/* FIXME: Move this to PCI code */
#define PCI_PRI_TLP_OFF (1 << 15)
static bool pci_pri_tlp_required(struct pci_dev *pdev)
{
u16 status;
int pos;
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
if (!pos)
return false;
pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
return (status & PCI_PRI_TLP_OFF) ? true : false;
}
/* /*
* If a device is not yet associated with a domain, this function makes the * If a device is not yet associated with a domain, this function makes the
* device visible in the domain * device visible in the domain
...@@ -2101,7 +2084,8 @@ static int attach_device(struct device *dev, ...@@ -2101,7 +2084,8 @@ static int attach_device(struct device *dev,
dev_data->ats.enabled = true; dev_data->ats.enabled = true;
dev_data->ats.qdep = pci_ats_queue_depth(pdev); dev_data->ats.qdep = pci_ats_queue_depth(pdev);
dev_data->pri_tlp = pci_pri_tlp_required(pdev); dev_data->pri_tlp =
pci_prg_resp_requires_prefix(pdev);
} }
} else if (amd_iommu_iotlb_sup && } else if (amd_iommu_iotlb_sup &&
pci_enable_ats(pdev, PAGE_SHIFT) == 0) { pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
......
...@@ -394,3 +394,20 @@ int pci_max_pasids(struct pci_dev *pdev) ...@@ -394,3 +394,20 @@ int pci_max_pasids(struct pci_dev *pdev)
} }
EXPORT_SYMBOL_GPL(pci_max_pasids); EXPORT_SYMBOL_GPL(pci_max_pasids);
#endif /* CONFIG_PCI_PASID */ #endif /* CONFIG_PCI_PASID */
#if defined(CONFIG_PCI_PASID) && defined(CONFIG_PCI_PRI)
bool pci_prg_resp_requires_prefix(struct pci_dev *pdev)
{
u16 status;
int pos;
pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
if (!pos)
return false;
pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
return !!(status & PCI_PRI_STATUS_PRPR);
}
EXPORT_SYMBOL_GPL(pci_prg_resp_requires_prefix);
#endif /* CONFIG_PCI_PASID && CONFIG_PCI_PRI */
...@@ -68,5 +68,13 @@ static inline int pci_max_pasids(struct pci_dev *pdev) ...@@ -68,5 +68,13 @@ static inline int pci_max_pasids(struct pci_dev *pdev)
#endif /* CONFIG_PCI_PASID */ #endif /* CONFIG_PCI_PASID */
#if defined(CONFIG_PCI_PASID) && defined(CONFIG_PCI_PRI)
bool pci_prg_resp_requires_prefix(struct pci_dev *pdev);
#else
static inline bool pci_prg_resp_requires_prefix(struct pci_dev *pdev)
{
return false;
}
#endif /* CONFIG_PCI_PASID && CONFIG_PCI_PRI */
#endif /* LINUX_PCI_ATS_H*/ #endif /* LINUX_PCI_ATS_H*/
...@@ -879,6 +879,7 @@ ...@@ -879,6 +879,7 @@
#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ #define PCI_PRI_STATUS_RF 0x001 /* Response Failure */
#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ #define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */
#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ #define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
#define PCI_PRI_STATUS_PRPR 0x8000 /* PRG Response requires PASID prefix */
#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
#define PCI_EXT_CAP_PRI_SIZEOF 16 #define PCI_EXT_CAP_PRI_SIZEOF 16
......
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