提交 3bb045f1 编写于 作者: H H. Peter Anvin

Merge branch 'x86/pat' into x86/urgent

Merge reason:

Suresh Siddha (1):
      x86, pat: don't use rb-tree based lookup in reserve_memtype()

... requires previous x86/pat commits already pushed to Linus.
Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
...@@ -112,6 +112,10 @@ config IA64_UNCACHED_ALLOCATOR ...@@ -112,6 +112,10 @@ config IA64_UNCACHED_ALLOCATOR
bool bool
select GENERIC_ALLOCATOR select GENERIC_ALLOCATOR
config ARCH_USES_PG_UNCACHED
def_bool y
depends on IA64_UNCACHED_ALLOCATOR
config AUDIT_ARCH config AUDIT_ARCH
bool bool
default y default y
......
...@@ -1414,6 +1414,10 @@ config X86_PAT ...@@ -1414,6 +1414,10 @@ config X86_PAT
If unsure, say Y. If unsure, say Y.
config ARCH_USES_PG_UNCACHED
def_bool y
depends on X86_PAT
config EFI config EFI
bool "EFI runtime service support" bool "EFI runtime service support"
depends on ACPI depends on ACPI
......
...@@ -43,8 +43,58 @@ static inline void copy_from_user_page(struct vm_area_struct *vma, ...@@ -43,8 +43,58 @@ static inline void copy_from_user_page(struct vm_area_struct *vma,
memcpy(dst, src, len); memcpy(dst, src, len);
} }
#define PG_non_WB PG_arch_1 #define PG_WC PG_arch_1
PAGEFLAG(NonWB, non_WB) PAGEFLAG(WC, WC)
#ifdef CONFIG_X86_PAT
/*
* X86 PAT uses page flags WC and Uncached together to keep track of
* memory type of pages that have backing page struct. X86 PAT supports 3
* different memory types, _PAGE_CACHE_WB, _PAGE_CACHE_WC and
* _PAGE_CACHE_UC_MINUS and fourth state where page's memory type has not
* been changed from its default (value of -1 used to denote this).
* Note we do not support _PAGE_CACHE_UC here.
*
* Caller must hold memtype_lock for atomicity.
*/
static inline unsigned long get_page_memtype(struct page *pg)
{
if (!PageUncached(pg) && !PageWC(pg))
return -1;
else if (!PageUncached(pg) && PageWC(pg))
return _PAGE_CACHE_WC;
else if (PageUncached(pg) && !PageWC(pg))
return _PAGE_CACHE_UC_MINUS;
else
return _PAGE_CACHE_WB;
}
static inline void set_page_memtype(struct page *pg, unsigned long memtype)
{
switch (memtype) {
case _PAGE_CACHE_WC:
ClearPageUncached(pg);
SetPageWC(pg);
break;
case _PAGE_CACHE_UC_MINUS:
SetPageUncached(pg);
ClearPageWC(pg);
break;
case _PAGE_CACHE_WB:
SetPageUncached(pg);
SetPageWC(pg);
break;
default:
case -1:
ClearPageUncached(pg);
ClearPageWC(pg);
break;
}
}
#else
static inline unsigned long get_page_memtype(struct page *pg) { return -1; }
static inline void set_page_memtype(struct page *pg, unsigned long memtype) { }
#endif
/* /*
* The set_memory_* API can be used to change various attributes of a virtual * The set_memory_* API can be used to change various attributes of a virtual
......
...@@ -26,13 +26,16 @@ ...@@ -26,13 +26,16 @@
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/tlbflush.h> #include <asm/tlbflush.h>
int
is_io_mapping_possible(resource_size_t base, unsigned long size);
void * void *
iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot); iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot);
void void
iounmap_atomic(void *kvaddr, enum km_type type); iounmap_atomic(void *kvaddr, enum km_type type);
int
iomap_create_wc(resource_size_t base, unsigned long size, pgprot_t *prot);
void
iomap_free(resource_size_t base, unsigned long size);
#endif /* _ASM_X86_IOMAP_H */ #endif /* _ASM_X86_IOMAP_H */
...@@ -121,6 +121,9 @@ extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); ...@@ -121,6 +121,9 @@ extern int mtrr_del_page(int reg, unsigned long base, unsigned long size);
extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
extern void mtrr_ap_init(void); extern void mtrr_ap_init(void);
extern void mtrr_bp_init(void); extern void mtrr_bp_init(void);
extern void set_mtrr_aps_delayed_init(void);
extern void mtrr_aps_init(void);
extern void mtrr_bp_restore(void);
extern int mtrr_trim_uncached_memory(unsigned long end_pfn); extern int mtrr_trim_uncached_memory(unsigned long end_pfn);
extern int amd_special_default_mtrr(void); extern int amd_special_default_mtrr(void);
# else # else
...@@ -161,6 +164,9 @@ static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) ...@@ -161,6 +164,9 @@ static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
#define mtrr_ap_init() do {} while (0) #define mtrr_ap_init() do {} while (0)
#define mtrr_bp_init() do {} while (0) #define mtrr_bp_init() do {} while (0)
#define set_mtrr_aps_delayed_init() do {} while (0)
#define mtrr_aps_init() do {} while (0)
#define mtrr_bp_restore() do {} while (0)
# endif # endif
#ifdef CONFIG_COMPAT #ifdef CONFIG_COMPAT
......
...@@ -19,4 +19,9 @@ extern int free_memtype(u64 start, u64 end); ...@@ -19,4 +19,9 @@ extern int free_memtype(u64 start, u64 end);
extern int kernel_map_sync_memtype(u64 base, unsigned long size, extern int kernel_map_sync_memtype(u64 base, unsigned long size,
unsigned long flag); unsigned long flag);
int io_reserve_memtype(resource_size_t start, resource_size_t end,
unsigned long *type);
void io_free_memtype(resource_size_t start, resource_size_t end);
#endif /* _ASM_X86_PAT_H */ #endif /* _ASM_X86_PAT_H */
...@@ -153,7 +153,7 @@ int safe_smp_processor_id(void) ...@@ -153,7 +153,7 @@ int safe_smp_processor_id(void)
{ {
int apicid, cpuid; int apicid, cpuid;
if (!boot_cpu_has(X86_FEATURE_APIC)) if (!cpu_has_apic)
return 0; return 0;
apicid = hard_smp_processor_id(); apicid = hard_smp_processor_id();
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
#include <linux/bitops.h> #include <linux/bitops.h>
#include <linux/mm.h> #include <linux/mm.h>
#include <asm/io.h> #include <linux/io.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/apic.h> #include <asm/apic.h>
#include <asm/cpu.h> #include <asm/cpu.h>
...@@ -45,8 +45,8 @@ static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c) ...@@ -45,8 +45,8 @@ static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
#define CBAR_ENB (0x80000000) #define CBAR_ENB (0x80000000)
#define CBAR_KEY (0X000000CB) #define CBAR_KEY (0X000000CB)
if (c->x86_model == 9 || c->x86_model == 10) { if (c->x86_model == 9 || c->x86_model == 10) {
if (inl (CBAR) & CBAR_ENB) if (inl(CBAR) & CBAR_ENB)
outl (0 | CBAR_KEY, CBAR); outl(0 | CBAR_KEY, CBAR);
} }
} }
...@@ -87,9 +87,10 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c) ...@@ -87,9 +87,10 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
d = d2-d; d = d2-d;
if (d > 20*K6_BUG_LOOP) if (d > 20*K6_BUG_LOOP)
printk("system stability may be impaired when more than 32 MB are used.\n"); printk(KERN_CONT
"system stability may be impaired when more than 32 MB are used.\n");
else else
printk("probably OK (after B9730xxxx).\n"); printk(KERN_CONT "probably OK (after B9730xxxx).\n");
printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
} }
...@@ -219,8 +220,9 @@ static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c) ...@@ -219,8 +220,9 @@ static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
rdmsr(MSR_K7_CLK_CTL, l, h); rdmsr(MSR_K7_CLK_CTL, l, h);
if ((l & 0xfff00000) != 0x20000000) { if ((l & 0xfff00000) != 0x20000000) {
printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l, printk(KERN_INFO
((l & 0x000fffff)|0x20000000)); "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
l, ((l & 0x000fffff)|0x20000000));
wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
} }
} }
...@@ -398,7 +400,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) ...@@ -398,7 +400,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
u32 level; u32 level;
level = cpuid_eax(1); level = cpuid_eax(1);
if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
set_cpu_cap(c, X86_FEATURE_REP_GOOD); set_cpu_cap(c, X86_FEATURE_REP_GOOD);
/* /*
...@@ -494,27 +496,30 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) ...@@ -494,27 +496,30 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
* benefit in doing so. * benefit in doing so.
*/ */
if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
printk(KERN_DEBUG "tseg: %010llx\n", tseg); printk(KERN_DEBUG "tseg: %010llx\n", tseg);
if ((tseg>>PMD_SHIFT) < if ((tseg>>PMD_SHIFT) <
(max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) || (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
((tseg>>PMD_SHIFT) < ((tseg>>PMD_SHIFT) <
(max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) && (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
(tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT)))) (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
set_memory_4k((unsigned long)__va(tseg), 1); set_memory_4k((unsigned long)__va(tseg), 1);
} }
} }
#endif #endif
} }
#ifdef CONFIG_X86_32 #ifdef CONFIG_X86_32
static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
unsigned int size)
{ {
/* AMD errata T13 (order #21922) */ /* AMD errata T13 (order #21922) */
if ((c->x86 == 6)) { if ((c->x86 == 6)) {
if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */ /* Duron Rev A0 */
if (c->x86_model == 3 && c->x86_mask == 0)
size = 64; size = 64;
/* Tbird rev A1/A2 */
if (c->x86_model == 4 && if (c->x86_model == 4 &&
(c->x86_mask == 0 || c->x86_mask == 1)) /* Tbird rev A1/A2 */ (c->x86_mask == 0 || c->x86_mask == 1))
size = 256; size = 256;
} }
return size; return size;
......
...@@ -81,7 +81,7 @@ static void __init check_fpu(void) ...@@ -81,7 +81,7 @@ static void __init check_fpu(void)
boot_cpu_data.fdiv_bug = fdiv_bug; boot_cpu_data.fdiv_bug = fdiv_bug;
if (boot_cpu_data.fdiv_bug) if (boot_cpu_data.fdiv_bug)
printk("Hmm, FPU with FDIV bug.\n"); printk(KERN_WARNING "Hmm, FPU with FDIV bug.\n");
} }
static void __init check_hlt(void) static void __init check_hlt(void)
...@@ -98,7 +98,7 @@ static void __init check_hlt(void) ...@@ -98,7 +98,7 @@ static void __init check_hlt(void)
halt(); halt();
halt(); halt();
halt(); halt();
printk("OK.\n"); printk(KERN_CONT "OK.\n");
} }
/* /*
...@@ -122,9 +122,9 @@ static void __init check_popad(void) ...@@ -122,9 +122,9 @@ static void __init check_popad(void)
* CPU hard. Too bad. * CPU hard. Too bad.
*/ */
if (res != 12345678) if (res != 12345678)
printk("Buggy.\n"); printk(KERN_CONT "Buggy.\n");
else else
printk("OK.\n"); printk(KERN_CONT "OK.\n");
#endif #endif
} }
...@@ -156,7 +156,7 @@ void __init check_bugs(void) ...@@ -156,7 +156,7 @@ void __init check_bugs(void)
{ {
identify_boot_cpu(); identify_boot_cpu();
#ifndef CONFIG_SMP #ifndef CONFIG_SMP
printk("CPU: "); printk(KERN_INFO "CPU: ");
print_cpu_info(&boot_cpu_data); print_cpu_info(&boot_cpu_data);
#endif #endif
check_config(); check_config();
......
...@@ -15,7 +15,7 @@ void __init check_bugs(void) ...@@ -15,7 +15,7 @@ void __init check_bugs(void)
{ {
identify_boot_cpu(); identify_boot_cpu();
#if !defined(CONFIG_SMP) #if !defined(CONFIG_SMP)
printk("CPU: "); printk(KERN_INFO "CPU: ");
print_cpu_info(&boot_cpu_data); print_cpu_info(&boot_cpu_data);
#endif #endif
alternative_instructions(); alternative_instructions();
......
...@@ -18,8 +18,8 @@ ...@@ -18,8 +18,8 @@
#include <asm/hypervisor.h> #include <asm/hypervisor.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/sections.h> #include <asm/sections.h>
#include <asm/topology.h> #include <linux/topology.h>
#include <asm/cpumask.h> #include <linux/cpumask.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/atomic.h> #include <asm/atomic.h>
#include <asm/proto.h> #include <asm/proto.h>
...@@ -28,13 +28,13 @@ ...@@ -28,13 +28,13 @@
#include <asm/desc.h> #include <asm/desc.h>
#include <asm/i387.h> #include <asm/i387.h>
#include <asm/mtrr.h> #include <asm/mtrr.h>
#include <asm/numa.h> #include <linux/numa.h>
#include <asm/asm.h> #include <asm/asm.h>
#include <asm/cpu.h> #include <asm/cpu.h>
#include <asm/mce.h> #include <asm/mce.h>
#include <asm/msr.h> #include <asm/msr.h>
#include <asm/pat.h> #include <asm/pat.h>
#include <asm/smp.h> #include <linux/smp.h>
#ifdef CONFIG_X86_LOCAL_APIC #ifdef CONFIG_X86_LOCAL_APIC
#include <asm/uv/uv.h> #include <asm/uv/uv.h>
...@@ -982,7 +982,7 @@ static __init int setup_disablecpuid(char *arg) ...@@ -982,7 +982,7 @@ static __init int setup_disablecpuid(char *arg)
__setup("clearcpuid=", setup_disablecpuid); __setup("clearcpuid=", setup_disablecpuid);
#ifdef CONFIG_X86_64 #ifdef CONFIG_X86_64
struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table }; struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
DEFINE_PER_CPU_FIRST(union irq_stack_union, DEFINE_PER_CPU_FIRST(union irq_stack_union,
irq_stack_union) __aligned(PAGE_SIZE); irq_stack_union) __aligned(PAGE_SIZE);
......
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <asm/dma.h> #include <asm/dma.h>
#include <asm/io.h> #include <linux/io.h>
#include <asm/processor-cyrix.h> #include <asm/processor-cyrix.h>
#include <asm/processor-flags.h> #include <asm/processor-flags.h>
#include <asm/timer.h> #include <linux/timer.h>
#include <asm/pci-direct.h> #include <asm/pci-direct.h>
#include <asm/tsc.h> #include <asm/tsc.h>
...@@ -282,7 +282,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) ...@@ -282,7 +282,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
* The 5510/5520 companion chips have a funky PIT. * The 5510/5520 companion chips have a funky PIT.
*/ */
if (vendor == PCI_VENDOR_ID_CYRIX && if (vendor == PCI_VENDOR_ID_CYRIX &&
(device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520)) (device == PCI_DEVICE_ID_CYRIX_5510 ||
device == PCI_DEVICE_ID_CYRIX_5520))
mark_tsc_unstable("cyrix 5510/5520 detected"); mark_tsc_unstable("cyrix 5510/5520 detected");
} }
#endif #endif
...@@ -299,7 +300,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c) ...@@ -299,7 +300,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
* ? : 0x7x * ? : 0x7x
* GX1 : 0x8x GX1 datasheet 56 * GX1 : 0x8x GX1 datasheet 56
*/ */
if ((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <= dir1 && dir1 <= 0x8f)) if ((0x30 <= dir1 && dir1 <= 0x6f) ||
(0x80 <= dir1 && dir1 <= 0x8f))
geode_configure(); geode_configure();
return; return;
} else { /* MediaGX */ } else { /* MediaGX */
...@@ -427,9 +429,12 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c) ...@@ -427,9 +429,12 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n"); printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
local_irq_save(flags); local_irq_save(flags);
ccr3 = getCx86(CX86_CCR3); ccr3 = getCx86(CX86_CCR3);
setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ /* enable MAPEN */
setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80); /* enable cpuid */ setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ /* enable cpuid */
setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80);
/* disable MAPEN */
setCx86(CX86_CCR3, ccr3);
local_irq_restore(flags); local_irq_restore(flags);
} }
} }
......
...@@ -28,11 +28,10 @@ ...@@ -28,11 +28,10 @@
static inline void __cpuinit static inline void __cpuinit
detect_hypervisor_vendor(struct cpuinfo_x86 *c) detect_hypervisor_vendor(struct cpuinfo_x86 *c)
{ {
if (vmware_platform()) { if (vmware_platform())
c->x86_hyper_vendor = X86_HYPER_VENDOR_VMWARE; c->x86_hyper_vendor = X86_HYPER_VENDOR_VMWARE;
} else { else
c->x86_hyper_vendor = X86_HYPER_VENDOR_NONE; c->x86_hyper_vendor = X86_HYPER_VENDOR_NONE;
}
} }
unsigned long get_hypervisor_tsc_freq(void) unsigned long get_hypervisor_tsc_freq(void)
......
...@@ -7,17 +7,17 @@ ...@@ -7,17 +7,17 @@
#include <linux/sched.h> #include <linux/sched.h>
#include <linux/thread_info.h> #include <linux/thread_info.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/uaccess.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/msr.h> #include <asm/msr.h>
#include <asm/uaccess.h>
#include <asm/ds.h> #include <asm/ds.h>
#include <asm/bugs.h> #include <asm/bugs.h>
#include <asm/cpu.h> #include <asm/cpu.h>
#ifdef CONFIG_X86_64 #ifdef CONFIG_X86_64
#include <asm/topology.h> #include <linux/topology.h>
#include <asm/numa_64.h> #include <asm/numa_64.h>
#endif #endif
...@@ -174,7 +174,8 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) ...@@ -174,7 +174,8 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_F00F_BUG #ifdef CONFIG_X86_F00F_BUG
/* /*
* All current models of Pentium and Pentium with MMX technology CPUs * All current models of Pentium and Pentium with MMX technology CPUs
* have the F0 0F bug, which lets nonprivileged users lock up the system. * have the F0 0F bug, which lets nonprivileged users lock up the
* system.
* Note that the workaround only should be initialized once... * Note that the workaround only should be initialized once...
*/ */
c->f00f_bug = 0; c->f00f_bug = 0;
...@@ -207,7 +208,7 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) ...@@ -207,7 +208,7 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n"); printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n"); printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE; lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
wrmsr (MSR_IA32_MISC_ENABLE, lo, hi); wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
} }
} }
...@@ -283,7 +284,7 @@ static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c) ...@@ -283,7 +284,7 @@ static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
/* Intel has a non-standard dependency on %ecx for this CPUID level. */ /* Intel has a non-standard dependency on %ecx for this CPUID level. */
cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
if (eax & 0x1f) if (eax & 0x1f)
return ((eax >> 26) + 1); return (eax >> 26) + 1;
else else
return 1; return 1;
} }
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* *
* Changes: * Changes:
* Venkatesh Pallipadi : Adding cache identification through cpuid(4) * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
* Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure. * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
* Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD. * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
*/ */
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
#include <linux/pci.h> #include <linux/pci.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/smp.h> #include <linux/smp.h>
#include <asm/k8.h> #include <asm/k8.h>
#define LVL_1_INST 1 #define LVL_1_INST 1
...@@ -25,14 +25,15 @@ ...@@ -25,14 +25,15 @@
#define LVL_3 4 #define LVL_3 4
#define LVL_TRACE 5 #define LVL_TRACE 5
struct _cache_table struct _cache_table {
{
unsigned char descriptor; unsigned char descriptor;
char cache_type; char cache_type;
short size; short size;
}; };
/* all the cache descriptor types we care about (no TLB or trace cache entries) */ /* All the cache descriptor types we care about (no TLB or
trace cache entries) */
static const struct _cache_table __cpuinitconst cache_table[] = static const struct _cache_table __cpuinitconst cache_table[] =
{ {
{ 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */ { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
...@@ -105,8 +106,7 @@ static const struct _cache_table __cpuinitconst cache_table[] = ...@@ -105,8 +106,7 @@ static const struct _cache_table __cpuinitconst cache_table[] =
}; };
enum _cache_type enum _cache_type {
{
CACHE_TYPE_NULL = 0, CACHE_TYPE_NULL = 0,
CACHE_TYPE_DATA = 1, CACHE_TYPE_DATA = 1,
CACHE_TYPE_INST = 2, CACHE_TYPE_INST = 2,
...@@ -170,31 +170,31 @@ unsigned short num_cache_leaves; ...@@ -170,31 +170,31 @@ unsigned short num_cache_leaves;
Maybe later */ Maybe later */
union l1_cache { union l1_cache {
struct { struct {
unsigned line_size : 8; unsigned line_size:8;
unsigned lines_per_tag : 8; unsigned lines_per_tag:8;
unsigned assoc : 8; unsigned assoc:8;
unsigned size_in_kb : 8; unsigned size_in_kb:8;
}; };
unsigned val; unsigned val;
}; };
union l2_cache { union l2_cache {
struct { struct {
unsigned line_size : 8; unsigned line_size:8;
unsigned lines_per_tag : 4; unsigned lines_per_tag:4;
unsigned assoc : 4; unsigned assoc:4;
unsigned size_in_kb : 16; unsigned size_in_kb:16;
}; };
unsigned val; unsigned val;
}; };
union l3_cache { union l3_cache {
struct { struct {
unsigned line_size : 8; unsigned line_size:8;
unsigned lines_per_tag : 4; unsigned lines_per_tag:4;
unsigned assoc : 4; unsigned assoc:4;
unsigned res : 2; unsigned res:2;
unsigned size_encoded : 14; unsigned size_encoded:14;
}; };
unsigned val; unsigned val;
}; };
...@@ -350,7 +350,8 @@ static int __cpuinit find_num_cache_leaves(void) ...@@ -350,7 +350,8 @@ static int __cpuinit find_num_cache_leaves(void)
unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c) unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
{ {
unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */ /* Cache sizes */
unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */ unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */ unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb; unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
...@@ -377,8 +378,8 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c) ...@@ -377,8 +378,8 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
retval = cpuid4_cache_lookup_regs(i, &this_leaf); retval = cpuid4_cache_lookup_regs(i, &this_leaf);
if (retval >= 0) { if (retval >= 0) {
switch(this_leaf.eax.split.level) { switch (this_leaf.eax.split.level) {
case 1: case 1:
if (this_leaf.eax.split.type == if (this_leaf.eax.split.type ==
CACHE_TYPE_DATA) CACHE_TYPE_DATA)
new_l1d = this_leaf.size/1024; new_l1d = this_leaf.size/1024;
...@@ -386,19 +387,20 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c) ...@@ -386,19 +387,20 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
CACHE_TYPE_INST) CACHE_TYPE_INST)
new_l1i = this_leaf.size/1024; new_l1i = this_leaf.size/1024;
break; break;
case 2: case 2:
new_l2 = this_leaf.size/1024; new_l2 = this_leaf.size/1024;
num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing; num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
index_msb = get_count_order(num_threads_sharing); index_msb = get_count_order(num_threads_sharing);
l2_id = c->apicid >> index_msb; l2_id = c->apicid >> index_msb;
break; break;
case 3: case 3:
new_l3 = this_leaf.size/1024; new_l3 = this_leaf.size/1024;
num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing; num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
index_msb = get_count_order(num_threads_sharing); index_msb = get_count_order(
num_threads_sharing);
l3_id = c->apicid >> index_msb; l3_id = c->apicid >> index_msb;
break; break;
default: default:
break; break;
} }
} }
...@@ -421,22 +423,21 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c) ...@@ -421,22 +423,21 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
/* Number of times to iterate */ /* Number of times to iterate */
n = cpuid_eax(2) & 0xFF; n = cpuid_eax(2) & 0xFF;
for ( i = 0 ; i < n ; i++ ) { for (i = 0 ; i < n ; i++) {
cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]); cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
/* If bit 31 is set, this is an unknown format */ /* If bit 31 is set, this is an unknown format */
for ( j = 0 ; j < 3 ; j++ ) { for (j = 0 ; j < 3 ; j++)
if (regs[j] & (1 << 31)) regs[j] = 0; if (regs[j] & (1 << 31))
} regs[j] = 0;
/* Byte 0 is level count, not a descriptor */ /* Byte 0 is level count, not a descriptor */
for ( j = 1 ; j < 16 ; j++ ) { for (j = 1 ; j < 16 ; j++) {
unsigned char des = dp[j]; unsigned char des = dp[j];
unsigned char k = 0; unsigned char k = 0;
/* look up this descriptor in the table */ /* look up this descriptor in the table */
while (cache_table[k].descriptor != 0) while (cache_table[k].descriptor != 0) {
{
if (cache_table[k].descriptor == des) { if (cache_table[k].descriptor == des) {
if (only_trace && cache_table[k].cache_type != LVL_TRACE) if (only_trace && cache_table[k].cache_type != LVL_TRACE)
break; break;
...@@ -488,14 +489,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c) ...@@ -488,14 +489,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
} }
if (trace) if (trace)
printk (KERN_INFO "CPU: Trace cache: %dK uops", trace); printk(KERN_INFO "CPU: Trace cache: %dK uops", trace);
else if ( l1i ) else if (l1i)
printk (KERN_INFO "CPU: L1 I cache: %dK", l1i); printk(KERN_INFO "CPU: L1 I cache: %dK", l1i);
if (l1d) if (l1d)
printk(", L1 D cache: %dK\n", l1d); printk(KERN_CONT ", L1 D cache: %dK\n", l1d);
else else
printk("\n"); printk(KERN_CONT "\n");
if (l2) if (l2)
printk(KERN_INFO "CPU: L2 cache: %dK\n", l2); printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
...@@ -558,8 +559,13 @@ static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index) ...@@ -558,8 +559,13 @@ static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
} }
} }
#else #else
static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index) {} static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index) {} {
}
static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
{
}
#endif #endif
static void __cpuinit free_cache_attributes(unsigned int cpu) static void __cpuinit free_cache_attributes(unsigned int cpu)
...@@ -645,7 +651,7 @@ static DEFINE_PER_CPU(struct _index_kobject *, index_kobject); ...@@ -645,7 +651,7 @@ static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
static ssize_t show_##file_name \ static ssize_t show_##file_name \
(struct _cpuid4_info *this_leaf, char *buf) \ (struct _cpuid4_info *this_leaf, char *buf) \
{ \ { \
return sprintf (buf, "%lu\n", (unsigned long)this_leaf->object + val); \ return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
} }
show_one_plus(level, eax.split.level, 0); show_one_plus(level, eax.split.level, 0);
...@@ -656,7 +662,7 @@ show_one_plus(number_of_sets, ecx.split.number_of_sets, 1); ...@@ -656,7 +662,7 @@ show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf) static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
{ {
return sprintf (buf, "%luK\n", this_leaf->size / 1024); return sprintf(buf, "%luK\n", this_leaf->size / 1024);
} }
static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf, static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
...@@ -669,7 +675,7 @@ static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf, ...@@ -669,7 +675,7 @@ static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
const struct cpumask *mask; const struct cpumask *mask;
mask = to_cpumask(this_leaf->shared_cpu_map); mask = to_cpumask(this_leaf->shared_cpu_map);
n = type? n = type ?
cpulist_scnprintf(buf, len-2, mask) : cpulist_scnprintf(buf, len-2, mask) :
cpumask_scnprintf(buf, len-2, mask); cpumask_scnprintf(buf, len-2, mask);
buf[n++] = '\n'; buf[n++] = '\n';
...@@ -800,7 +806,7 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644, ...@@ -800,7 +806,7 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644, static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
show_cache_disable_1, store_cache_disable_1); show_cache_disable_1, store_cache_disable_1);
static struct attribute * default_attrs[] = { static struct attribute *default_attrs[] = {
&type.attr, &type.attr,
&level.attr, &level.attr,
&coherency_line_size.attr, &coherency_line_size.attr,
...@@ -815,7 +821,7 @@ static struct attribute * default_attrs[] = { ...@@ -815,7 +821,7 @@ static struct attribute * default_attrs[] = {
NULL NULL
}; };
static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf) static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
{ {
struct _cache_attr *fattr = to_attr(attr); struct _cache_attr *fattr = to_attr(attr);
struct _index_kobject *this_leaf = to_object(kobj); struct _index_kobject *this_leaf = to_object(kobj);
...@@ -828,8 +834,8 @@ static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf) ...@@ -828,8 +834,8 @@ static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
return ret; return ret;
} }
static ssize_t store(struct kobject * kobj, struct attribute * attr, static ssize_t store(struct kobject *kobj, struct attribute *attr,
const char * buf, size_t count) const char *buf, size_t count)
{ {
struct _cache_attr *fattr = to_attr(attr); struct _cache_attr *fattr = to_attr(attr);
struct _index_kobject *this_leaf = to_object(kobj); struct _index_kobject *this_leaf = to_object(kobj);
...@@ -883,7 +889,7 @@ static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu) ...@@ -883,7 +889,7 @@ static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
goto err_out; goto err_out;
per_cpu(index_kobject, cpu) = kzalloc( per_cpu(index_kobject, cpu) = kzalloc(
sizeof(struct _index_kobject ) * num_cache_leaves, GFP_KERNEL); sizeof(struct _index_kobject) * num_cache_leaves, GFP_KERNEL);
if (unlikely(per_cpu(index_kobject, cpu) == NULL)) if (unlikely(per_cpu(index_kobject, cpu) == NULL))
goto err_out; goto err_out;
...@@ -917,7 +923,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev) ...@@ -917,7 +923,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
} }
for (i = 0; i < num_cache_leaves; i++) { for (i = 0; i < num_cache_leaves; i++) {
this_object = INDEX_KOBJECT_PTR(cpu,i); this_object = INDEX_KOBJECT_PTR(cpu, i);
this_object->cpu = cpu; this_object->cpu = cpu;
this_object->index = i; this_object->index = i;
retval = kobject_init_and_add(&(this_object->kobj), retval = kobject_init_and_add(&(this_object->kobj),
...@@ -925,9 +931,8 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev) ...@@ -925,9 +931,8 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
per_cpu(cache_kobject, cpu), per_cpu(cache_kobject, cpu),
"index%1lu", i); "index%1lu", i);
if (unlikely(retval)) { if (unlikely(retval)) {
for (j = 0; j < i; j++) { for (j = 0; j < i; j++)
kobject_put(&(INDEX_KOBJECT_PTR(cpu,j)->kobj)); kobject_put(&(INDEX_KOBJECT_PTR(cpu, j)->kobj));
}
kobject_put(per_cpu(cache_kobject, cpu)); kobject_put(per_cpu(cache_kobject, cpu));
cpuid4_cache_sysfs_exit(cpu); cpuid4_cache_sysfs_exit(cpu);
return retval; return retval;
...@@ -952,7 +957,7 @@ static void __cpuinit cache_remove_dev(struct sys_device * sys_dev) ...@@ -952,7 +957,7 @@ static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map)); cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
for (i = 0; i < num_cache_leaves; i++) for (i = 0; i < num_cache_leaves; i++)
kobject_put(&(INDEX_KOBJECT_PTR(cpu,i)->kobj)); kobject_put(&(INDEX_KOBJECT_PTR(cpu, i)->kobj));
kobject_put(per_cpu(cache_kobject, cpu)); kobject_put(per_cpu(cache_kobject, cpu));
cpuid4_cache_sysfs_exit(cpu); cpuid4_cache_sysfs_exit(cpu);
} }
...@@ -977,8 +982,7 @@ static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb, ...@@ -977,8 +982,7 @@ static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
return NOTIFY_OK; return NOTIFY_OK;
} }
static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier = static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier = {
{
.notifier_call = cacheinfo_cpu_callback, .notifier_call = cacheinfo_cpu_callback,
}; };
......
...@@ -7,15 +7,15 @@ ...@@ -7,15 +7,15 @@
static void static void
amd_get_mtrr(unsigned int reg, unsigned long *base, amd_get_mtrr(unsigned int reg, unsigned long *base,
unsigned long *size, mtrr_type * type) unsigned long *size, mtrr_type *type)
{ {
unsigned long low, high; unsigned long low, high;
rdmsr(MSR_K6_UWCCR, low, high); rdmsr(MSR_K6_UWCCR, low, high);
/* Upper dword is region 1, lower is region 0 */ /* Upper dword is region 1, lower is region 0 */
if (reg == 1) if (reg == 1)
low = high; low = high;
/* The base masks off on the right alignment */ /* The base masks off on the right alignment */
*base = (low & 0xFFFE0000) >> PAGE_SHIFT; *base = (low & 0xFFFE0000) >> PAGE_SHIFT;
*type = 0; *type = 0;
if (low & 1) if (low & 1)
...@@ -27,74 +27,81 @@ amd_get_mtrr(unsigned int reg, unsigned long *base, ...@@ -27,74 +27,81 @@ amd_get_mtrr(unsigned int reg, unsigned long *base,
return; return;
} }
/* /*
* This needs a little explaining. The size is stored as an * This needs a little explaining. The size is stored as an
* inverted mask of bits of 128K granularity 15 bits long offset * inverted mask of bits of 128K granularity 15 bits long offset
* 2 bits * 2 bits.
* *
* So to get a size we do invert the mask and add 1 to the lowest * So to get a size we do invert the mask and add 1 to the lowest
* mask bit (4 as its 2 bits in). This gives us a size we then shift * mask bit (4 as its 2 bits in). This gives us a size we then shift
* to turn into 128K blocks * to turn into 128K blocks.
* *
* eg 111 1111 1111 1100 is 512K * eg 111 1111 1111 1100 is 512K
* *
* invert 000 0000 0000 0011 * invert 000 0000 0000 0011
* +1 000 0000 0000 0100 * +1 000 0000 0000 0100
* *128K ... * *128K ...
*/ */
low = (~low) & 0x1FFFC; low = (~low) & 0x1FFFC;
*size = (low + 4) << (15 - PAGE_SHIFT); *size = (low + 4) << (15 - PAGE_SHIFT);
return;
} }
static void amd_set_mtrr(unsigned int reg, unsigned long base, /**
unsigned long size, mtrr_type type) * amd_set_mtrr - Set variable MTRR register on the local CPU.
/* [SUMMARY] Set variable MTRR register on the local CPU. *
<reg> The register to set. * @reg The register to set.
<base> The base address of the region. * @base The base address of the region.
<size> The size of the region. If this is 0 the region is disabled. * @size The size of the region. If this is 0 the region is disabled.
<type> The type of the region. * @type The type of the region.
[RETURNS] Nothing. *
*/ * Returns nothing.
*/
static void
amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
{ {
u32 regs[2]; u32 regs[2];
/* /*
* Low is MTRR0 , High MTRR 1 * Low is MTRR0, High MTRR 1
*/ */
rdmsr(MSR_K6_UWCCR, regs[0], regs[1]); rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
/* /*
* Blank to disable * Blank to disable
*/ */
if (size == 0) if (size == 0) {
regs[reg] = 0; regs[reg] = 0;
else } else {
/* Set the register to the base, the type (off by one) and an /*
inverted bitmask of the size The size is the only odd * Set the register to the base, the type (off by one) and an
bit. We are fed say 512K We invert this and we get 111 1111 * inverted bitmask of the size The size is the only odd
1111 1011 but if you subtract one and invert you get the * bit. We are fed say 512K We invert this and we get 111 1111
desired 111 1111 1111 1100 mask * 1111 1011 but if you subtract one and invert you get the
* desired 111 1111 1111 1100 mask
But ~(x - 1) == ~x + 1 == -x. Two's complement rocks! */ *
* But ~(x - 1) == ~x + 1 == -x. Two's complement rocks!
*/
regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC) regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC)
| (base << PAGE_SHIFT) | (type + 1); | (base << PAGE_SHIFT) | (type + 1);
}
/* /*
* The writeback rule is quite specific. See the manual. Its * The writeback rule is quite specific. See the manual. Its
* disable local interrupts, write back the cache, set the mtrr * disable local interrupts, write back the cache, set the mtrr
*/ */
wbinvd(); wbinvd();
wrmsr(MSR_K6_UWCCR, regs[0], regs[1]); wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
} }
static int amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type) static int
amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
{ {
/* Apply the K6 block alignment and size rules /*
In order * Apply the K6 block alignment and size rules
o Uncached or gathering only * In order
o 128K or bigger block * o Uncached or gathering only
o Power of 2 block * o 128K or bigger block
o base suitably aligned to the power * o Power of 2 block
*/ * o base suitably aligned to the power
*/
if (type > MTRR_TYPE_WRCOMB || size < (1 << (17 - PAGE_SHIFT)) if (type > MTRR_TYPE_WRCOMB || size < (1 << (17 - PAGE_SHIFT))
|| (size & ~(size - 1)) - size || (base & (size - 1))) || (size & ~(size - 1)) - size || (base & (size - 1)))
return -EINVAL; return -EINVAL;
...@@ -115,5 +122,3 @@ int __init amd_init_mtrr(void) ...@@ -115,5 +122,3 @@ int __init amd_init_mtrr(void)
set_mtrr_ops(&amd_mtrr_ops); set_mtrr_ops(&amd_mtrr_ops);
return 0; return 0;
} }
//arch_initcall(amd_mtrr_init);
#include <linux/init.h> #include <linux/init.h>
#include <linux/mm.h> #include <linux/mm.h>
#include <asm/mtrr.h> #include <asm/mtrr.h>
#include <asm/msr.h> #include <asm/msr.h>
#include "mtrr.h" #include "mtrr.h"
static struct { static struct {
...@@ -12,25 +14,25 @@ static struct { ...@@ -12,25 +14,25 @@ static struct {
static u8 centaur_mcr_reserved; static u8 centaur_mcr_reserved;
static u8 centaur_mcr_type; /* 0 for winchip, 1 for winchip2 */ static u8 centaur_mcr_type; /* 0 for winchip, 1 for winchip2 */
/* /**
* Report boot time MCR setups * centaur_get_free_region - Get a free MTRR.
*
* @base: The starting (base) address of the region.
* @size: The size (in bytes) of the region.
*
* Returns: the index of the region on success, else -1 on error.
*/ */
static int static int
centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg) centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg)
/* [SUMMARY] Get a free MTRR.
<base> The starting (base) address of the region.
<size> The size (in bytes) of the region.
[RETURNS] The index of the region on success, else -1 on error.
*/
{ {
int i, max;
mtrr_type ltype;
unsigned long lbase, lsize; unsigned long lbase, lsize;
mtrr_type ltype;
int i, max;
max = num_var_ranges; max = num_var_ranges;
if (replace_reg >= 0 && replace_reg < max) if (replace_reg >= 0 && replace_reg < max)
return replace_reg; return replace_reg;
for (i = 0; i < max; ++i) { for (i = 0; i < max; ++i) {
if (centaur_mcr_reserved & (1 << i)) if (centaur_mcr_reserved & (1 << i))
continue; continue;
...@@ -38,11 +40,14 @@ centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg) ...@@ -38,11 +40,14 @@ centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg)
if (lsize == 0) if (lsize == 0)
return i; return i;
} }
return -ENOSPC; return -ENOSPC;
} }
void /*
mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) * Report boot time MCR setups
*/
void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
{ {
centaur_mcr[mcr].low = lo; centaur_mcr[mcr].low = lo;
centaur_mcr[mcr].high = hi; centaur_mcr[mcr].high = hi;
...@@ -54,33 +59,35 @@ centaur_get_mcr(unsigned int reg, unsigned long *base, ...@@ -54,33 +59,35 @@ centaur_get_mcr(unsigned int reg, unsigned long *base,
{ {
*base = centaur_mcr[reg].high >> PAGE_SHIFT; *base = centaur_mcr[reg].high >> PAGE_SHIFT;
*size = -(centaur_mcr[reg].low & 0xfffff000) >> PAGE_SHIFT; *size = -(centaur_mcr[reg].low & 0xfffff000) >> PAGE_SHIFT;
*type = MTRR_TYPE_WRCOMB; /* If it is there, it is write-combining */ *type = MTRR_TYPE_WRCOMB; /* write-combining */
if (centaur_mcr_type == 1 && ((centaur_mcr[reg].low & 31) & 2)) if (centaur_mcr_type == 1 && ((centaur_mcr[reg].low & 31) & 2))
*type = MTRR_TYPE_UNCACHABLE; *type = MTRR_TYPE_UNCACHABLE;
if (centaur_mcr_type == 1 && (centaur_mcr[reg].low & 31) == 25) if (centaur_mcr_type == 1 && (centaur_mcr[reg].low & 31) == 25)
*type = MTRR_TYPE_WRBACK; *type = MTRR_TYPE_WRBACK;
if (centaur_mcr_type == 0 && (centaur_mcr[reg].low & 31) == 31) if (centaur_mcr_type == 0 && (centaur_mcr[reg].low & 31) == 31)
*type = MTRR_TYPE_WRBACK; *type = MTRR_TYPE_WRBACK;
} }
static void centaur_set_mcr(unsigned int reg, unsigned long base, static void
unsigned long size, mtrr_type type) centaur_set_mcr(unsigned int reg, unsigned long base,
unsigned long size, mtrr_type type)
{ {
unsigned long low, high; unsigned long low, high;
if (size == 0) { if (size == 0) {
/* Disable */ /* Disable */
high = low = 0; high = low = 0;
} else { } else {
high = base << PAGE_SHIFT; high = base << PAGE_SHIFT;
if (centaur_mcr_type == 0) if (centaur_mcr_type == 0) {
low = -size << PAGE_SHIFT | 0x1f; /* only support write-combining... */ /* Only support write-combining... */
else { low = -size << PAGE_SHIFT | 0x1f;
} else {
if (type == MTRR_TYPE_UNCACHABLE) if (type == MTRR_TYPE_UNCACHABLE)
low = -size << PAGE_SHIFT | 0x02; /* NC */ low = -size << PAGE_SHIFT | 0x02; /* NC */
else else
low = -size << PAGE_SHIFT | 0x09; /* WWO,WC */ low = -size << PAGE_SHIFT | 0x09; /* WWO, WC */
} }
} }
centaur_mcr[reg].high = high; centaur_mcr[reg].high = high;
...@@ -88,118 +95,16 @@ static void centaur_set_mcr(unsigned int reg, unsigned long base, ...@@ -88,118 +95,16 @@ static void centaur_set_mcr(unsigned int reg, unsigned long base,
wrmsr(MSR_IDT_MCR0 + reg, low, high); wrmsr(MSR_IDT_MCR0 + reg, low, high);
} }
#if 0 static int
/* centaur_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
* Initialise the later (saner) Winchip MCR variant. In this version
* the BIOS can pass us the registers it has used (but not their values)
* and the control register is read/write
*/
static void __init
centaur_mcr1_init(void)
{
unsigned i;
u32 lo, hi;
/* Unfortunately, MCR's are read-only, so there is no way to
* find out what the bios might have done.
*/
rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
if (((lo >> 17) & 7) == 1) { /* Type 1 Winchip2 MCR */
lo &= ~0x1C0; /* clear key */
lo |= 0x040; /* set key to 1 */
wrmsr(MSR_IDT_MCR_CTRL, lo, hi); /* unlock MCR */
}
centaur_mcr_type = 1;
/*
* Clear any unconfigured MCR's.
*/
for (i = 0; i < 8; ++i) {
if (centaur_mcr[i].high == 0 && centaur_mcr[i].low == 0) {
if (!(lo & (1 << (9 + i))))
wrmsr(MSR_IDT_MCR0 + i, 0, 0);
else
/*
* If the BIOS set up an MCR we cannot see it
* but we don't wish to obliterate it
*/
centaur_mcr_reserved |= (1 << i);
}
}
/*
* Throw the main write-combining switch...
* However if OOSTORE is enabled then people have already done far
* cleverer things and we should behave.
*/
lo |= 15; /* Write combine enables */
wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
}
/*
* Initialise the original winchip with read only MCR registers
* no used bitmask for the BIOS to pass on and write only control
*/
static void __init
centaur_mcr0_init(void)
{
unsigned i;
/* Unfortunately, MCR's are read-only, so there is no way to
* find out what the bios might have done.
*/
/* Clear any unconfigured MCR's.
* This way we are sure that the centaur_mcr array contains the actual
* values. The disadvantage is that any BIOS tweaks are thus undone.
*
*/
for (i = 0; i < 8; ++i) {
if (centaur_mcr[i].high == 0 && centaur_mcr[i].low == 0)
wrmsr(MSR_IDT_MCR0 + i, 0, 0);
}
wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0); /* Write only */
}
/*
* Initialise Winchip series MCR registers
*/
static void __init
centaur_mcr_init(void)
{
struct set_mtrr_context ctxt;
set_mtrr_prepare_save(&ctxt);
set_mtrr_cache_disable(&ctxt);
if (boot_cpu_data.x86_model == 4)
centaur_mcr0_init();
else if (boot_cpu_data.x86_model == 8 || boot_cpu_data.x86_model == 9)
centaur_mcr1_init();
set_mtrr_done(&ctxt);
}
#endif
static int centaur_validate_add_page(unsigned long base,
unsigned long size, unsigned int type)
{ {
/* /*
* FIXME: Winchip2 supports uncached * FIXME: Winchip2 supports uncached
*/ */
if (type != MTRR_TYPE_WRCOMB && if (type != MTRR_TYPE_WRCOMB &&
(centaur_mcr_type == 0 || type != MTRR_TYPE_UNCACHABLE)) { (centaur_mcr_type == 0 || type != MTRR_TYPE_UNCACHABLE)) {
printk(KERN_WARNING pr_warning("mtrr: only write-combining%s supported\n",
"mtrr: only write-combining%s supported\n", centaur_mcr_type ? " and uncacheable are" : " is");
centaur_mcr_type ? " and uncacheable are"
: " is");
return -EINVAL; return -EINVAL;
} }
return 0; return 0;
...@@ -207,7 +112,6 @@ static int centaur_validate_add_page(unsigned long base, ...@@ -207,7 +112,6 @@ static int centaur_validate_add_page(unsigned long base,
static struct mtrr_ops centaur_mtrr_ops = { static struct mtrr_ops centaur_mtrr_ops = {
.vendor = X86_VENDOR_CENTAUR, .vendor = X86_VENDOR_CENTAUR,
// .init = centaur_mcr_init,
.set = centaur_set_mcr, .set = centaur_set_mcr,
.get = centaur_get_mcr, .get = centaur_get_mcr,
.get_free_region = centaur_get_free_region, .get_free_region = centaur_get_free_region,
...@@ -220,5 +124,3 @@ int __init centaur_init_mtrr(void) ...@@ -220,5 +124,3 @@ int __init centaur_init_mtrr(void)
set_mtrr_ops(&centaur_mtrr_ops); set_mtrr_ops(&centaur_mtrr_ops);
return 0; return 0;
} }
//arch_initcall(centaur_init_mtrr);
此差异已折叠。
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h>
#include <linux/mm.h> #include <linux/mm.h>
#include <asm/mtrr.h>
#include <asm/msr.h>
#include <asm/io.h>
#include <asm/processor-cyrix.h> #include <asm/processor-cyrix.h>
#include <asm/processor-flags.h> #include <asm/processor-flags.h>
#include <asm/mtrr.h>
#include <asm/msr.h>
#include "mtrr.h" #include "mtrr.h"
static void static void
cyrix_get_arr(unsigned int reg, unsigned long *base, cyrix_get_arr(unsigned int reg, unsigned long *base,
unsigned long *size, mtrr_type * type) unsigned long *size, mtrr_type * type)
{ {
unsigned long flags;
unsigned char arr, ccr3, rcr, shift; unsigned char arr, ccr3, rcr, shift;
unsigned long flags;
arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */ arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
/* Save flags and disable interrupts */
local_irq_save(flags); local_irq_save(flags);
ccr3 = getCx86(CX86_CCR3); ccr3 = getCx86(CX86_CCR3);
setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */ setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
((unsigned char *) base)[3] = getCx86(arr); ((unsigned char *)base)[3] = getCx86(arr);
((unsigned char *) base)[2] = getCx86(arr + 1); ((unsigned char *)base)[2] = getCx86(arr + 1);
((unsigned char *) base)[1] = getCx86(arr + 2); ((unsigned char *)base)[1] = getCx86(arr + 2);
rcr = getCx86(CX86_RCR_BASE + reg); rcr = getCx86(CX86_RCR_BASE + reg);
setCx86(CX86_CCR3, ccr3); /* disable MAPEN */ setCx86(CX86_CCR3, ccr3); /* disable MAPEN */
/* Enable interrupts if it was enabled previously */
local_irq_restore(flags); local_irq_restore(flags);
shift = ((unsigned char *) base)[1] & 0x0f; shift = ((unsigned char *) base)[1] & 0x0f;
*base >>= PAGE_SHIFT; *base >>= PAGE_SHIFT;
/* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7 /*
* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
* Note: shift==0xf means 4G, this is unsupported. * Note: shift==0xf means 4G, this is unsupported.
*/ */
if (shift) if (shift)
...@@ -76,17 +78,20 @@ cyrix_get_arr(unsigned int reg, unsigned long *base, ...@@ -76,17 +78,20 @@ cyrix_get_arr(unsigned int reg, unsigned long *base,
} }
} }
/*
* cyrix_get_free_region - get a free ARR.
*
* @base: the starting (base) address of the region.
* @size: the size (in bytes) of the region.
*
* Returns: the index of the region on success, else -1 on error.
*/
static int static int
cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg) cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
/* [SUMMARY] Get a free ARR.
<base> The starting (base) address of the region.
<size> The size (in bytes) of the region.
[RETURNS] The index of the region on success, else -1 on error.
*/
{ {
int i;
mtrr_type ltype;
unsigned long lbase, lsize; unsigned long lbase, lsize;
mtrr_type ltype;
int i;
switch (replace_reg) { switch (replace_reg) {
case 7: case 7:
...@@ -107,14 +112,17 @@ cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg) ...@@ -107,14 +112,17 @@ cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
cyrix_get_arr(7, &lbase, &lsize, &ltype); cyrix_get_arr(7, &lbase, &lsize, &ltype);
if (lsize == 0) if (lsize == 0)
return 7; return 7;
/* Else try ARR0-ARR6 first */ /* Else try ARR0-ARR6 first */
} else { } else {
for (i = 0; i < 7; i++) { for (i = 0; i < 7; i++) {
cyrix_get_arr(i, &lbase, &lsize, &ltype); cyrix_get_arr(i, &lbase, &lsize, &ltype);
if (lsize == 0) if (lsize == 0)
return i; return i;
} }
/* ARR0-ARR6 isn't free, try ARR7 but its size must be at least 256K */ /*
* ARR0-ARR6 isn't free
* try ARR7 but its size must be at least 256K
*/
cyrix_get_arr(i, &lbase, &lsize, &ltype); cyrix_get_arr(i, &lbase, &lsize, &ltype);
if ((lsize == 0) && (size >= 0x40)) if ((lsize == 0) && (size >= 0x40))
return i; return i;
...@@ -122,21 +130,22 @@ cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg) ...@@ -122,21 +130,22 @@ cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
return -ENOSPC; return -ENOSPC;
} }
static u32 cr4 = 0; static u32 cr4, ccr3;
static u32 ccr3;
static void prepare_set(void) static void prepare_set(void)
{ {
u32 cr0; u32 cr0;
/* Save value of CR4 and clear Page Global Enable (bit 7) */ /* Save value of CR4 and clear Page Global Enable (bit 7) */
if ( cpu_has_pge ) { if (cpu_has_pge) {
cr4 = read_cr4(); cr4 = read_cr4();
write_cr4(cr4 & ~X86_CR4_PGE); write_cr4(cr4 & ~X86_CR4_PGE);
} }
/* Disable and flush caches. Note that wbinvd flushes the TLBs as /*
a side-effect */ * Disable and flush caches.
* Note that wbinvd flushes the TLBs as a side-effect
*/
cr0 = read_cr0() | X86_CR0_CD; cr0 = read_cr0() | X86_CR0_CD;
wbinvd(); wbinvd();
write_cr0(cr0); write_cr0(cr0);
...@@ -147,22 +156,21 @@ static void prepare_set(void) ...@@ -147,22 +156,21 @@ static void prepare_set(void)
/* Cyrix ARRs - everything else was excluded at the top */ /* Cyrix ARRs - everything else was excluded at the top */
setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
} }
static void post_set(void) static void post_set(void)
{ {
/* Flush caches and TLBs */ /* Flush caches and TLBs */
wbinvd(); wbinvd();
/* Cyrix ARRs - everything else was excluded at the top */ /* Cyrix ARRs - everything else was excluded at the top */
setCx86(CX86_CCR3, ccr3); setCx86(CX86_CCR3, ccr3);
/* Enable caches */ /* Enable caches */
write_cr0(read_cr0() & 0xbfffffff); write_cr0(read_cr0() & 0xbfffffff);
/* Restore value of CR4 */ /* Restore value of CR4 */
if ( cpu_has_pge ) if (cpu_has_pge)
write_cr4(cr4); write_cr4(cr4);
} }
...@@ -178,7 +186,8 @@ static void cyrix_set_arr(unsigned int reg, unsigned long base, ...@@ -178,7 +186,8 @@ static void cyrix_set_arr(unsigned int reg, unsigned long base,
size >>= 6; size >>= 6;
size &= 0x7fff; /* make sure arr_size <= 14 */ size &= 0x7fff; /* make sure arr_size <= 14 */
for (arr_size = 0; size; arr_size++, size >>= 1) ; for (arr_size = 0; size; arr_size++, size >>= 1)
;
if (reg < 7) { if (reg < 7) {
switch (type) { switch (type) {
...@@ -215,18 +224,18 @@ static void cyrix_set_arr(unsigned int reg, unsigned long base, ...@@ -215,18 +224,18 @@ static void cyrix_set_arr(unsigned int reg, unsigned long base,
prepare_set(); prepare_set();
base <<= PAGE_SHIFT; base <<= PAGE_SHIFT;
setCx86(arr, ((unsigned char *) &base)[3]); setCx86(arr + 0, ((unsigned char *)&base)[3]);
setCx86(arr + 1, ((unsigned char *) &base)[2]); setCx86(arr + 1, ((unsigned char *)&base)[2]);
setCx86(arr + 2, (((unsigned char *) &base)[1]) | arr_size); setCx86(arr + 2, (((unsigned char *)&base)[1]) | arr_size);
setCx86(CX86_RCR_BASE + reg, arr_type); setCx86(CX86_RCR_BASE + reg, arr_type);
post_set(); post_set();
} }
typedef struct { typedef struct {
unsigned long base; unsigned long base;
unsigned long size; unsigned long size;
mtrr_type type; mtrr_type type;
} arr_state_t; } arr_state_t;
static arr_state_t arr_state[8] = { static arr_state_t arr_state[8] = {
...@@ -247,16 +256,17 @@ static void cyrix_set_all(void) ...@@ -247,16 +256,17 @@ static void cyrix_set_all(void)
setCx86(CX86_CCR0 + i, ccr_state[i]); setCx86(CX86_CCR0 + i, ccr_state[i]);
for (; i < 7; i++) for (; i < 7; i++)
setCx86(CX86_CCR4 + i, ccr_state[i]); setCx86(CX86_CCR4 + i, ccr_state[i]);
for (i = 0; i < 8; i++)
cyrix_set_arr(i, arr_state[i].base, for (i = 0; i < 8; i++) {
cyrix_set_arr(i, arr_state[i].base,
arr_state[i].size, arr_state[i].type); arr_state[i].size, arr_state[i].type);
}
post_set(); post_set();
} }
static struct mtrr_ops cyrix_mtrr_ops = { static struct mtrr_ops cyrix_mtrr_ops = {
.vendor = X86_VENDOR_CYRIX, .vendor = X86_VENDOR_CYRIX,
// .init = cyrix_arr_init,
.set_all = cyrix_set_all, .set_all = cyrix_set_all,
.set = cyrix_set_arr, .set = cyrix_set_arr,
.get = cyrix_get_arr, .get = cyrix_get_arr,
...@@ -270,5 +280,3 @@ int __init cyrix_init_mtrr(void) ...@@ -270,5 +280,3 @@ int __init cyrix_init_mtrr(void)
set_mtrr_ops(&cyrix_mtrr_ops); set_mtrr_ops(&cyrix_mtrr_ops);
return 0; return 0;
} }
//arch_initcall(cyrix_init_mtrr);
此差异已折叠。
#include <linux/init.h>
#include <linux/proc_fs.h>
#include <linux/capability.h> #include <linux/capability.h>
#include <linux/ctype.h>
#include <linux/module.h>
#include <linux/seq_file.h> #include <linux/seq_file.h>
#include <asm/uaccess.h> #include <linux/uaccess.h>
#include <linux/proc_fs.h>
#include <linux/module.h>
#include <linux/ctype.h>
#include <linux/init.h>
#define LINE_SIZE 80 #define LINE_SIZE 80
#include <asm/mtrr.h> #include <asm/mtrr.h>
#include "mtrr.h" #include "mtrr.h"
#define FILE_FCOUNT(f) (((struct seq_file *)((f)->private_data))->private) #define FILE_FCOUNT(f) (((struct seq_file *)((f)->private_data))->private)
static const char *const mtrr_strings[MTRR_NUM_TYPES] = static const char *const mtrr_strings[MTRR_NUM_TYPES] =
{ {
"uncachable", /* 0 */ "uncachable", /* 0 */
"write-combining", /* 1 */ "write-combining", /* 1 */
"?", /* 2 */ "?", /* 2 */
"?", /* 3 */ "?", /* 3 */
"write-through", /* 4 */ "write-through", /* 4 */
"write-protect", /* 5 */ "write-protect", /* 5 */
"write-back", /* 6 */ "write-back", /* 6 */
}; };
const char *mtrr_attrib_to_str(int x) const char *mtrr_attrib_to_str(int x)
...@@ -35,8 +36,8 @@ static int ...@@ -35,8 +36,8 @@ static int
mtrr_file_add(unsigned long base, unsigned long size, mtrr_file_add(unsigned long base, unsigned long size,
unsigned int type, bool increment, struct file *file, int page) unsigned int type, bool increment, struct file *file, int page)
{ {
unsigned int *fcount = FILE_FCOUNT(file);
int reg, max; int reg, max;
unsigned int *fcount = FILE_FCOUNT(file);
max = num_var_ranges; max = num_var_ranges;
if (fcount == NULL) { if (fcount == NULL) {
...@@ -61,8 +62,8 @@ static int ...@@ -61,8 +62,8 @@ static int
mtrr_file_del(unsigned long base, unsigned long size, mtrr_file_del(unsigned long base, unsigned long size,
struct file *file, int page) struct file *file, int page)
{ {
int reg;
unsigned int *fcount = FILE_FCOUNT(file); unsigned int *fcount = FILE_FCOUNT(file);
int reg;
if (!page) { if (!page) {
if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1)))
...@@ -81,13 +82,14 @@ mtrr_file_del(unsigned long base, unsigned long size, ...@@ -81,13 +82,14 @@ mtrr_file_del(unsigned long base, unsigned long size,
return reg; return reg;
} }
/* RED-PEN: seq_file can seek now. this is ignored. */ /*
* seq_file can seek but we ignore it.
*
* Format of control line:
* "base=%Lx size=%Lx type=%s" or "disable=%d"
*/
static ssize_t static ssize_t
mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos) mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos)
/* Format of control line:
"base=%Lx size=%Lx type=%s" OR:
"disable=%d"
*/
{ {
int i, err; int i, err;
unsigned long reg; unsigned long reg;
...@@ -100,15 +102,18 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos) ...@@ -100,15 +102,18 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos)
return -EPERM; return -EPERM;
if (!len) if (!len)
return -EINVAL; return -EINVAL;
memset(line, 0, LINE_SIZE); memset(line, 0, LINE_SIZE);
if (len > LINE_SIZE) if (len > LINE_SIZE)
len = LINE_SIZE; len = LINE_SIZE;
if (copy_from_user(line, buf, len - 1)) if (copy_from_user(line, buf, len - 1))
return -EFAULT; return -EFAULT;
linelen = strlen(line); linelen = strlen(line);
ptr = line + linelen - 1; ptr = line + linelen - 1;
if (linelen && *ptr == '\n') if (linelen && *ptr == '\n')
*ptr = '\0'; *ptr = '\0';
if (!strncmp(line, "disable=", 8)) { if (!strncmp(line, "disable=", 8)) {
reg = simple_strtoul(line + 8, &ptr, 0); reg = simple_strtoul(line + 8, &ptr, 0);
err = mtrr_del_page(reg, 0, 0); err = mtrr_del_page(reg, 0, 0);
...@@ -116,28 +121,35 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos) ...@@ -116,28 +121,35 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos)
return err; return err;
return len; return len;
} }
if (strncmp(line, "base=", 5)) if (strncmp(line, "base=", 5))
return -EINVAL; return -EINVAL;
base = simple_strtoull(line + 5, &ptr, 0); base = simple_strtoull(line + 5, &ptr, 0);
for (; isspace(*ptr); ++ptr) ; for (; isspace(*ptr); ++ptr)
;
if (strncmp(ptr, "size=", 5)) if (strncmp(ptr, "size=", 5))
return -EINVAL; return -EINVAL;
size = simple_strtoull(ptr + 5, &ptr, 0); size = simple_strtoull(ptr + 5, &ptr, 0);
if ((base & 0xfff) || (size & 0xfff)) if ((base & 0xfff) || (size & 0xfff))
return -EINVAL; return -EINVAL;
for (; isspace(*ptr); ++ptr) ; for (; isspace(*ptr); ++ptr)
;
if (strncmp(ptr, "type=", 5)) if (strncmp(ptr, "type=", 5))
return -EINVAL; return -EINVAL;
ptr += 5; ptr += 5;
for (; isspace(*ptr); ++ptr) ; for (; isspace(*ptr); ++ptr)
;
for (i = 0; i < MTRR_NUM_TYPES; ++i) { for (i = 0; i < MTRR_NUM_TYPES; ++i) {
if (strcmp(ptr, mtrr_strings[i])) if (strcmp(ptr, mtrr_strings[i]))
continue; continue;
base >>= PAGE_SHIFT; base >>= PAGE_SHIFT;
size >>= PAGE_SHIFT; size >>= PAGE_SHIFT;
err = err = mtrr_add_page((unsigned long)base, (unsigned long)size, i, true);
mtrr_add_page((unsigned long) base, (unsigned long) size, i,
true);
if (err < 0) if (err < 0)
return err; return err;
return len; return len;
...@@ -181,7 +193,9 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg) ...@@ -181,7 +193,9 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
case MTRRIOC32_SET_PAGE_ENTRY: case MTRRIOC32_SET_PAGE_ENTRY:
case MTRRIOC32_DEL_PAGE_ENTRY: case MTRRIOC32_DEL_PAGE_ENTRY:
case MTRRIOC32_KILL_PAGE_ENTRY: { case MTRRIOC32_KILL_PAGE_ENTRY: {
struct mtrr_sentry32 __user *s32 = (struct mtrr_sentry32 __user *)__arg; struct mtrr_sentry32 __user *s32;
s32 = (struct mtrr_sentry32 __user *)__arg;
err = get_user(sentry.base, &s32->base); err = get_user(sentry.base, &s32->base);
err |= get_user(sentry.size, &s32->size); err |= get_user(sentry.size, &s32->size);
err |= get_user(sentry.type, &s32->type); err |= get_user(sentry.type, &s32->type);
...@@ -191,7 +205,9 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg) ...@@ -191,7 +205,9 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
} }
case MTRRIOC32_GET_ENTRY: case MTRRIOC32_GET_ENTRY:
case MTRRIOC32_GET_PAGE_ENTRY: { case MTRRIOC32_GET_PAGE_ENTRY: {
struct mtrr_gentry32 __user *g32 = (struct mtrr_gentry32 __user *)__arg; struct mtrr_gentry32 __user *g32;
g32 = (struct mtrr_gentry32 __user *)__arg;
err = get_user(gentry.regnum, &g32->regnum); err = get_user(gentry.regnum, &g32->regnum);
err |= get_user(gentry.base, &g32->base); err |= get_user(gentry.base, &g32->base);
err |= get_user(gentry.size, &g32->size); err |= get_user(gentry.size, &g32->size);
...@@ -314,7 +330,7 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg) ...@@ -314,7 +330,7 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
if (err) if (err)
return err; return err;
switch(cmd) { switch (cmd) {
case MTRRIOC_GET_ENTRY: case MTRRIOC_GET_ENTRY:
case MTRRIOC_GET_PAGE_ENTRY: case MTRRIOC_GET_PAGE_ENTRY:
if (copy_to_user(arg, &gentry, sizeof gentry)) if (copy_to_user(arg, &gentry, sizeof gentry))
...@@ -323,7 +339,9 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg) ...@@ -323,7 +339,9 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
#ifdef CONFIG_COMPAT #ifdef CONFIG_COMPAT
case MTRRIOC32_GET_ENTRY: case MTRRIOC32_GET_ENTRY:
case MTRRIOC32_GET_PAGE_ENTRY: { case MTRRIOC32_GET_PAGE_ENTRY: {
struct mtrr_gentry32 __user *g32 = (struct mtrr_gentry32 __user *)__arg; struct mtrr_gentry32 __user *g32;
g32 = (struct mtrr_gentry32 __user *)__arg;
err = put_user(gentry.base, &g32->base); err = put_user(gentry.base, &g32->base);
err |= put_user(gentry.size, &g32->size); err |= put_user(gentry.size, &g32->size);
err |= put_user(gentry.regnum, &g32->regnum); err |= put_user(gentry.regnum, &g32->regnum);
...@@ -335,11 +353,10 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg) ...@@ -335,11 +353,10 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
return err; return err;
} }
static int static int mtrr_close(struct inode *ino, struct file *file)
mtrr_close(struct inode *ino, struct file *file)
{ {
int i, max;
unsigned int *fcount = FILE_FCOUNT(file); unsigned int *fcount = FILE_FCOUNT(file);
int i, max;
if (fcount != NULL) { if (fcount != NULL) {
max = num_var_ranges; max = num_var_ranges;
...@@ -359,22 +376,22 @@ static int mtrr_seq_show(struct seq_file *seq, void *offset); ...@@ -359,22 +376,22 @@ static int mtrr_seq_show(struct seq_file *seq, void *offset);
static int mtrr_open(struct inode *inode, struct file *file) static int mtrr_open(struct inode *inode, struct file *file)
{ {
if (!mtrr_if) if (!mtrr_if)
return -EIO; return -EIO;
if (!mtrr_if->get) if (!mtrr_if->get)
return -ENXIO; return -ENXIO;
return single_open(file, mtrr_seq_show, NULL); return single_open(file, mtrr_seq_show, NULL);
} }
static const struct file_operations mtrr_fops = { static const struct file_operations mtrr_fops = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.open = mtrr_open, .open = mtrr_open,
.read = seq_read, .read = seq_read,
.llseek = seq_lseek, .llseek = seq_lseek,
.write = mtrr_write, .write = mtrr_write,
.unlocked_ioctl = mtrr_ioctl, .unlocked_ioctl = mtrr_ioctl,
.compat_ioctl = mtrr_ioctl, .compat_ioctl = mtrr_ioctl,
.release = mtrr_close, .release = mtrr_close,
}; };
static int mtrr_seq_show(struct seq_file *seq, void *offset) static int mtrr_seq_show(struct seq_file *seq, void *offset)
...@@ -388,23 +405,24 @@ static int mtrr_seq_show(struct seq_file *seq, void *offset) ...@@ -388,23 +405,24 @@ static int mtrr_seq_show(struct seq_file *seq, void *offset)
max = num_var_ranges; max = num_var_ranges;
for (i = 0; i < max; i++) { for (i = 0; i < max; i++) {
mtrr_if->get(i, &base, &size, &type); mtrr_if->get(i, &base, &size, &type);
if (size == 0) if (size == 0) {
mtrr_usage_table[i] = 0; mtrr_usage_table[i] = 0;
else { continue;
if (size < (0x100000 >> PAGE_SHIFT)) {
/* less than 1MB */
factor = 'K';
size <<= PAGE_SHIFT - 10;
} else {
factor = 'M';
size >>= 20 - PAGE_SHIFT;
}
/* RED-PEN: base can be > 32bit */
len += seq_printf(seq,
"reg%02i: base=0x%06lx000 (%5luMB), size=%5lu%cB, count=%d: %s\n",
i, base, base >> (20 - PAGE_SHIFT), size, factor,
mtrr_usage_table[i], mtrr_attrib_to_str(type));
} }
if (size < (0x100000 >> PAGE_SHIFT)) {
/* less than 1MB */
factor = 'K';
size <<= PAGE_SHIFT - 10;
} else {
factor = 'M';
size >>= 20 - PAGE_SHIFT;
}
/* Base can be > 32bit */
len += seq_printf(seq, "reg%02i: base=0x%06lx000 "
"(%5luMB), size=%5lu%cB, count=%d: %s\n",
i, base, base >> (20 - PAGE_SHIFT), size,
factor, mtrr_usage_table[i],
mtrr_attrib_to_str(type));
} }
return 0; return 0;
} }
...@@ -422,6 +440,5 @@ static int __init mtrr_if_init(void) ...@@ -422,6 +440,5 @@ static int __init mtrr_if_init(void)
proc_create("mtrr", S_IWUSR | S_IRUGO, NULL, &mtrr_fops); proc_create("mtrr", S_IWUSR | S_IRUGO, NULL, &mtrr_fops);
return 0; return 0;
} }
arch_initcall(mtrr_if_init); arch_initcall(mtrr_if_init);
#endif /* CONFIG_PROC_FS */ #endif /* CONFIG_PROC_FS */
此差异已折叠。
/* /*
* local mtrr defines. * local MTRR defines.
*/ */
#include <linux/types.h> #include <linux/types.h>
...@@ -14,13 +14,12 @@ extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; ...@@ -14,13 +14,12 @@ extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
struct mtrr_ops { struct mtrr_ops {
u32 vendor; u32 vendor;
u32 use_intel_if; u32 use_intel_if;
// void (*init)(void);
void (*set)(unsigned int reg, unsigned long base, void (*set)(unsigned int reg, unsigned long base,
unsigned long size, mtrr_type type); unsigned long size, mtrr_type type);
void (*set_all)(void); void (*set_all)(void);
void (*get)(unsigned int reg, unsigned long *base, void (*get)(unsigned int reg, unsigned long *base,
unsigned long *size, mtrr_type * type); unsigned long *size, mtrr_type *type);
int (*get_free_region)(unsigned long base, unsigned long size, int (*get_free_region)(unsigned long base, unsigned long size,
int replace_reg); int replace_reg);
int (*validate_add_page)(unsigned long base, unsigned long size, int (*validate_add_page)(unsigned long base, unsigned long size,
...@@ -39,11 +38,11 @@ extern int positive_have_wrcomb(void); ...@@ -39,11 +38,11 @@ extern int positive_have_wrcomb(void);
/* library functions for processor-specific routines */ /* library functions for processor-specific routines */
struct set_mtrr_context { struct set_mtrr_context {
unsigned long flags; unsigned long flags;
unsigned long cr4val; unsigned long cr4val;
u32 deftype_lo; u32 deftype_lo;
u32 deftype_hi; u32 deftype_hi;
u32 ccr3; u32 ccr3;
}; };
void set_mtrr_done(struct set_mtrr_context *ctxt); void set_mtrr_done(struct set_mtrr_context *ctxt);
...@@ -54,10 +53,10 @@ void fill_mtrr_var_range(unsigned int index, ...@@ -54,10 +53,10 @@ void fill_mtrr_var_range(unsigned int index,
u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi); u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi);
void get_mtrr_state(void); void get_mtrr_state(void);
extern void set_mtrr_ops(struct mtrr_ops * ops); extern void set_mtrr_ops(struct mtrr_ops *ops);
extern u64 size_or_mask, size_and_mask; extern u64 size_or_mask, size_and_mask;
extern struct mtrr_ops * mtrr_if; extern struct mtrr_ops *mtrr_if;
#define is_cpu(vnd) (mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd) #define is_cpu(vnd) (mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd)
#define use_intel() (mtrr_if && mtrr_if->use_intel_if == 1) #define use_intel() (mtrr_if && mtrr_if->use_intel_if == 1)
......
#include <linux/mm.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/io.h> #include <linux/io.h>
#include <asm/mtrr.h> #include <linux/mm.h>
#include <asm/msr.h>
#include <asm/processor-cyrix.h> #include <asm/processor-cyrix.h>
#include <asm/processor-flags.h> #include <asm/processor-flags.h>
#include "mtrr.h" #include <asm/mtrr.h>
#include <asm/msr.h>
#include "mtrr.h"
/* Put the processor into a state where MTRRs can be safely set */ /* Put the processor into a state where MTRRs can be safely set */
void set_mtrr_prepare_save(struct set_mtrr_context *ctxt) void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
{ {
unsigned int cr0; unsigned int cr0;
/* Disable interrupts locally */ /* Disable interrupts locally */
local_irq_save(ctxt->flags); local_irq_save(ctxt->flags);
if (use_intel() || is_cpu(CYRIX)) { if (use_intel() || is_cpu(CYRIX)) {
/* Save value of CR4 and clear Page Global Enable (bit 7) */ /* Save value of CR4 and clear Page Global Enable (bit 7) */
if (cpu_has_pge) { if (cpu_has_pge) {
ctxt->cr4val = read_cr4(); ctxt->cr4val = read_cr4();
write_cr4(ctxt->cr4val & ~X86_CR4_PGE); write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
...@@ -33,50 +34,61 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt) ...@@ -33,50 +34,61 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
write_cr0(cr0); write_cr0(cr0);
wbinvd(); wbinvd();
if (use_intel()) if (use_intel()) {
/* Save MTRR state */ /* Save MTRR state */
rdmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi); rdmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);
else } else {
/* Cyrix ARRs - everything else were excluded at the top */ /*
* Cyrix ARRs -
* everything else were excluded at the top
*/
ctxt->ccr3 = getCx86(CX86_CCR3); ctxt->ccr3 = getCx86(CX86_CCR3);
}
} }
} }
void set_mtrr_cache_disable(struct set_mtrr_context *ctxt) void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
{ {
if (use_intel()) if (use_intel()) {
/* Disable MTRRs, and set the default type to uncached */ /* Disable MTRRs, and set the default type to uncached */
mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo & 0xf300UL, mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo & 0xf300UL,
ctxt->deftype_hi); ctxt->deftype_hi);
else if (is_cpu(CYRIX)) } else {
/* Cyrix ARRs - everything else were excluded at the top */ if (is_cpu(CYRIX)) {
setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10); /* Cyrix ARRs - everything else were excluded at the top */
setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
}
}
} }
/* Restore the processor after a set_mtrr_prepare */ /* Restore the processor after a set_mtrr_prepare */
void set_mtrr_done(struct set_mtrr_context *ctxt) void set_mtrr_done(struct set_mtrr_context *ctxt)
{ {
if (use_intel() || is_cpu(CYRIX)) { if (use_intel() || is_cpu(CYRIX)) {
/* Flush caches and TLBs */ /* Flush caches and TLBs */
wbinvd(); wbinvd();
/* Restore MTRRdefType */ /* Restore MTRRdefType */
if (use_intel()) if (use_intel()) {
/* Intel (P6) standard MTRRs */ /* Intel (P6) standard MTRRs */
mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi); mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo,
else ctxt->deftype_hi);
/* Cyrix ARRs - everything else was excluded at the top */ } else {
/*
* Cyrix ARRs -
* everything else was excluded at the top
*/
setCx86(CX86_CCR3, ctxt->ccr3); setCx86(CX86_CCR3, ctxt->ccr3);
}
/* Enable caches */ /* Enable caches */
write_cr0(read_cr0() & 0xbfffffff); write_cr0(read_cr0() & 0xbfffffff);
/* Restore value of CR4 */ /* Restore value of CR4 */
if (cpu_has_pge) if (cpu_has_pge)
write_cr4(ctxt->cr4val); write_cr4(ctxt->cr4val);
} }
/* Re-enable interrupts locally (if enabled previously) */ /* Re-enable interrupts locally (if enabled previously) */
local_irq_restore(ctxt->flags); local_irq_restore(ctxt->flags);
} }
...@@ -68,16 +68,16 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr) ...@@ -68,16 +68,16 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
/* returns the bit offset of the performance counter register */ /* returns the bit offset of the performance counter register */
switch (boot_cpu_data.x86_vendor) { switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD: case X86_VENDOR_AMD:
return (msr - MSR_K7_PERFCTR0); return msr - MSR_K7_PERFCTR0;
case X86_VENDOR_INTEL: case X86_VENDOR_INTEL:
if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
return (msr - MSR_ARCH_PERFMON_PERFCTR0); return msr - MSR_ARCH_PERFMON_PERFCTR0;
switch (boot_cpu_data.x86) { switch (boot_cpu_data.x86) {
case 6: case 6:
return (msr - MSR_P6_PERFCTR0); return msr - MSR_P6_PERFCTR0;
case 15: case 15:
return (msr - MSR_P4_BPU_PERFCTR0); return msr - MSR_P4_BPU_PERFCTR0;
} }
} }
return 0; return 0;
...@@ -92,16 +92,16 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr) ...@@ -92,16 +92,16 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
/* returns the bit offset of the event selection register */ /* returns the bit offset of the event selection register */
switch (boot_cpu_data.x86_vendor) { switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD: case X86_VENDOR_AMD:
return (msr - MSR_K7_EVNTSEL0); return msr - MSR_K7_EVNTSEL0;
case X86_VENDOR_INTEL: case X86_VENDOR_INTEL:
if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
return (msr - MSR_ARCH_PERFMON_EVENTSEL0); return msr - MSR_ARCH_PERFMON_EVENTSEL0;
switch (boot_cpu_data.x86) { switch (boot_cpu_data.x86) {
case 6: case 6:
return (msr - MSR_P6_EVNTSEL0); return msr - MSR_P6_EVNTSEL0;
case 15: case 15:
return (msr - MSR_P4_BSU_ESCR0); return msr - MSR_P4_BSU_ESCR0;
} }
} }
return 0; return 0;
...@@ -113,7 +113,7 @@ int avail_to_resrv_perfctr_nmi_bit(unsigned int counter) ...@@ -113,7 +113,7 @@ int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
{ {
BUG_ON(counter > NMI_MAX_COUNTER_BITS); BUG_ON(counter > NMI_MAX_COUNTER_BITS);
return (!test_bit(counter, perfctr_nmi_owner)); return !test_bit(counter, perfctr_nmi_owner);
} }
/* checks the an msr for availability */ /* checks the an msr for availability */
...@@ -124,7 +124,7 @@ int avail_to_resrv_perfctr_nmi(unsigned int msr) ...@@ -124,7 +124,7 @@ int avail_to_resrv_perfctr_nmi(unsigned int msr)
counter = nmi_perfctr_msr_to_bit(msr); counter = nmi_perfctr_msr_to_bit(msr);
BUG_ON(counter > NMI_MAX_COUNTER_BITS); BUG_ON(counter > NMI_MAX_COUNTER_BITS);
return (!test_bit(counter, perfctr_nmi_owner)); return !test_bit(counter, perfctr_nmi_owner);
} }
EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit); EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
...@@ -237,7 +237,7 @@ static unsigned int adjust_for_32bit_ctr(unsigned int hz) ...@@ -237,7 +237,7 @@ static unsigned int adjust_for_32bit_ctr(unsigned int hz)
*/ */
counter_val = (u64)cpu_khz * 1000; counter_val = (u64)cpu_khz * 1000;
do_div(counter_val, retval); do_div(counter_val, retval);
if (counter_val > 0x7fffffffULL) { if (counter_val > 0x7fffffffULL) {
u64 count = (u64)cpu_khz * 1000; u64 count = (u64)cpu_khz * 1000;
do_div(count, 0x7fffffffUL); do_div(count, 0x7fffffffUL);
retval = count + 1; retval = count + 1;
...@@ -251,7 +251,7 @@ static void write_watchdog_counter(unsigned int perfctr_msr, ...@@ -251,7 +251,7 @@ static void write_watchdog_counter(unsigned int perfctr_msr,
u64 count = (u64)cpu_khz * 1000; u64 count = (u64)cpu_khz * 1000;
do_div(count, nmi_hz); do_div(count, nmi_hz);
if(descr) if (descr)
pr_debug("setting %s to -0x%08Lx\n", descr, count); pr_debug("setting %s to -0x%08Lx\n", descr, count);
wrmsrl(perfctr_msr, 0 - count); wrmsrl(perfctr_msr, 0 - count);
} }
...@@ -262,7 +262,7 @@ static void write_watchdog_counter32(unsigned int perfctr_msr, ...@@ -262,7 +262,7 @@ static void write_watchdog_counter32(unsigned int perfctr_msr,
u64 count = (u64)cpu_khz * 1000; u64 count = (u64)cpu_khz * 1000;
do_div(count, nmi_hz); do_div(count, nmi_hz);
if(descr) if (descr)
pr_debug("setting %s to -0x%08Lx\n", descr, count); pr_debug("setting %s to -0x%08Lx\n", descr, count);
wrmsr(perfctr_msr, (u32)(-count), 0); wrmsr(perfctr_msr, (u32)(-count), 0);
} }
...@@ -296,7 +296,7 @@ static int setup_k7_watchdog(unsigned nmi_hz) ...@@ -296,7 +296,7 @@ static int setup_k7_watchdog(unsigned nmi_hz)
/* setup the timer */ /* setup the timer */
wrmsr(evntsel_msr, evntsel, 0); wrmsr(evntsel_msr, evntsel, 0);
write_watchdog_counter(perfctr_msr, "K7_PERFCTR0",nmi_hz); write_watchdog_counter(perfctr_msr, "K7_PERFCTR0", nmi_hz);
/* initialize the wd struct before enabling */ /* initialize the wd struct before enabling */
wd->perfctr_msr = perfctr_msr; wd->perfctr_msr = perfctr_msr;
...@@ -387,7 +387,7 @@ static int setup_p6_watchdog(unsigned nmi_hz) ...@@ -387,7 +387,7 @@ static int setup_p6_watchdog(unsigned nmi_hz)
/* setup the timer */ /* setup the timer */
wrmsr(evntsel_msr, evntsel, 0); wrmsr(evntsel_msr, evntsel, 0);
nmi_hz = adjust_for_32bit_ctr(nmi_hz); nmi_hz = adjust_for_32bit_ctr(nmi_hz);
write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0",nmi_hz); write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0", nmi_hz);
/* initialize the wd struct before enabling */ /* initialize the wd struct before enabling */
wd->perfctr_msr = perfctr_msr; wd->perfctr_msr = perfctr_msr;
...@@ -415,7 +415,7 @@ static void __kprobes p6_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz) ...@@ -415,7 +415,7 @@ static void __kprobes p6_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
apic_write(APIC_LVTPC, APIC_DM_NMI); apic_write(APIC_LVTPC, APIC_DM_NMI);
/* P6/ARCH_PERFMON has 32 bit counter write */ /* P6/ARCH_PERFMON has 32 bit counter write */
write_watchdog_counter32(wd->perfctr_msr, NULL,nmi_hz); write_watchdog_counter32(wd->perfctr_msr, NULL, nmi_hz);
} }
static const struct wd_ops p6_wd_ops = { static const struct wd_ops p6_wd_ops = {
...@@ -490,9 +490,9 @@ static int setup_p4_watchdog(unsigned nmi_hz) ...@@ -490,9 +490,9 @@ static int setup_p4_watchdog(unsigned nmi_hz)
if (smp_num_siblings == 2) { if (smp_num_siblings == 2) {
unsigned int ebx, apicid; unsigned int ebx, apicid;
ebx = cpuid_ebx(1); ebx = cpuid_ebx(1);
apicid = (ebx >> 24) & 0xff; apicid = (ebx >> 24) & 0xff;
ht_num = apicid & 1; ht_num = apicid & 1;
} else } else
#endif #endif
ht_num = 0; ht_num = 0;
...@@ -544,7 +544,7 @@ static int setup_p4_watchdog(unsigned nmi_hz) ...@@ -544,7 +544,7 @@ static int setup_p4_watchdog(unsigned nmi_hz)
} }
evntsel = P4_ESCR_EVENT_SELECT(0x3F) evntsel = P4_ESCR_EVENT_SELECT(0x3F)
| P4_ESCR_OS | P4_ESCR_OS
| P4_ESCR_USR; | P4_ESCR_USR;
cccr_val |= P4_CCCR_THRESHOLD(15) cccr_val |= P4_CCCR_THRESHOLD(15)
...@@ -612,7 +612,7 @@ static void __kprobes p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz) ...@@ -612,7 +612,7 @@ static void __kprobes p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
{ {
unsigned dummy; unsigned dummy;
/* /*
* P4 quirks: * P4 quirks:
* - An overflown perfctr will assert its interrupt * - An overflown perfctr will assert its interrupt
* until the OVF flag in its CCCR is cleared. * until the OVF flag in its CCCR is cleared.
* - LVTPC is masked on interrupt and must be * - LVTPC is masked on interrupt and must be
...@@ -662,7 +662,8 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz) ...@@ -662,7 +662,8 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz)
* NOTE: Corresponding bit = 0 in ebx indicates event present. * NOTE: Corresponding bit = 0 in ebx indicates event present.
*/ */
cpuid(10, &(eax.full), &ebx, &unused, &unused); cpuid(10, &(eax.full), &ebx, &unused, &unused);
if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) || if ((eax.split.mask_length <
(ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
(ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT)) (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
return 0; return 0;
......
...@@ -128,7 +128,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) ...@@ -128,7 +128,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
if (i < ARRAY_SIZE(x86_power_flags) && if (i < ARRAY_SIZE(x86_power_flags) &&
x86_power_flags[i]) x86_power_flags[i])
seq_printf(m, "%s%s", seq_printf(m, "%s%s",
x86_power_flags[i][0]?" ":"", x86_power_flags[i][0] ? " " : "",
x86_power_flags[i]); x86_power_flags[i]);
else else
seq_printf(m, " [%d]", i); seq_printf(m, " [%d]", i);
......
...@@ -49,17 +49,17 @@ static inline int __vmware_platform(void) ...@@ -49,17 +49,17 @@ static inline int __vmware_platform(void)
static unsigned long __vmware_get_tsc_khz(void) static unsigned long __vmware_get_tsc_khz(void)
{ {
uint64_t tsc_hz; uint64_t tsc_hz;
uint32_t eax, ebx, ecx, edx; uint32_t eax, ebx, ecx, edx;
VMWARE_PORT(GETHZ, eax, ebx, ecx, edx); VMWARE_PORT(GETHZ, eax, ebx, ecx, edx);
if (ebx == UINT_MAX) if (ebx == UINT_MAX)
return 0; return 0;
tsc_hz = eax | (((uint64_t)ebx) << 32); tsc_hz = eax | (((uint64_t)ebx) << 32);
do_div(tsc_hz, 1000); do_div(tsc_hz, 1000);
BUG_ON(tsc_hz >> 32); BUG_ON(tsc_hz >> 32);
return tsc_hz; return tsc_hz;
} }
/* /*
......
...@@ -509,15 +509,15 @@ enum bts_field { ...@@ -509,15 +509,15 @@ enum bts_field {
bts_escape = ((unsigned long)-1 & ~bts_qual_mask) bts_escape = ((unsigned long)-1 & ~bts_qual_mask)
}; };
static inline unsigned long bts_get(const char *base, enum bts_field field) static inline unsigned long bts_get(const char *base, unsigned long field)
{ {
base += (ds_cfg.sizeof_ptr_field * field); base += (ds_cfg.sizeof_ptr_field * field);
return *(unsigned long *)base; return *(unsigned long *)base;
} }
static inline void bts_set(char *base, enum bts_field field, unsigned long val) static inline void bts_set(char *base, unsigned long field, unsigned long val)
{ {
base += (ds_cfg.sizeof_ptr_field * field);; base += (ds_cfg.sizeof_ptr_field * field);
(*(unsigned long *)base) = val; (*(unsigned long *)base) = val;
} }
......
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
#include <linux/bug.h> #include <linux/bug.h>
#include <linux/nmi.h> #include <linux/nmi.h>
#include <linux/sysfs.h> #include <linux/sysfs.h>
#include <linux/ftrace.h>
#include <asm/stacktrace.h> #include <asm/stacktrace.h>
......
...@@ -218,7 +218,6 @@ bool handle_irq(unsigned irq, struct pt_regs *regs) ...@@ -218,7 +218,6 @@ bool handle_irq(unsigned irq, struct pt_regs *regs)
void fixup_irqs(void) void fixup_irqs(void)
{ {
unsigned int irq; unsigned int irq;
static int warned;
struct irq_desc *desc; struct irq_desc *desc;
for_each_irq_desc(irq, desc) { for_each_irq_desc(irq, desc) {
...@@ -236,8 +235,8 @@ void fixup_irqs(void) ...@@ -236,8 +235,8 @@ void fixup_irqs(void)
} }
if (desc->chip->set_affinity) if (desc->chip->set_affinity)
desc->chip->set_affinity(irq, affinity); desc->chip->set_affinity(irq, affinity);
else if (desc->action && !(warned++)) else if (desc->action)
printk("Cannot set affinity for irq %i\n", irq); printk_once("Cannot set affinity for irq %i\n", irq);
} }
#if 0 #if 0
......
...@@ -711,6 +711,21 @@ void __init setup_arch(char **cmdline_p) ...@@ -711,6 +711,21 @@ void __init setup_arch(char **cmdline_p)
printk(KERN_INFO "Command line: %s\n", boot_command_line); printk(KERN_INFO "Command line: %s\n", boot_command_line);
#endif #endif
strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
#ifdef CONFIG_X86_64
/*
* Must call this twice: Once just to detect whether hardware doesn't
* support NX (so that the early EHCI debug console setup can safely
* call set_fixmap(), and then again after parsing early parameters to
* honor the respective command line option.
*/
check_efer();
#endif
parse_early_param();
/* VMI may relocate the fixmap; do this before touching ioremap area */ /* VMI may relocate the fixmap; do this before touching ioremap area */
vmi_init(); vmi_init();
...@@ -793,11 +808,6 @@ void __init setup_arch(char **cmdline_p) ...@@ -793,11 +808,6 @@ void __init setup_arch(char **cmdline_p)
#endif #endif
#endif #endif
strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
#ifdef CONFIG_X86_64 #ifdef CONFIG_X86_64
check_efer(); check_efer();
#endif #endif
......
...@@ -1116,9 +1116,22 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) ...@@ -1116,9 +1116,22 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
if (is_uv_system()) if (is_uv_system())
uv_system_init(); uv_system_init();
set_mtrr_aps_delayed_init();
out: out:
preempt_enable(); preempt_enable();
} }
void arch_enable_nonboot_cpus_begin(void)
{
set_mtrr_aps_delayed_init();
}
void arch_enable_nonboot_cpus_end(void)
{
mtrr_aps_init();
}
/* /*
* Early setup to make printk work. * Early setup to make printk work.
*/ */
...@@ -1140,6 +1153,7 @@ void __init native_smp_cpus_done(unsigned int max_cpus) ...@@ -1140,6 +1153,7 @@ void __init native_smp_cpus_done(unsigned int max_cpus)
setup_ioapic_dest(); setup_ioapic_dest();
#endif #endif
check_nmi_watchdog(); check_nmi_watchdog();
mtrr_aps_init();
} }
static int __initdata setup_possible_cpus = -1; static int __initdata setup_possible_cpus = -1;
......
...@@ -76,7 +76,7 @@ char ignore_fpu_irq; ...@@ -76,7 +76,7 @@ char ignore_fpu_irq;
* F0 0F bug workaround.. We have a special link segment * F0 0F bug workaround.. We have a special link segment
* for this. * for this.
*/ */
gate_desc idt_table[256] gate_desc idt_table[NR_VECTORS]
__attribute__((__section__(".data.idt"))) = { { { { 0, 0 } } }, }; __attribute__((__section__(".data.idt"))) = { { { { 0, 0 } } }, };
#endif #endif
......
...@@ -2297,12 +2297,7 @@ static int emulator_cmpxchg_emulated(unsigned long addr, ...@@ -2297,12 +2297,7 @@ static int emulator_cmpxchg_emulated(unsigned long addr,
unsigned int bytes, unsigned int bytes,
struct kvm_vcpu *vcpu) struct kvm_vcpu *vcpu)
{ {
static int reported; printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
if (!reported) {
reported = 1;
printk(KERN_WARNING "kvm: emulating exchange as write\n");
}
#ifndef CONFIG_X86_64 #ifndef CONFIG_X86_64
/* guests cmpxchg8b have to be emulated atomically */ /* guests cmpxchg8b have to be emulated atomically */
if (bytes == 8) { if (bytes == 8) {
......
...@@ -21,7 +21,7 @@ ...@@ -21,7 +21,7 @@
#include <linux/module.h> #include <linux/module.h>
#include <linux/highmem.h> #include <linux/highmem.h>
int is_io_mapping_possible(resource_size_t base, unsigned long size) static int is_io_mapping_possible(resource_size_t base, unsigned long size)
{ {
#if !defined(CONFIG_X86_PAE) && defined(CONFIG_PHYS_ADDR_T_64BIT) #if !defined(CONFIG_X86_PAE) && defined(CONFIG_PHYS_ADDR_T_64BIT)
/* There is no way to map greater than 1 << 32 address without PAE */ /* There is no way to map greater than 1 << 32 address without PAE */
...@@ -30,7 +30,30 @@ int is_io_mapping_possible(resource_size_t base, unsigned long size) ...@@ -30,7 +30,30 @@ int is_io_mapping_possible(resource_size_t base, unsigned long size)
#endif #endif
return 1; return 1;
} }
EXPORT_SYMBOL_GPL(is_io_mapping_possible);
int iomap_create_wc(resource_size_t base, unsigned long size, pgprot_t *prot)
{
unsigned long flag = _PAGE_CACHE_WC;
int ret;
if (!is_io_mapping_possible(base, size))
return -EINVAL;
ret = io_reserve_memtype(base, base + size, &flag);
if (ret)
return ret;
*prot = __pgprot(__PAGE_KERNEL | flag);
return 0;
}
EXPORT_SYMBOL_GPL(iomap_create_wc);
void
iomap_free(resource_size_t base, unsigned long size)
{
io_free_memtype(base, base + size);
}
EXPORT_SYMBOL_GPL(iomap_free);
void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot) void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot)
{ {
......
...@@ -228,24 +228,14 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr, ...@@ -228,24 +228,14 @@ static void __iomem *__ioremap_caller(resource_size_t phys_addr,
retval = reserve_memtype(phys_addr, (u64)phys_addr + size, retval = reserve_memtype(phys_addr, (u64)phys_addr + size,
prot_val, &new_prot_val); prot_val, &new_prot_val);
if (retval) { if (retval) {
pr_debug("Warning: reserve_memtype returned %d\n", retval); printk(KERN_ERR "ioremap reserve_memtype failed %d\n", retval);
return NULL; return NULL;
} }
if (prot_val != new_prot_val) { if (prot_val != new_prot_val) {
/* if (!is_new_memtype_allowed(phys_addr, size,
* Do not fallback to certain memory types with certain prot_val, new_prot_val)) {
* requested type: printk(KERN_ERR
* - request is uc-, return cannot be write-back
* - request is uc-, return cannot be write-combine
* - request is write-combine, return cannot be write-back
*/
if ((prot_val == _PAGE_CACHE_UC_MINUS &&
(new_prot_val == _PAGE_CACHE_WB ||
new_prot_val == _PAGE_CACHE_WC)) ||
(prot_val == _PAGE_CACHE_WC &&
new_prot_val == _PAGE_CACHE_WB)) {
pr_debug(
"ioremap error for 0x%llx-0x%llx, requested 0x%lx, got 0x%lx\n", "ioremap error for 0x%llx-0x%llx, requested 0x%lx, got 0x%lx\n",
(unsigned long long)phys_addr, (unsigned long long)phys_addr,
(unsigned long long)(phys_addr + size), (unsigned long long)(phys_addr + size),
......
...@@ -822,6 +822,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages, ...@@ -822,6 +822,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
{ {
struct cpa_data cpa; struct cpa_data cpa;
int ret, cache, checkalias; int ret, cache, checkalias;
unsigned long baddr = 0;
/* /*
* Check, if we are requested to change a not supported * Check, if we are requested to change a not supported
...@@ -853,6 +854,11 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages, ...@@ -853,6 +854,11 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
*/ */
WARN_ON_ONCE(1); WARN_ON_ONCE(1);
} }
/*
* Save address for cache flush. *addr is modified in the call
* to __change_page_attr_set_clr() below.
*/
baddr = *addr;
} }
/* Must avoid aliasing mappings in the highmem code */ /* Must avoid aliasing mappings in the highmem code */
...@@ -900,7 +906,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages, ...@@ -900,7 +906,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
cpa_flush_array(addr, numpages, cache, cpa_flush_array(addr, numpages, cache,
cpa.flags, pages); cpa.flags, pages);
} else } else
cpa_flush_range(*addr, numpages, cache); cpa_flush_range(baddr, numpages, cache);
} else } else
cpa_flush_all(cache); cpa_flush_all(cache);
......
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
#include <linux/gfp.h> #include <linux/gfp.h>
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/fs.h> #include <linux/fs.h>
#include <linux/rbtree.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/processor.h> #include <asm/processor.h>
...@@ -148,11 +149,10 @@ static char *cattr_name(unsigned long flags) ...@@ -148,11 +149,10 @@ static char *cattr_name(unsigned long flags)
* areas). All the aliases have the same cache attributes of course. * areas). All the aliases have the same cache attributes of course.
* Zero attributes are represented as holes. * Zero attributes are represented as holes.
* *
* Currently the data structure is a list because the number of mappings * The data structure is a list that is also organized as an rbtree
* are expected to be relatively small. If this should be a problem * sorted on the start address of memtype range.
* it could be changed to a rbtree or similar.
* *
* memtype_lock protects the whole list. * memtype_lock protects both the linear list and rbtree.
*/ */
struct memtype { struct memtype {
...@@ -160,11 +160,53 @@ struct memtype { ...@@ -160,11 +160,53 @@ struct memtype {
u64 end; u64 end;
unsigned long type; unsigned long type;
struct list_head nd; struct list_head nd;
struct rb_node rb;
}; };
static struct rb_root memtype_rbroot = RB_ROOT;
static LIST_HEAD(memtype_list); static LIST_HEAD(memtype_list);
static DEFINE_SPINLOCK(memtype_lock); /* protects memtype list */ static DEFINE_SPINLOCK(memtype_lock); /* protects memtype list */
static struct memtype *memtype_rb_search(struct rb_root *root, u64 start)
{
struct rb_node *node = root->rb_node;
struct memtype *last_lower = NULL;
while (node) {
struct memtype *data = container_of(node, struct memtype, rb);
if (data->start < start) {
last_lower = data;
node = node->rb_right;
} else if (data->start > start) {
node = node->rb_left;
} else
return data;
}
/* Will return NULL if there is no entry with its start <= start */
return last_lower;
}
static void memtype_rb_insert(struct rb_root *root, struct memtype *data)
{
struct rb_node **new = &(root->rb_node);
struct rb_node *parent = NULL;
while (*new) {
struct memtype *this = container_of(*new, struct memtype, rb);
parent = *new;
if (data->start <= this->start)
new = &((*new)->rb_left);
else if (data->start > this->start)
new = &((*new)->rb_right);
}
rb_link_node(&data->rb, parent, new);
rb_insert_color(&data->rb, root);
}
/* /*
* Does intersection of PAT memory type and MTRR memory type and returns * Does intersection of PAT memory type and MTRR memory type and returns
* the resulting memory type as PAT understands it. * the resulting memory type as PAT understands it.
...@@ -218,9 +260,6 @@ chk_conflict(struct memtype *new, struct memtype *entry, unsigned long *type) ...@@ -218,9 +260,6 @@ chk_conflict(struct memtype *new, struct memtype *entry, unsigned long *type)
return -EBUSY; return -EBUSY;
} }
static struct memtype *cached_entry;
static u64 cached_start;
static int pat_pagerange_is_ram(unsigned long start, unsigned long end) static int pat_pagerange_is_ram(unsigned long start, unsigned long end)
{ {
int ram_page = 0, not_rampage = 0; int ram_page = 0, not_rampage = 0;
...@@ -249,63 +288,61 @@ static int pat_pagerange_is_ram(unsigned long start, unsigned long end) ...@@ -249,63 +288,61 @@ static int pat_pagerange_is_ram(unsigned long start, unsigned long end)
} }
/* /*
* For RAM pages, mark the pages as non WB memory type using * For RAM pages, we use page flags to mark the pages with appropriate type.
* PageNonWB (PG_arch_1). We allow only one set_memory_uc() or * Here we do two pass:
* set_memory_wc() on a RAM page at a time before marking it as WB again. * - Find the memtype of all the pages in the range, look for any conflicts
* This is ok, because only one driver will be owning the page and * - In case of no conflicts, set the new memtype for pages in the range
* doing set_memory_*() calls.
* *
* For now, we use PageNonWB to track that the RAM page is being mapped * Caller must hold memtype_lock for atomicity.
* as non WB. In future, we will have to use one more flag
* (or some other mechanism in page_struct) to distinguish between
* UC and WC mapping.
*/ */
static int reserve_ram_pages_type(u64 start, u64 end, unsigned long req_type, static int reserve_ram_pages_type(u64 start, u64 end, unsigned long req_type,
unsigned long *new_type) unsigned long *new_type)
{ {
struct page *page; struct page *page;
u64 pfn, end_pfn; u64 pfn;
if (req_type == _PAGE_CACHE_UC) {
/* We do not support strong UC */
WARN_ON_ONCE(1);
req_type = _PAGE_CACHE_UC_MINUS;
}
for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) { for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) {
page = pfn_to_page(pfn); unsigned long type;
if (page_mapped(page) || PageNonWB(page))
goto out;
SetPageNonWB(page); page = pfn_to_page(pfn);
type = get_page_memtype(page);
if (type != -1) {
printk(KERN_INFO "reserve_ram_pages_type failed "
"0x%Lx-0x%Lx, track 0x%lx, req 0x%lx\n",
start, end, type, req_type);
if (new_type)
*new_type = type;
return -EBUSY;
}
} }
return 0;
out: if (new_type)
end_pfn = pfn; *new_type = req_type;
for (pfn = (start >> PAGE_SHIFT); pfn < end_pfn; ++pfn) {
for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) {
page = pfn_to_page(pfn); page = pfn_to_page(pfn);
ClearPageNonWB(page); set_page_memtype(page, req_type);
} }
return 0;
return -EINVAL;
} }
static int free_ram_pages_type(u64 start, u64 end) static int free_ram_pages_type(u64 start, u64 end)
{ {
struct page *page; struct page *page;
u64 pfn, end_pfn; u64 pfn;
for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) { for (pfn = (start >> PAGE_SHIFT); pfn < (end >> PAGE_SHIFT); ++pfn) {
page = pfn_to_page(pfn); page = pfn_to_page(pfn);
if (page_mapped(page) || !PageNonWB(page)) set_page_memtype(page, -1);
goto out;
ClearPageNonWB(page);
} }
return 0; return 0;
out:
end_pfn = pfn;
for (pfn = (start >> PAGE_SHIFT); pfn < end_pfn; ++pfn) {
page = pfn_to_page(pfn);
SetPageNonWB(page);
}
return -EINVAL;
} }
/* /*
...@@ -339,6 +376,8 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type, ...@@ -339,6 +376,8 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
if (new_type) { if (new_type) {
if (req_type == -1) if (req_type == -1)
*new_type = _PAGE_CACHE_WB; *new_type = _PAGE_CACHE_WB;
else if (req_type == _PAGE_CACHE_WC)
*new_type = _PAGE_CACHE_UC_MINUS;
else else
*new_type = req_type & _PAGE_CACHE_MASK; *new_type = req_type & _PAGE_CACHE_MASK;
} }
...@@ -364,11 +403,16 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type, ...@@ -364,11 +403,16 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
*new_type = actual_type; *new_type = actual_type;
is_range_ram = pat_pagerange_is_ram(start, end); is_range_ram = pat_pagerange_is_ram(start, end);
if (is_range_ram == 1) if (is_range_ram == 1) {
return reserve_ram_pages_type(start, end, req_type,
new_type); spin_lock(&memtype_lock);
else if (is_range_ram < 0) err = reserve_ram_pages_type(start, end, req_type, new_type);
spin_unlock(&memtype_lock);
return err;
} else if (is_range_ram < 0) {
return -EINVAL; return -EINVAL;
}
new = kmalloc(sizeof(struct memtype), GFP_KERNEL); new = kmalloc(sizeof(struct memtype), GFP_KERNEL);
if (!new) if (!new)
...@@ -380,17 +424,11 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type, ...@@ -380,17 +424,11 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
spin_lock(&memtype_lock); spin_lock(&memtype_lock);
if (cached_entry && start >= cached_start)
entry = cached_entry;
else
entry = list_entry(&memtype_list, struct memtype, nd);
/* Search for existing mapping that overlaps the current range */ /* Search for existing mapping that overlaps the current range */
where = NULL; where = NULL;
list_for_each_entry_continue(entry, &memtype_list, nd) { list_for_each_entry(entry, &memtype_list, nd) {
if (end <= entry->start) { if (end <= entry->start) {
where = entry->nd.prev; where = entry->nd.prev;
cached_entry = list_entry(where, struct memtype, nd);
break; break;
} else if (start <= entry->start) { /* end > entry->start */ } else if (start <= entry->start) { /* end > entry->start */
err = chk_conflict(new, entry, new_type); err = chk_conflict(new, entry, new_type);
...@@ -398,8 +436,6 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type, ...@@ -398,8 +436,6 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
dprintk("Overlap at 0x%Lx-0x%Lx\n", dprintk("Overlap at 0x%Lx-0x%Lx\n",
entry->start, entry->end); entry->start, entry->end);
where = entry->nd.prev; where = entry->nd.prev;
cached_entry = list_entry(where,
struct memtype, nd);
} }
break; break;
} else if (start < entry->end) { /* start > entry->start */ } else if (start < entry->end) { /* start > entry->start */
...@@ -407,8 +443,6 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type, ...@@ -407,8 +443,6 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
if (!err) { if (!err) {
dprintk("Overlap at 0x%Lx-0x%Lx\n", dprintk("Overlap at 0x%Lx-0x%Lx\n",
entry->start, entry->end); entry->start, entry->end);
cached_entry = list_entry(entry->nd.prev,
struct memtype, nd);
/* /*
* Move to right position in the linked * Move to right position in the linked
...@@ -436,13 +470,13 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type, ...@@ -436,13 +470,13 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
return err; return err;
} }
cached_start = start;
if (where) if (where)
list_add(&new->nd, where); list_add(&new->nd, where);
else else
list_add_tail(&new->nd, &memtype_list); list_add_tail(&new->nd, &memtype_list);
memtype_rb_insert(&memtype_rbroot, new);
spin_unlock(&memtype_lock); spin_unlock(&memtype_lock);
dprintk("reserve_memtype added 0x%Lx-0x%Lx, track %s, req %s, ret %s\n", dprintk("reserve_memtype added 0x%Lx-0x%Lx, track %s, req %s, ret %s\n",
...@@ -454,7 +488,7 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type, ...@@ -454,7 +488,7 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
int free_memtype(u64 start, u64 end) int free_memtype(u64 start, u64 end)
{ {
struct memtype *entry; struct memtype *entry, *saved_entry;
int err = -EINVAL; int err = -EINVAL;
int is_range_ram; int is_range_ram;
...@@ -466,23 +500,58 @@ int free_memtype(u64 start, u64 end) ...@@ -466,23 +500,58 @@ int free_memtype(u64 start, u64 end)
return 0; return 0;
is_range_ram = pat_pagerange_is_ram(start, end); is_range_ram = pat_pagerange_is_ram(start, end);
if (is_range_ram == 1) if (is_range_ram == 1) {
return free_ram_pages_type(start, end);
else if (is_range_ram < 0) spin_lock(&memtype_lock);
err = free_ram_pages_type(start, end);
spin_unlock(&memtype_lock);
return err;
} else if (is_range_ram < 0) {
return -EINVAL; return -EINVAL;
}
spin_lock(&memtype_lock); spin_lock(&memtype_lock);
list_for_each_entry(entry, &memtype_list, nd) {
entry = memtype_rb_search(&memtype_rbroot, start);
if (unlikely(entry == NULL))
goto unlock_ret;
/*
* Saved entry points to an entry with start same or less than what
* we searched for. Now go through the list in both directions to look
* for the entry that matches with both start and end, with list stored
* in sorted start address
*/
saved_entry = entry;
list_for_each_entry_from(entry, &memtype_list, nd) {
if (entry->start == start && entry->end == end) { if (entry->start == start && entry->end == end) {
if (cached_entry == entry || cached_start == start) rb_erase(&entry->rb, &memtype_rbroot);
cached_entry = NULL; list_del(&entry->nd);
kfree(entry);
err = 0;
break;
} else if (entry->start > start) {
break;
}
}
if (!err)
goto unlock_ret;
entry = saved_entry;
list_for_each_entry_reverse(entry, &memtype_list, nd) {
if (entry->start == start && entry->end == end) {
rb_erase(&entry->rb, &memtype_rbroot);
list_del(&entry->nd); list_del(&entry->nd);
kfree(entry); kfree(entry);
err = 0; err = 0;
break; break;
} else if (entry->start < start) {
break;
} }
} }
unlock_ret:
spin_unlock(&memtype_lock); spin_unlock(&memtype_lock);
if (err) { if (err) {
...@@ -496,6 +565,101 @@ int free_memtype(u64 start, u64 end) ...@@ -496,6 +565,101 @@ int free_memtype(u64 start, u64 end)
} }
/**
* lookup_memtype - Looksup the memory type for a physical address
* @paddr: physical address of which memory type needs to be looked up
*
* Only to be called when PAT is enabled
*
* Returns _PAGE_CACHE_WB, _PAGE_CACHE_WC, _PAGE_CACHE_UC_MINUS or
* _PAGE_CACHE_UC
*/
static unsigned long lookup_memtype(u64 paddr)
{
int rettype = _PAGE_CACHE_WB;
struct memtype *entry;
if (is_ISA_range(paddr, paddr + PAGE_SIZE - 1))
return rettype;
if (pat_pagerange_is_ram(paddr, paddr + PAGE_SIZE)) {
struct page *page;
spin_lock(&memtype_lock);
page = pfn_to_page(paddr >> PAGE_SHIFT);
rettype = get_page_memtype(page);
spin_unlock(&memtype_lock);
/*
* -1 from get_page_memtype() implies RAM page is in its
* default state and not reserved, and hence of type WB
*/
if (rettype == -1)
rettype = _PAGE_CACHE_WB;
return rettype;
}
spin_lock(&memtype_lock);
entry = memtype_rb_search(&memtype_rbroot, paddr);
if (entry != NULL)
rettype = entry->type;
else
rettype = _PAGE_CACHE_UC_MINUS;
spin_unlock(&memtype_lock);
return rettype;
}
/**
* io_reserve_memtype - Request a memory type mapping for a region of memory
* @start: start (physical address) of the region
* @end: end (physical address) of the region
* @type: A pointer to memtype, with requested type. On success, requested
* or any other compatible type that was available for the region is returned
*
* On success, returns 0
* On failure, returns non-zero
*/
int io_reserve_memtype(resource_size_t start, resource_size_t end,
unsigned long *type)
{
resource_size_t size = end - start;
unsigned long req_type = *type;
unsigned long new_type;
int ret;
WARN_ON_ONCE(iomem_map_sanity_check(start, size));
ret = reserve_memtype(start, end, req_type, &new_type);
if (ret)
goto out_err;
if (!is_new_memtype_allowed(start, size, req_type, new_type))
goto out_free;
if (kernel_map_sync_memtype(start, size, new_type) < 0)
goto out_free;
*type = new_type;
return 0;
out_free:
free_memtype(start, end);
ret = -EBUSY;
out_err:
return ret;
}
/**
* io_free_memtype - Release a memory type mapping for a region of memory
* @start: start (physical address) of the region
* @end: end (physical address) of the region
*/
void io_free_memtype(resource_size_t start, resource_size_t end)
{
free_memtype(start, end);
}
pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
unsigned long size, pgprot_t vma_prot) unsigned long size, pgprot_t vma_prot)
{ {
...@@ -577,7 +741,7 @@ int kernel_map_sync_memtype(u64 base, unsigned long size, unsigned long flags) ...@@ -577,7 +741,7 @@ int kernel_map_sync_memtype(u64 base, unsigned long size, unsigned long flags)
{ {
unsigned long id_sz; unsigned long id_sz;
if (!pat_enabled || base >= __pa(high_memory)) if (base >= __pa(high_memory))
return 0; return 0;
id_sz = (__pa(high_memory) < base + size) ? id_sz = (__pa(high_memory) < base + size) ?
...@@ -612,11 +776,29 @@ static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t *vma_prot, ...@@ -612,11 +776,29 @@ static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t *vma_prot,
is_ram = pat_pagerange_is_ram(paddr, paddr + size); is_ram = pat_pagerange_is_ram(paddr, paddr + size);
/* /*
* reserve_pfn_range() doesn't support RAM pages. Maintain the current * reserve_pfn_range() for RAM pages. We do not refcount to keep
* behavior with RAM pages by returning success. * track of number of mappings of RAM pages. We can assert that
* the type requested matches the type of first page in the range.
*/ */
if (is_ram != 0) if (is_ram) {
if (!pat_enabled)
return 0;
flags = lookup_memtype(paddr);
if (want_flags != flags) {
printk(KERN_WARNING
"%s:%d map pfn RAM range req %s for %Lx-%Lx, got %s\n",
current->comm, current->pid,
cattr_name(want_flags),
(unsigned long long)paddr,
(unsigned long long)(paddr + size),
cattr_name(flags));
*vma_prot = __pgprot((pgprot_val(*vma_prot) &
(~_PAGE_CACHE_MASK)) |
flags);
}
return 0; return 0;
}
ret = reserve_memtype(paddr, paddr + size, want_flags, &flags); ret = reserve_memtype(paddr, paddr + size, want_flags, &flags);
if (ret) if (ret)
...@@ -678,14 +860,6 @@ int track_pfn_vma_copy(struct vm_area_struct *vma) ...@@ -678,14 +860,6 @@ int track_pfn_vma_copy(struct vm_area_struct *vma)
unsigned long vma_size = vma->vm_end - vma->vm_start; unsigned long vma_size = vma->vm_end - vma->vm_start;
pgprot_t pgprot; pgprot_t pgprot;
if (!pat_enabled)
return 0;
/*
* For now, only handle remap_pfn_range() vmas where
* is_linear_pfn_mapping() == TRUE. Handling of
* vm_insert_pfn() is TBD.
*/
if (is_linear_pfn_mapping(vma)) { if (is_linear_pfn_mapping(vma)) {
/* /*
* reserve the whole chunk covered by vma. We need the * reserve the whole chunk covered by vma. We need the
...@@ -713,23 +887,24 @@ int track_pfn_vma_copy(struct vm_area_struct *vma) ...@@ -713,23 +887,24 @@ int track_pfn_vma_copy(struct vm_area_struct *vma)
int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t *prot, int track_pfn_vma_new(struct vm_area_struct *vma, pgprot_t *prot,
unsigned long pfn, unsigned long size) unsigned long pfn, unsigned long size)
{ {
unsigned long flags;
resource_size_t paddr; resource_size_t paddr;
unsigned long vma_size = vma->vm_end - vma->vm_start; unsigned long vma_size = vma->vm_end - vma->vm_start;
if (!pat_enabled)
return 0;
/*
* For now, only handle remap_pfn_range() vmas where
* is_linear_pfn_mapping() == TRUE. Handling of
* vm_insert_pfn() is TBD.
*/
if (is_linear_pfn_mapping(vma)) { if (is_linear_pfn_mapping(vma)) {
/* reserve the whole chunk starting from vm_pgoff */ /* reserve the whole chunk starting from vm_pgoff */
paddr = (resource_size_t)vma->vm_pgoff << PAGE_SHIFT; paddr = (resource_size_t)vma->vm_pgoff << PAGE_SHIFT;
return reserve_pfn_range(paddr, vma_size, prot, 0); return reserve_pfn_range(paddr, vma_size, prot, 0);
} }
if (!pat_enabled)
return 0;
/* for vm_insert_pfn and friends, we set prot based on lookup */
flags = lookup_memtype(pfn << PAGE_SHIFT);
*prot = __pgprot((pgprot_val(vma->vm_page_prot) & (~_PAGE_CACHE_MASK)) |
flags);
return 0; return 0;
} }
...@@ -744,14 +919,6 @@ void untrack_pfn_vma(struct vm_area_struct *vma, unsigned long pfn, ...@@ -744,14 +919,6 @@ void untrack_pfn_vma(struct vm_area_struct *vma, unsigned long pfn,
resource_size_t paddr; resource_size_t paddr;
unsigned long vma_size = vma->vm_end - vma->vm_start; unsigned long vma_size = vma->vm_end - vma->vm_start;
if (!pat_enabled)
return;
/*
* For now, only handle remap_pfn_range() vmas where
* is_linear_pfn_mapping() == TRUE. Handling of
* vm_insert_pfn() is TBD.
*/
if (is_linear_pfn_mapping(vma)) { if (is_linear_pfn_mapping(vma)) {
/* free the whole chunk starting from vm_pgoff */ /* free the whole chunk starting from vm_pgoff */
paddr = (resource_size_t)vma->vm_pgoff << PAGE_SHIFT; paddr = (resource_size_t)vma->vm_pgoff << PAGE_SHIFT;
......
...@@ -242,7 +242,7 @@ static void __restore_processor_state(struct saved_context *ctxt) ...@@ -242,7 +242,7 @@ static void __restore_processor_state(struct saved_context *ctxt)
fix_processor_context(); fix_processor_context();
do_fpu_end(); do_fpu_end();
mtrr_ap_init(); mtrr_bp_restore();
#ifdef CONFIG_X86_OLD_MCE #ifdef CONFIG_X86_OLD_MCE
mcheck_init(&boot_cpu_data); mcheck_init(&boot_cpu_data);
......
此差异已折叠。
...@@ -99,7 +99,7 @@ enum pageflags { ...@@ -99,7 +99,7 @@ enum pageflags {
#ifdef CONFIG_HAVE_MLOCKED_PAGE_BIT #ifdef CONFIG_HAVE_MLOCKED_PAGE_BIT
PG_mlocked, /* Page is vma mlocked */ PG_mlocked, /* Page is vma mlocked */
#endif #endif
#ifdef CONFIG_IA64_UNCACHED_ALLOCATOR #ifdef CONFIG_ARCH_USES_PG_UNCACHED
PG_uncached, /* Page has been mapped as uncached */ PG_uncached, /* Page has been mapped as uncached */
#endif #endif
__NR_PAGEFLAGS, __NR_PAGEFLAGS,
...@@ -257,7 +257,7 @@ PAGEFLAG_FALSE(Mlocked) ...@@ -257,7 +257,7 @@ PAGEFLAG_FALSE(Mlocked)
SETPAGEFLAG_NOOP(Mlocked) TESTCLEARFLAG_FALSE(Mlocked) SETPAGEFLAG_NOOP(Mlocked) TESTCLEARFLAG_FALSE(Mlocked)
#endif #endif
#ifdef CONFIG_IA64_UNCACHED_ALLOCATOR #ifdef CONFIG_ARCH_USES_PG_UNCACHED
PAGEFLAG(Uncached, uncached) PAGEFLAG(Uncached, uncached)
#else #else
PAGEFLAG_FALSE(Uncached) PAGEFLAG_FALSE(Uncached)
......
此差异已折叠。
此差异已折叠。
...@@ -153,7 +153,7 @@ config MEMORY_HOTREMOVE ...@@ -153,7 +153,7 @@ config MEMORY_HOTREMOVE
# #
config PAGEFLAGS_EXTENDED config PAGEFLAGS_EXTENDED
def_bool y def_bool y
depends on 64BIT || SPARSEMEM_VMEMMAP || !NUMA || !SPARSEMEM depends on 64BIT || SPARSEMEM_VMEMMAP || !SPARSEMEM
# Heavily threaded applications may benefit from splitting the mm-wide # Heavily threaded applications may benefit from splitting the mm-wide
# page_table_lock, so that faults on different parts of the user address # page_table_lock, so that faults on different parts of the user address
......
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