Add HPRE enabling on Hi1620 CS FPGA

Feature or Bugfix:Feature
Signed-off-by: Nxuzaibo <xuzaibo@huawei.com>
Reviewed-by: Nwangzhou <wangzhou1@hisilicon.com>
Reviewed-by: Nfanghao <fanghao11@huawei.com>

drivers/crypto/hisilicon/hpre/hpre_crypto.c

@@ -12,9 +12,6 @@
 
 #include "hpre.h"
 
-static DEFINE_MUTEX(algs_lock);
-static unsigned int active_devs;
-
 struct hpre_ctx;
 
 #define GET_DEV(ctx)		((ctx)->qp->qm->pdev->dev)
@@ -1035,25 +1032,15 @@ int hpre_algs_register(void)
 {
 	int ret = 0;
 
-	mutex_lock(&algs_lock);
-	if (++active_devs == 1) {
-		rsa.base.cra_flags = 0;
-		ret = crypto_register_akcipher(&rsa);
-		if (ret)
-			goto unlock;
-		ret = crypto_register_kpp(&dh);
-	}
-unlock:
-	mutex_unlock(&algs_lock);
-	return ret;
+	rsa.base.cra_flags = 0;
+	ret = crypto_register_akcipher(&rsa);
+	if (ret)
+		return ret;
+	return crypto_register_kpp(&dh);
 }
 
 void hpre_algs_unregister(void)
 {
-	mutex_lock(&algs_lock);
-	if (--active_devs == 0) {
-		crypto_unregister_akcipher(&rsa);
-		crypto_unregister_kpp(&dh);
-	}
-	mutex_unlock(&algs_lock);
+	crypto_unregister_akcipher(&rsa);
+	crypto_unregister_kpp(&dh);
 }

drivers/crypto/hisilicon/hpre/hpre_main.c

@@ -11,7 +11,9 @@
 #define HPRE_VF_NUM			63
 #define HPRE_QUEUE_NUM_V1		4096
 #define HPRE_QUEUE_NUM_V2		1024
-
+#define HPRE_CLUSTERS_NUM		4
+#define HPRE_CLUSTER_CORES		4
+#define HPRE_QM_ABNML_INT_MASK		0x100004
 #define HPRE_COMM_CNT_CLR_CE		0x0
 #define HPRE_FSM_MAX_CNT		0x301008
 #define HPRE_VFG_AXQOS			0x30100c
@@ -41,7 +43,6 @@
 #define HPRE_CORE_INI_CFG		0x302020
 #define HPRE_CORE_INI_STATUS		0x302080
 
-
 LIST_HEAD(hisi_hpre_list);
 DEFINE_MUTEX(hisi_hpre_list_lock);
 
@@ -68,8 +69,9 @@ static inline void hisi_hpre_remove_from_list(struct hisi_hpre *hisi_hpre)
 
 static int hisi_hpre_set_user_domain_and_cache(struct hisi_hpre *hisi_hpre)
 {
-	int ret;
+	int ret, i;
 	u32 val;
+	unsigned long offset;
 
 	writel(0x1, hisi_hpre->qm.io_base + HPRE_TYPES_ENB);
 	writel(0x0, hisi_hpre->qm.io_base + HPRE_VFG_AXQOS);
@@ -80,40 +82,33 @@ static int hisi_hpre_set_user_domain_and_cache(struct hisi_hpre *hisi_hpre)
 	writel(0x0, hisi_hpre->qm.io_base + HPRE_POISON_BYPASS);
 	writel(0x0, hisi_hpre->qm.io_base + HPRE_COMM_CNT_CLR_CE);
 	writel(0x0, hisi_hpre->qm.io_base + HPRE_ECC_BYPASS);
+
 #ifndef CONFIG_ARM_SMMU_V3
 	writel(0x1, hisi_hpre->qm.io_base + HPRE_ARUSR_CFG);
 	writel(0x1, hisi_hpre->qm.io_base + HPRE_AWUSR_CFG);
-#else
-	writel(0x203, hisi_hpre->qm.io_base + HPRE_ARUSR_CFG);
-	writel(0x203, hisi_hpre->qm.io_base + HPRE_AWUSR_CFG);
 #endif
 	writel(0x1, hisi_hpre->qm.io_base + HPRE_RDCHN_INI_CFG);
 	ret = readl_relaxed_poll_timeout(hisi_hpre->qm.io_base +
-			HPRE_RDCHN_INI_ST, val, val & BIT(0), 10, 1000);
+					 HPRE_RDCHN_INI_ST, val,
+					 val & BIT(0), 10, 1000);
 	if (ret) {
 		pr_err("\nHPRE:INI ST TIMEOUT");
 		return -ETIMEDOUT;
 	}
-	/* First cluster initiating */
-	writel(0xf, hisi_hpre->qm.io_base + HPRE_CORE_ENB);
-	writel(0x1, hisi_hpre->qm.io_base + HPRE_CORE_INI_CFG);
-	ret = readl_relaxed_poll_timeout(hisi_hpre->qm.io_base +
-					 HPRE_CORE_INI_STATUS,
-					 val, ((val & 0xf) == 0xf), 10, 1000);
-	if (ret) {
-		pr_err("\nHPRE:CLUSTER 1 INI ST STATUS timeout");
-		return -ETIMEDOUT;
-	}
-	/* Second cluster initiating, reg's address is 0x1000 more*/
-	/* writel(0xf, hpre->io_base + 0x1000 + HPRE_CORE_ENB);*/
-	writel(0x0, hisi_hpre->qm.io_base + 0x1000 + HPRE_CORE_ENB);
-	writel(0x1, hisi_hpre->qm.io_base + 0x1000 + HPRE_CORE_INI_CFG);
-	ret = readl_relaxed_poll_timeout(hisi_hpre->qm.io_base + 0x1000 +
-				    HPRE_CORE_INI_STATUS,
-				    val, ((val & 0xf) == 0xf), 10, 1000);
-	if (ret) {
-		pr_err("\nHPRE:CLUSTER 2 INI ST STATUS timeout");
-		return -ETIMEDOUT;
+	for (i = 0; i < HPRE_CLUSTERS_NUM; i++) {
+		offset = i * 0x1000;
+
+		/* clusters initiating */
+		writel(0xf, hisi_hpre->qm.io_base + offset + HPRE_CORE_ENB);
+		writel(0x1, hisi_hpre->qm.io_base + offset + HPRE_CORE_INI_CFG);
+		ret = readl_relaxed_poll_timeout(hisi_hpre->qm.io_base +
+						 offset + HPRE_CORE_INI_STATUS,
+						 val, ((val & 0xf) == 0xf),
+						 10, 1000);
+		if (ret) {
+			pr_err("\nHPRE:CLUSTER %d INI ST STATUS timeout!", i);
+			return -ETIMEDOUT;
+		}
 	}
 
 	return ret;
@@ -125,10 +120,7 @@ static int hisi_hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	struct qm_info *qm;
 	int ret;
 	u8 rev_id = 0;
-
-#ifdef CONFIG_ARM_SMMU_V3
 	u32 val;
-#endif
 
 	hisi_hpre = devm_kzalloc(&pdev->dev, sizeof(*hisi_hpre), GFP_KERNEL);
 	if (!hisi_hpre)
@@ -197,6 +189,10 @@ static int hisi_hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 		writel_relaxed(0xffffffff,
 			HPRE_ADDR(QM_PEH_AXUSER_CFG_ENABLE));
 #endif
+		val = readl_relaxed(HPRE_ADDR(HPRE_QM_ABNML_INT_MASK));
+		val |= (1 << 6);
+		writel_relaxed(val, HPRE_ADDR(HPRE_QM_ABNML_INT_MASK));
+
 		ret = hisi_qm_mem_start(qm);
 		if (ret)
 			goto err_with_qm_init;
@@ -212,8 +208,6 @@ static int hisi_hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	if (ret)
 		goto err_with_qm_init;
 
-	/* todo: exception irq handler register, ES did not support */
-
 	return 0;
 
 err_with_qm_init:

samples/warpdrive/drv/hisi_hpre_udrv.c

@@ -285,7 +285,7 @@ int hpre_set_queue_dio(struct wd_queue *q)
 		HPRE_SQE_SIZE * HPRE_EQ_DEPTH + HPRE_CQE_SIZE * HPRE_EQ_DEPTH,
 		PROT_READ | PROT_WRITE, MAP_SHARED, q->fd, 4096);
 	if (vaddr <= 0) {
-		ret = (intptr_t)vaddr;
+		ret = -EIO;
 		goto err_with_info;
 	}
 	info->sq_base = vaddr;
@@ -296,7 +296,7 @@ int hpre_set_queue_dio(struct wd_queue *q)
 	vaddr = mmap(NULL, HPRE_IOMEM_SIZE,
 		PROT_READ | PROT_WRITE, MAP_SHARED, q->fd, 0);
 	if (vaddr <= 0) {
-		ret = (intptr_t)vaddr;
+		ret = -EIO;
 		goto err_with_scq;
 	}
 
@@ -315,10 +315,18 @@ int hpre_set_queue_dio(struct wd_queue *q)
 	info->cqc_phase = 1;
 	info->is_sq_full = 0;
 
+	info->recv = malloc(HPRE_EQ_DEPTH * sizeof(struct wd_rsa_msg));
+	if (!info->recv) {
+		ret = -ENOMEM;
+		goto err_with_scq;
+	}
+	memset(info->recv, 0, HPRE_EQ_DEPTH * sizeof(struct wd_rsa_msg));
 	ret = hpre_init_cache_buf(q);
 	if (ret)
 		goto init_cache_fail;
 
+	return ret;
+
 init_cache_fail:
 	(void)hpre_uninit_cache_buf(q);
 err_with_scq:
@@ -343,6 +351,7 @@ void hpre_unset_queue_dio(struct wd_queue *q)
 		       HPRE_IOMEM_SIZE);
 
 	munmap(info->sq_base, (HPRE_CQE_SIZE + HPRE_SQE_SIZE) * HPRE_EQ_DEPTH);
+	free(info->recv);
 	free(info);
 	q->priv = NULL;
 }

samples/warpdrive/test/test_hisi_hpre.c

@@ -17,8 +17,6 @@ static int key_bits = 4096;
 #define TEST_THRDS_NUM		dbg_thrd_num
 static pthread_t request_release_q_thrds[TEST_MAX_THRD];
 
-#define DEBUG_NOIOMMU
-
 #define ASIZE			(16 * 4096)
 
 #define SYS_ERR_COND(cond, msg)		\
@@ -136,14 +134,11 @@ void  *test_q_mng_thread(void *data)
 {
 	struct wd_queue q;
 	int ret;
-	int container;
 
-	container = *(int *)data;
 	memset(&q, 0, sizeof(q));
 	q.capa.alg = "rsa";
 	q.capa.throughput = 10;
 	q.capa.latency = 10;
-	q.container = container;
 	while (1) {
 		ret = wd_request_queue(&q);
 		if (ret) {
@@ -171,8 +166,6 @@ int main(int argc, char *argv[])
 	void *ctx = NULL;
 	struct wd_rsa_ctx_setup setup;
 	struct wd_rsa_op_data opdata;
-	int is_new_container = 0;
-	int container = 0;
 
 	if (argv[1]) {
 		key_bits = strtoul(argv[1], NULL, 10);
@@ -196,21 +189,10 @@ int main(int argc, char *argv[])
 		TEST_THRDS_NUM = strtoul(argv[4], NULL, 10);
 	else
 		TEST_THRDS_NUM = 0;
-	if (argv[5])
-		is_new_container = strtoul(argv[5], NULL, 10);
-	else
-		is_new_container = 0;
 	if (TEST_THRDS_NUM > TEST_MAX_THRD)
 		TEST_THRDS_NUM = TEST_MAX_THRD;
 	pkt_len = (RSA_KEY_BITS >> 3);
 
-	if (is_new_container) {
-		container = open("/dev/vfio/vfio", O_RDWR);
-		if (container < 0) {
-			WD_ERR("Create VFIO container fail!\n");
-			return -ENODEV;
-		}
-	}
 	memset(&q, 0, sizeof(q));
 	q.capa.alg = "rsa";
 	q.capa.throughput = 10;
@@ -218,7 +200,7 @@ int main(int argc, char *argv[])
 
 	for (i = 0; i < TEST_THRDS_NUM; i++) {
 		ret = pthread_create(&request_release_q_thrds[i], NULL,
-				     test_q_mng_thread, &container);
+				     test_q_mng_thread, NULL);
 		if (ret) {
 			printf("\npthread_create %dth thread fail!", i);
 			return -1;
@@ -257,11 +239,9 @@ int main(int argc, char *argv[])
 	/* set input rsa sample data */
 	for (i = 0; i < ASIZE / 8; i++)
 		*(__u32 *)(a + i * 4) = i;
-#ifndef DEBUG_NOIOMMU
 	ret = wd_mem_share(&q, a, ASIZE, 0);
 	SYS_ERR_COND(ret, "wd_mem_share err\n");
 	printf("WD dma map VA=IOVA=%p successfully!\n", a);
-#endif
 	src = a;
 	dst = (char *)a + (ASIZE / 2);
 
@@ -313,9 +293,7 @@ int main(int argc, char *argv[])
 
 alloc_msg_fail:
 	wd_del_rsa_ctx(ctx);
-#ifndef DEBUG_NOIOMMU
 	wd_mem_unshare(&q, a, ASIZE);
-#endif
 	munmap(a, ASIZE);
 release_q:
 	wd_release_queue(&q);