drm/nouveau/disp: switch to device pri macros

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c

@@ -33,6 +33,7 @@
 int
 nv50_dac_power(NV50_DISP_MTHD_V1)
 {
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 doff = outp->or * 0x800;
 	union {
 		struct nv50_disp_dac_pwr_v0 v0;
@@ -54,7 +55,7 @@ nv50_dac_power(NV50_DISP_MTHD_V1)
 		return ret;
 
 	nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);
-	nv_mask(disp, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);
+	nvkm_mask(device, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);
 	nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);
 	return 0;
 }
@@ -62,6 +63,7 @@ nv50_dac_power(NV50_DISP_MTHD_V1)
 int
 nv50_dac_sense(NV50_DISP_MTHD_V1)
 {
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	union {
 		struct nv50_disp_dac_load_v0 v0;
 	} *args = data;
@@ -79,15 +81,15 @@ nv50_dac_sense(NV50_DISP_MTHD_V1)
 	} else
 		return ret;
 
-	nv_mask(disp, 0x61a004 + doff, 0x807f0000, 0x80150000);
+	nvkm_mask(device, 0x61a004 + doff, 0x807f0000, 0x80150000);
 	nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);
 
-	nv_wr32(disp, 0x61a00c + doff, 0x00100000 | loadval);
+	nvkm_wr32(device, 0x61a00c + doff, 0x00100000 | loadval);
 	mdelay(9);
 	udelay(500);
-	loadval = nv_mask(disp, 0x61a00c + doff, 0xffffffff, 0x00000000);
+	loadval = nvkm_mask(device, 0x61a00c + doff, 0xffffffff, 0x00000000);
 
-	nv_mask(disp, 0x61a004 + doff, 0x807f0000, 0x80550000);
+	nvkm_mask(device, 0x61a004 + doff, 0x807f0000, 0x80550000);
 	nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000);
 
 	nv_debug(disp, "DAC%d sense: 0x%08x\n", outp->or, loadval);

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

@@ -219,8 +219,9 @@ gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
+	struct nvkm_device *device = (void *)parent;
 	struct nv50_disp *disp;
-	int heads = nv_rd32(parent, 0x022448);
+	int heads = nvkm_rd32(device, 0x022448);
 	int ret;
 
 	ret = nvkm_disp_create(parent, engine, oclass, heads,

drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c

@@ -54,8 +54,9 @@ gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
+	struct nvkm_device *device = (void *)parent;
 	struct nv50_disp *disp;
-	int heads = nv_rd32(parent, 0x022448);
+	int heads = nvkm_rd32(device, 0x022448);
 	int ret;
 
 	ret = nvkm_disp_create(parent, engine, oclass, heads,

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c

@@ -54,8 +54,9 @@ gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
+	struct nvkm_device *device = (void *)parent;
 	struct nv50_disp *disp;
-	int heads = nv_rd32(parent, 0x022448);
+	int heads = nvkm_rd32(device, 0x022448);
 	int ret;
 
 	ret = nvkm_disp_create(parent, engine, oclass, heads,

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c

@@ -55,8 +55,9 @@ gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		struct nvkm_oclass *oclass, void *data, u32 size,
 		struct nvkm_object **pobject)
 {
+	struct nvkm_device *device = (void *)parent;
 	struct nv50_disp *disp;
-	int heads = nv_rd32(parent, 0x022448);
+	int heads = nvkm_rd32(device, 0x022448);
 	int ret;
 
 	ret = nvkm_disp_create(parent, engine, oclass, heads,

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c

@@ -35,6 +35,7 @@
 int
 gf110_hda_eld(NV50_DISP_MTHD_V1)
 {
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	union {
 		struct nv50_disp_sor_hda_eld_v0 v0;
 	} *args = data;
@@ -52,21 +53,21 @@ gf110_hda_eld(NV50_DISP_MTHD_V1)
 
 	if (size && args->v0.data[0]) {
 		if (outp->info.type == DCB_OUTPUT_DP) {
-			nv_mask(disp, 0x616618 + hoff, 0x8000000c, 0x80000001);
+			nvkm_mask(device, 0x616618 + hoff, 0x8000000c, 0x80000001);
 			nv_wait(disp, 0x616618 + hoff, 0x80000000, 0x00000000);
 		}
-		nv_mask(disp, 0x616548 + hoff, 0x00000070, 0x00000000);
+		nvkm_mask(device, 0x616548 + hoff, 0x00000070, 0x00000000);
 		for (i = 0; i < size; i++)
-			nv_wr32(disp, 0x10ec00 + soff, (i << 8) | args->v0.data[i]);
+			nvkm_wr32(device, 0x10ec00 + soff, (i << 8) | args->v0.data[i]);
 		for (; i < 0x60; i++)
-			nv_wr32(disp, 0x10ec00 + soff, (i << 8));
-		nv_mask(disp, 0x10ec10 + soff, 0x80000003, 0x80000003);
+			nvkm_wr32(device, 0x10ec00 + soff, (i << 8));
+		nvkm_mask(device, 0x10ec10 + soff, 0x80000003, 0x80000003);
 	} else {
 		if (outp->info.type == DCB_OUTPUT_DP) {
-			nv_mask(disp, 0x616618 + hoff, 0x80000001, 0x80000000);
+			nvkm_mask(device, 0x616618 + hoff, 0x80000001, 0x80000000);
 			nv_wait(disp, 0x616618 + hoff, 0x80000000, 0x00000000);
 		}
-		nv_mask(disp, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size);
+		nvkm_mask(device, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size);
 	}
 
 	return 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c

@@ -33,6 +33,7 @@
 int
 gt215_hda_eld(NV50_DISP_MTHD_V1)
 {
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	union {
 		struct nv50_disp_sor_hda_eld_v0 v0;
 	} *args = data;
@@ -49,20 +50,20 @@ gt215_hda_eld(NV50_DISP_MTHD_V1)
 
 	if (size && args->v0.data[0]) {
 		if (outp->info.type == DCB_OUTPUT_DP) {
-			nv_mask(disp, 0x61c1e0 + soff, 0x8000000d, 0x80000001);
+			nvkm_mask(device, 0x61c1e0 + soff, 0x8000000d, 0x80000001);
 			nv_wait(disp, 0x61c1e0 + soff, 0x80000000, 0x00000000);
 		}
 		for (i = 0; i < size; i++)
-			nv_wr32(disp, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
+			nvkm_wr32(device, 0x61c440 + soff, (i << 8) | args->v0.data[0]);
 		for (; i < 0x60; i++)
-			nv_wr32(disp, 0x61c440 + soff, (i << 8));
-		nv_mask(disp, 0x61c448 + soff, 0x80000003, 0x80000003);
+			nvkm_wr32(device, 0x61c440 + soff, (i << 8));
+		nvkm_mask(device, 0x61c448 + soff, 0x80000003, 0x80000003);
 	} else {
 		if (outp->info.type == DCB_OUTPUT_DP) {
-			nv_mask(disp, 0x61c1e0 + soff, 0x80000001, 0x80000000);
+			nvkm_mask(device, 0x61c1e0 + soff, 0x80000001, 0x80000000);
 			nv_wait(disp, 0x61c1e0 + soff, 0x80000000, 0x00000000);
 		}
-		nv_mask(disp, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size);
+		nvkm_mask(device, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size);
 	}
 
 	return 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c

@@ -31,6 +31,7 @@
 int
 g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
 {
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 hoff = (head * 0x800);
 	union {
 		struct nv50_disp_sor_hdmi_pwr_v0 v0;
@@ -54,38 +55,38 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
 		return ret;
 
 	if (!(ctrl & 0x40000000)) {
-		nv_mask(disp, 0x6165a4 + hoff, 0x40000000, 0x00000000);
-		nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000000);
-		nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000000);
+		nvkm_mask(device, 0x6165a4 + hoff, 0x40000000, 0x00000000);
+		nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);
+		nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);
 		return 0;
 	}
 
 	/* AVI InfoFrame */
-	nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000000);
-	nv_wr32(disp, 0x616528 + hoff, 0x000d0282);
-	nv_wr32(disp, 0x61652c + hoff, 0x0000006f);
-	nv_wr32(disp, 0x616530 + hoff, 0x00000000);
-	nv_wr32(disp, 0x616534 + hoff, 0x00000000);
-	nv_wr32(disp, 0x616538 + hoff, 0x00000000);
-	nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000001);
+	nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000000);
+	nvkm_wr32(device, 0x616528 + hoff, 0x000d0282);
+	nvkm_wr32(device, 0x61652c + hoff, 0x0000006f);
+	nvkm_wr32(device, 0x616530 + hoff, 0x00000000);
+	nvkm_wr32(device, 0x616534 + hoff, 0x00000000);
+	nvkm_wr32(device, 0x616538 + hoff, 0x00000000);
+	nvkm_mask(device, 0x616520 + hoff, 0x00000001, 0x00000001);
 
 	/* Audio InfoFrame */
-	nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000000);
-	nv_wr32(disp, 0x616508 + hoff, 0x000a0184);
-	nv_wr32(disp, 0x61650c + hoff, 0x00000071);
-	nv_wr32(disp, 0x616510 + hoff, 0x00000000);
-	nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000001);
+	nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000000);
+	nvkm_wr32(device, 0x616508 + hoff, 0x000a0184);
+	nvkm_wr32(device, 0x61650c + hoff, 0x00000071);
+	nvkm_wr32(device, 0x616510 + hoff, 0x00000000);
+	nvkm_mask(device, 0x616500 + hoff, 0x00000001, 0x00000001);
 
-	nv_mask(disp, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
-	nv_mask(disp, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
-	nv_mask(disp, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
+	nvkm_mask(device, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
+	nvkm_mask(device, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
+	nvkm_mask(device, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
 
 	/* ??? */
-	nv_mask(disp, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
-	nv_mask(disp, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
-	nv_mask(disp, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
+	nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
+	nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
+	nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
 
 	/* HDMI_CTRL */
-	nv_mask(disp, 0x6165a4 + hoff, 0x5f1f007f, ctrl);
+	nvkm_mask(device, 0x6165a4 + hoff, 0x5f1f007f, ctrl);
 	return 0;
 }

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c

@@ -31,6 +31,7 @@
 int
 gf110_hdmi_ctrl(NV50_DISP_MTHD_V1)
 {
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 hoff = (head * 0x800);
 	union {
 		struct nv50_disp_sor_hdmi_pwr_v0 v0;
@@ -53,27 +54,27 @@ gf110_hdmi_ctrl(NV50_DISP_MTHD_V1)
 		return ret;
 
 	if (!(ctrl & 0x40000000)) {
-		nv_mask(disp, 0x616798 + hoff, 0x40000000, 0x00000000);
-		nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000000);
-		nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000000);
+		nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000);
+		nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000000);
+		nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000000);
 		return 0;
 	}
 
 	/* AVI InfoFrame */
-	nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000000);
-	nv_wr32(disp, 0x61671c + hoff, 0x000d0282);
-	nv_wr32(disp, 0x616720 + hoff, 0x0000006f);
-	nv_wr32(disp, 0x616724 + hoff, 0x00000000);
-	nv_wr32(disp, 0x616728 + hoff, 0x00000000);
-	nv_wr32(disp, 0x61672c + hoff, 0x00000000);
-	nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000001);
+	nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000000);
+	nvkm_wr32(device, 0x61671c + hoff, 0x000d0282);
+	nvkm_wr32(device, 0x616720 + hoff, 0x0000006f);
+	nvkm_wr32(device, 0x616724 + hoff, 0x00000000);
+	nvkm_wr32(device, 0x616728 + hoff, 0x00000000);
+	nvkm_wr32(device, 0x61672c + hoff, 0x00000000);
+	nvkm_mask(device, 0x616714 + hoff, 0x00000001, 0x00000001);
 
 	/* ??? InfoFrame? */
-	nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000000);
-	nv_wr32(disp, 0x6167ac + hoff, 0x00000010);
-	nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000001);
+	nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000000);
+	nvkm_wr32(device, 0x6167ac + hoff, 0x00000010);
+	nvkm_mask(device, 0x6167a4 + hoff, 0x00000001, 0x00000001);
 
 	/* HDMI_CTRL */
-	nv_mask(disp, 0x616798 + hoff, 0x401f007f, ctrl);
+	nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl);
 	return 0;
 }

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c

@@ -31,6 +31,7 @@
 int
 gk104_hdmi_ctrl(NV50_DISP_MTHD_V1)
 {
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 hoff = (head * 0x800);
 	const u32 hdmi = (head * 0x400);
 	union {
@@ -54,30 +55,30 @@ gk104_hdmi_ctrl(NV50_DISP_MTHD_V1)
 		return ret;
 
 	if (!(ctrl & 0x40000000)) {
-		nv_mask(disp, 0x616798 + hoff, 0x40000000, 0x00000000);
-		nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
-		nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000000);
+		nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000);
+		nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
+		nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000);
 		return 0;
 	}
 
 	/* AVI InfoFrame */
-	nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000000);
-	nv_wr32(disp, 0x690008 + hdmi, 0x000d0282);
-	nv_wr32(disp, 0x69000c + hdmi, 0x0000006f);
-	nv_wr32(disp, 0x690010 + hdmi, 0x00000000);
-	nv_wr32(disp, 0x690014 + hdmi, 0x00000000);
-	nv_wr32(disp, 0x690018 + hdmi, 0x00000000);
-	nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000001);
+	nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000);
+	nvkm_wr32(device, 0x690008 + hdmi, 0x000d0282);
+	nvkm_wr32(device, 0x69000c + hdmi, 0x0000006f);
+	nvkm_wr32(device, 0x690010 + hdmi, 0x00000000);
+	nvkm_wr32(device, 0x690014 + hdmi, 0x00000000);
+	nvkm_wr32(device, 0x690018 + hdmi, 0x00000000);
+	nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000001);
 
 	/* ??? InfoFrame? */
-	nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
-	nv_wr32(disp, 0x6900cc + hdmi, 0x00000010);
-	nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000001);
+	nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
+	nvkm_wr32(device, 0x6900cc + hdmi, 0x00000010);
+	nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000001);
 
 	/* ??? */
-	nv_wr32(disp, 0x690080 + hdmi, 0x82000000);
+	nvkm_wr32(device, 0x690080 + hdmi, 0x82000000);
 
 	/* HDMI_CTRL */
-	nv_mask(disp, 0x616798 + hoff, 0x401f007f, ctrl);
+	nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl);
 	return 0;
 }

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c

@@ -32,6 +32,7 @@
 int
 gt215_hdmi_ctrl(NV50_DISP_MTHD_V1)
 {
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 soff = outp->or * 0x800;
 	union {
 		struct nv50_disp_sor_hdmi_pwr_v0 v0;
@@ -55,38 +56,38 @@ gt215_hdmi_ctrl(NV50_DISP_MTHD_V1)
 		return ret;
 
 	if (!(ctrl & 0x40000000)) {
-		nv_mask(disp, 0x61c5a4 + soff, 0x40000000, 0x00000000);
-		nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000000);
-		nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000000);
+		nvkm_mask(device, 0x61c5a4 + soff, 0x40000000, 0x00000000);
+		nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000);
+		nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000);
 		return 0;
 	}
 
 	/* AVI InfoFrame */
-	nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000000);
-	nv_wr32(disp, 0x61c528 + soff, 0x000d0282);
-	nv_wr32(disp, 0x61c52c + soff, 0x0000006f);
-	nv_wr32(disp, 0x61c530 + soff, 0x00000000);
-	nv_wr32(disp, 0x61c534 + soff, 0x00000000);
-	nv_wr32(disp, 0x61c538 + soff, 0x00000000);
-	nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000001);
+	nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000000);
+	nvkm_wr32(device, 0x61c528 + soff, 0x000d0282);
+	nvkm_wr32(device, 0x61c52c + soff, 0x0000006f);
+	nvkm_wr32(device, 0x61c530 + soff, 0x00000000);
+	nvkm_wr32(device, 0x61c534 + soff, 0x00000000);
+	nvkm_wr32(device, 0x61c538 + soff, 0x00000000);
+	nvkm_mask(device, 0x61c520 + soff, 0x00000001, 0x00000001);
 
 	/* Audio InfoFrame */
-	nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000000);
-	nv_wr32(disp, 0x61c508 + soff, 0x000a0184);
-	nv_wr32(disp, 0x61c50c + soff, 0x00000071);
-	nv_wr32(disp, 0x61c510 + soff, 0x00000000);
-	nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000001);
+	nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000000);
+	nvkm_wr32(device, 0x61c508 + soff, 0x000a0184);
+	nvkm_wr32(device, 0x61c50c + soff, 0x00000071);
+	nvkm_wr32(device, 0x61c510 + soff, 0x00000000);
+	nvkm_mask(device, 0x61c500 + soff, 0x00000001, 0x00000001);
 
-	nv_mask(disp, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
-	nv_mask(disp, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
-	nv_mask(disp, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
+	nvkm_mask(device, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
+	nvkm_mask(device, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
+	nvkm_mask(device, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
 
 	/* ??? */
-	nv_mask(disp, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
-	nv_mask(disp, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
-	nv_mask(disp, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
+	nvkm_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
+	nvkm_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
+	nvkm_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
 
 	/* HDMI_CTRL */
-	nv_mask(disp, 0x61c5a4 + soff, 0x5f1f007f, ctrl);
+	nvkm_mask(device, 0x61c5a4 + soff, 0x5f1f007f, ctrl);
 	return 0;
 }

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c

@@ -32,6 +32,7 @@ static int
 nv04_disp_scanoutpos(struct nvkm_object *object, struct nvkm_disp *disp,
 		     void *data, u32 size, int head)
 {
+	struct nvkm_device *device = disp->engine.subdev.device;
 	const u32 hoff = head * 0x2000;
 	union {
 		struct nv04_disp_scanoutpos_v0 v0;
@@ -42,12 +43,12 @@ nv04_disp_scanoutpos(struct nvkm_object *object, struct nvkm_disp *disp,
 	nv_ioctl(object, "disp scanoutpos size %d\n", size);
 	if (nvif_unpack(args->v0, 0, 0, false)) {
 		nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version);
-		args->v0.vblanks = nv_rd32(disp, 0x680800 + hoff) & 0xffff;
-		args->v0.vtotal  = nv_rd32(disp, 0x680804 + hoff) & 0xffff;
+		args->v0.vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0xffff;
+		args->v0.vtotal  = nvkm_rd32(device, 0x680804 + hoff) & 0xffff;
 		args->v0.vblanke = args->v0.vtotal - 1;
 
-		args->v0.hblanks = nv_rd32(disp, 0x680820 + hoff) & 0xffff;
-		args->v0.htotal  = nv_rd32(disp, 0x680824 + hoff) & 0xffff;
+		args->v0.hblanks = nvkm_rd32(device, 0x680820 + hoff) & 0xffff;
+		args->v0.htotal  = nvkm_rd32(device, 0x680824 + hoff) & 0xffff;
 		args->v0.hblanke = args->v0.htotal - 1;
 
 		/*
@@ -59,7 +60,7 @@ nv04_disp_scanoutpos(struct nvkm_object *object, struct nvkm_disp *disp,
 			return -ENOTSUPP;
 
 		args->v0.time[0] = ktime_to_ns(ktime_get());
-		line = nv_rd32(disp, 0x600868 + hoff);
+		line = nvkm_rd32(device, 0x600868 + hoff);
 		args->v0.time[1] = ktime_to_ns(ktime_get());
 		args->v0.hline = (line & 0xffff0000) >> 16;
 		args->v0.vline = (line & 0x0000ffff);
@@ -124,14 +125,16 @@ static void
 nv04_disp_vblank_init(struct nvkm_event *event, int type, int head)
 {
 	struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
-	nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000001);
+	struct nvkm_device *device = disp->engine.subdev.device;
+	nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000001);
 }
 
 static void
 nv04_disp_vblank_fini(struct nvkm_event *event, int type, int head)
 {
 	struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
-	nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000000);
+	struct nvkm_device *device = disp->engine.subdev.device;
+	nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000000);
 }
 
 static const struct nvkm_event_func
@@ -145,26 +148,27 @@ static void
 nv04_disp_intr(struct nvkm_subdev *subdev)
 {
 	struct nvkm_disp *disp = (void *)subdev;
-	u32 crtc0 = nv_rd32(disp, 0x600100);
-	u32 crtc1 = nv_rd32(disp, 0x602100);
+	struct nvkm_device *device = disp->engine.subdev.device;
+	u32 crtc0 = nvkm_rd32(device, 0x600100);
+	u32 crtc1 = nvkm_rd32(device, 0x602100);
 	u32 pvideo;
 
 	if (crtc0 & 0x00000001) {
 		nvkm_disp_vblank(disp, 0);
-		nv_wr32(disp, 0x600100, 0x00000001);
+		nvkm_wr32(device, 0x600100, 0x00000001);
 	}
 
 	if (crtc1 & 0x00000001) {
 		nvkm_disp_vblank(disp, 1);
-		nv_wr32(disp, 0x602100, 0x00000001);
+		nvkm_wr32(device, 0x602100, 0x00000001);
 	}
 
 	if (nv_device(disp)->chipset >= 0x10 &&
 	    nv_device(disp)->chipset <= 0x40) {
-		pvideo = nv_rd32(disp, 0x8100);
+		pvideo = nvkm_rd32(device, 0x8100);
 		if (pvideo & ~0x11)
 			nv_info(disp, "PVIDEO intr: %08x\n", pvideo);
-		nv_wr32(disp, 0x8100, pvideo);
+		nvkm_wr32(device, 0x8100, pvideo);
 	}
 }
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c

@@ -144,6 +144,7 @@ nv50_pior_dp_impl = {
 int
 nv50_pior_power(NV50_DISP_MTHD_V1)
 {
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 soff = outp->or * 0x800;
 	union {
 		struct nv50_disp_pior_pwr_v0 v0;
@@ -163,7 +164,7 @@ nv50_pior_power(NV50_DISP_MTHD_V1)
 		return ret;
 
 	nv_wait(disp, 0x61e004 + soff, 0x80000000, 0x00000000);
-	nv_mask(disp, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl);
+	nvkm_mask(device, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl);
 	nv_wait(disp, 0x61e004 + soff, 0x80000000, 0x00000000);
 	disp->pior.type[outp->or] = type;
 	return 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c

@@ -55,8 +55,9 @@ static int
 g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 loff = g94_sor_loff(outp);
-	nv_mask(disp, 0x61c10c + loff, 0x0f000000, pattern << 24);
+	nvkm_mask(device, 0x61c10c + loff, 0x0f000000, pattern << 24);
 	return 0;
 }
 
@@ -64,6 +65,7 @@ int
 g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 soff = g94_sor_soff(outp);
 	const u32 loff = g94_sor_loff(outp);
 	u32 mask = 0, i;
@@ -71,8 +73,8 @@ g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
 	for (i = 0; i < nr; i++)
 		mask |= 1 << (g94_sor_dp_lane_map(disp, i) >> 3);
 
-	nv_mask(disp, 0x61c130 + loff, 0x0000000f, mask);
-	nv_mask(disp, 0x61c034 + soff, 0x80000000, 0x80000000);
+	nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask);
+	nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);
 	nv_wait(disp, 0x61c034 + soff, 0x80000000, 0x00000000);
 	return 0;
 }
@@ -81,6 +83,7 @@ static int
 g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 soff = g94_sor_soff(outp);
 	const u32 loff = g94_sor_loff(outp);
 	u32 dpctrl = 0x00000000;
@@ -92,8 +95,8 @@ g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
 	if (bw > 0x06)
 		clksor |= 0x00040000;
 
-	nv_mask(disp, 0x614300 + soff, 0x000c0000, clksor);
-	nv_mask(disp, 0x61c10c + loff, 0x001f4000, dpctrl);
+	nvkm_mask(device, 0x614300 + soff, 0x000c0000, clksor);
+	nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl);
 	return 0;
 }
 
@@ -101,7 +104,8 @@ static int
 g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
-	struct nvkm_bios *bios = nvkm_bios(disp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
+	struct nvkm_bios *bios = device->bios;
 	const u32 shift = g94_sor_dp_lane_map(disp, ln);
 	const u32 loff = g94_sor_loff(outp);
 	u32 addr, data[3];
@@ -120,14 +124,14 @@ g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
 	if (!addr)
 		return -EINVAL;
 
-	data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift);
-	data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift);
-	data[2] = nv_rd32(disp, 0x61c130 + loff);
+	data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
+	data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
+	data[2] = nvkm_rd32(device, 0x61c130 + loff);
 	if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
 		data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
-	nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
-	nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
-	nv_wr32(disp, 0x61c130 + loff, data[2]);
+	nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
+	nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
+	nvkm_wr32(device, 0x61c130 + loff, data[2]);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c

@@ -40,8 +40,9 @@ static int
 gf110_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 loff = gf110_sor_loff(outp);
-	nv_mask(disp, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
+	nvkm_mask(device, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
 	return 0;
 }
 
@@ -49,6 +50,7 @@ int
 gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 soff = gf110_sor_soff(outp);
 	const u32 loff = gf110_sor_loff(outp);
 	u32 dpctrl = 0x00000000;
@@ -59,8 +61,8 @@ gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
 	if (ef)
 		dpctrl |= 0x00004000;
 
-	nv_mask(disp, 0x612300 + soff, 0x007c0000, clksor);
-	nv_mask(disp, 0x61c10c + loff, 0x001f4000, dpctrl);
+	nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
+	nvkm_mask(device, 0x61c10c + loff, 0x001f4000, dpctrl);
 	return 0;
 }
 
@@ -69,7 +71,8 @@ gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
 		     int ln, int vs, int pe, int pc)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
-	struct nvkm_bios *bios = nvkm_bios(disp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
+	struct nvkm_bios *bios = device->bios;
 	const u32 shift = g94_sor_dp_lane_map(disp, ln);
 	const u32 loff = gf110_sor_loff(outp);
 	u32 addr, data[4];
@@ -88,16 +91,16 @@ gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
 	if (!addr)
 		return -EINVAL;
 
-	data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift);
-	data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift);
-	data[2] = nv_rd32(disp, 0x61c130 + loff);
+	data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
+	data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
+	data[2] = nvkm_rd32(device, 0x61c130 + loff);
 	if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
 		data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
-	nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
-	nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
-	nv_wr32(disp, 0x61c130 + loff, data[2]);
-	data[3] = nv_rd32(disp, 0x61c13c + loff) & ~(0x000000ff << shift);
-	nv_wr32(disp, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
+	nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
+	nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
+	nvkm_wr32(device, 0x61c130 + loff, data[2]);
+	data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
+	nvkm_wr32(device, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c

@@ -42,12 +42,13 @@ void
 gm204_sor_magic(struct nvkm_output *outp)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 soff = outp->or * 0x100;
 	const u32 data = outp->or + 1;
 	if (outp->info.sorconf.link & 1)
-		nv_mask(disp, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
+		nvkm_mask(device, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
 	if (outp->info.sorconf.link & 2)
-		nv_mask(disp, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
+		nvkm_mask(device, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
 }
 
 static inline u32
@@ -60,12 +61,13 @@ static int
 gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 soff = gm204_sor_soff(outp);
 	const u32 data = 0x01010101 * pattern;
 	if (outp->base.info.sorconf.link & 1)
-		nv_mask(disp, 0x61c110 + soff, 0x0f0f0f0f, data);
+		nvkm_mask(device, 0x61c110 + soff, 0x0f0f0f0f, data);
 	else
-		nv_mask(disp, 0x61c12c + soff, 0x0f0f0f0f, data);
+		nvkm_mask(device, 0x61c12c + soff, 0x0f0f0f0f, data);
 	return 0;
 }
 
@@ -73,6 +75,7 @@ static int
 gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	const u32 soff = gm204_sor_soff(outp);
 	const u32 loff = gm204_sor_loff(outp);
 	u32 mask = 0, i;
@@ -80,8 +83,8 @@ gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
 	for (i = 0; i < nr; i++)
 		mask |= 1 << (gm204_sor_dp_lane_map(disp, i) >> 3);
 
-	nv_mask(disp, 0x61c130 + loff, 0x0000000f, mask);
-	nv_mask(disp, 0x61c034 + soff, 0x80000000, 0x80000000);
+	nvkm_mask(device, 0x61c130 + loff, 0x0000000f, mask);
+	nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);
 	nv_wait(disp, 0x61c034 + soff, 0x80000000, 0x00000000);
 	return 0;
 }
@@ -91,7 +94,8 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
 		     int ln, int vs, int pe, int pc)
 {
 	struct nv50_disp *disp = (void *)nvkm_disp(outp);
-	struct nvkm_bios *bios = nvkm_bios(disp);
+	struct nvkm_device *device = disp->base.engine.subdev.device;
+	struct nvkm_bios *bios = device->bios;
 	const u32 shift = gm204_sor_dp_lane_map(disp, ln);
 	const u32 loff = gm204_sor_loff(outp);
 	u32 addr, data[4];
@@ -111,16 +115,16 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
 		return -EINVAL;
 	ocfg.tx_pu &= 0x0f;
 
-	data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift);
-	data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift);
-	data[2] = nv_rd32(disp, 0x61c130 + loff);
+	data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift);
+	data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift);
+	data[2] = nvkm_rd32(device, 0x61c130 + loff);
 	if ((data[2] & 0x00000f00) < (ocfg.tx_pu << 8) || ln == 0)
 		data[2] = (data[2] & ~0x00000f00) | (ocfg.tx_pu << 8);
-	nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
-	nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
-	nv_wr32(disp, 0x61c130 + loff, data[2]);
-	data[3] = nv_rd32(disp, 0x61c13c + loff) & ~(0x000000ff << shift);
-	nv_wr32(disp, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
+	nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
+	nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
+	nvkm_wr32(device, 0x61c130 + loff, data[2]);
+	data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift);
+	nvkm_wr32(device, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c

@@ -33,6 +33,7 @@
 int
 nv50_sor_power(NV50_DISP_MTHD_V1)
 {
+	struct nvkm_device *device = disp->base.engine.subdev.device;
 	union {
 		struct nv50_disp_sor_pwr_v0 v0;
 	} *args = data;
@@ -49,7 +50,7 @@ nv50_sor_power(NV50_DISP_MTHD_V1)
 		return ret;
 
 	nv_wait(disp, 0x61c004 + soff, 0x80000000, 0x00000000);
-	nv_mask(disp, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);
+	nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);
 	nv_wait(disp, 0x61c004 + soff, 0x80000000, 0x00000000);
 	nv_wait(disp, 0x61c030 + soff, 0x10000000, 0x00000000);
 	return 0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c

@@ -29,19 +29,19 @@ nv_rdport(void *obj, int head, u16 port)
 	struct nvkm_device *device = nv_device(obj);
 
 	if (device->card_type >= NV_50)
-		return nv_rd08(obj, 0x601000 + port);
+		return nvkm_rd08(device, 0x601000 + port);
 
 	if (port == 0x03c0 || port == 0x03c1 ||	/* AR */
 	    port == 0x03c2 || port == 0x03da ||	/* INP0 */
 	    port == 0x03d4 || port == 0x03d5)	/* CR */
-		return nv_rd08(obj, 0x601000 + (head * 0x2000) + port);
+		return nvkm_rd08(device, 0x601000 + (head * 0x2000) + port);
 
 	if (port == 0x03c2 || port == 0x03cc ||	/* MISC */
 	    port == 0x03c4 || port == 0x03c5 ||	/* SR */
 	    port == 0x03ce || port == 0x03cf) {	/* GR */
 		if (device->card_type < NV_40)
 			head = 0; /* CR44 selects head */
-		return nv_rd08(obj, 0x0c0000 + (head * 0x2000) + port);
+		return nvkm_rd08(device, 0x0c0000 + (head * 0x2000) + port);
 	}
 
 	nv_error(obj, "unknown vga port 0x%04x\n", port);
@@ -54,19 +54,19 @@ nv_wrport(void *obj, int head, u16 port, u8 data)
 	struct nvkm_device *device = nv_device(obj);
 
 	if (device->card_type >= NV_50)
-		nv_wr08(obj, 0x601000 + port, data);
+		nvkm_wr08(device, 0x601000 + port, data);
 	else
 	if (port == 0x03c0 || port == 0x03c1 ||	/* AR */
 	    port == 0x03c2 || port == 0x03da ||	/* INP0 */
 	    port == 0x03d4 || port == 0x03d5)	/* CR */
-		nv_wr08(obj, 0x601000 + (head * 0x2000) + port, data);
+		nvkm_wr08(device, 0x601000 + (head * 0x2000) + port, data);
 	else
 	if (port == 0x03c2 || port == 0x03cc ||	/* MISC */
 	    port == 0x03c4 || port == 0x03c5 ||	/* SR */
 	    port == 0x03ce || port == 0x03cf) {	/* GR */
 		if (device->card_type < NV_40)
 			head = 0; /* CR44 selects head */
-		nv_wr08(obj, 0x0c0000 + (head * 0x2000) + port, data);
+		nvkm_wr08(device, 0x0c0000 + (head * 0x2000) + port, data);
 	} else
 		nv_error(obj, "unknown vga port 0x%04x\n", port);
 }
@@ -135,16 +135,16 @@ nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value)
 bool
 nv_lockvgac(void *obj, bool lock)
 {
-	struct nvkm_device *dev = nv_device(obj);
+	struct nvkm_device *device = nv_device(obj);
 
 	bool locked = !nv_rdvgac(obj, 0, 0x1f);
 	u8 data = lock ? 0x99 : 0x57;
-	if (dev->card_type < NV_50)
+	if (device->card_type < NV_50)
 		nv_wrvgac(obj, 0, 0x1f, data);
 	else
 		nv_wrvgac(obj, 0, 0x3f, data);
-	if (dev->chipset == 0x11) {
-		if (!(nv_rd32(obj, 0x001084) & 0x10000000))
+	if (device->chipset == 0x11) {
+		if (!(nvkm_rd32(device, 0x001084) & 0x10000000))
 			nv_wrvgac(obj, 1, 0x1f, data);
 	}
 	return locked;
@@ -171,9 +171,10 @@ nv_lockvgac(void *obj, bool lock)
 u8
 nv_rdvgaowner(void *obj)
 {
-	if (nv_device(obj)->card_type < NV_50) {
+	struct nvkm_device *device = nv_device(obj);
+	if (device->card_type < NV_50) {
 		if (nv_device(obj)->chipset == 0x11) {
-			u32 tied = nv_rd32(obj, 0x001084) & 0x10000000;
+			u32 tied = nvkm_rd32(device, 0x001084) & 0x10000000;
 			if (tied == 0) {
 				u8 slA = nv_rdvgac(obj, 0, 0x28) & 0x80;
 				u8 tvA = nv_rdvgac(obj, 0, 0x33) & 0x01;