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raspberrypi-kernel
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2b73a19f
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raspberrypi-kernel
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2b73a19f
编写于
14年前
作者:
M
Mike Frysinger
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电子邮件补丁
差异文件
Blackfin: BF54x: tweak DMAC MMR naming to match other ports
Signed-off-by:
N
Mike Frysinger
<
vapier@gentoo.org
>
上级
ba3f5973
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
12 addition
and
12 deletion
+12
-12
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
+8
-8
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+4
-4
未找到文件。
arch/blackfin/mach-bf548/include/mach/cdefBF54x_base.h
浏览文件 @
2b73a19f
...
...
@@ -301,10 +301,10 @@
/* DMAC0 Registers */
#define bfin_read_DMAC0_TC
PER() bfin_read16(DMAC0_TC
PER)
#define bfin_write_DMAC0_TC
PER(val) bfin_write16(DMAC0_TC
PER, val)
#define bfin_read_DMAC0_TC
CNT() bfin_read16(DMAC0_TC
CNT)
#define bfin_write_DMAC0_TC
CNT(val) bfin_write16(DMAC0_TC
CNT, val)
#define bfin_read_DMAC0_TC
_PER() bfin_read16(DMAC0_TC_
PER)
#define bfin_write_DMAC0_TC
_PER(val) bfin_write16(DMAC0_TC_
PER, val)
#define bfin_read_DMAC0_TC
_CNT() bfin_read16(DMAC0_TC_
CNT)
#define bfin_write_DMAC0_TC
_CNT(val) bfin_write16(DMAC0_TC_
CNT, val)
/* DMA Channel 0 Registers */
...
...
@@ -1155,10 +1155,10 @@
/* DMAC1 Registers */
#define bfin_read_DMAC1_TC
PER() bfin_read16(DMAC1_TC
PER)
#define bfin_write_DMAC1_TC
PER(val) bfin_write16(DMAC1_TC
PER, val)
#define bfin_read_DMAC1_TC
CNT() bfin_read16(DMAC1_TC
CNT)
#define bfin_write_DMAC1_TC
CNT(val) bfin_write16(DMAC1_TC
CNT, val)
#define bfin_read_DMAC1_TC
_PER() bfin_read16(DMAC1_TC_
PER)
#define bfin_write_DMAC1_TC
_PER(val) bfin_write16(DMAC1_TC_
PER, val)
#define bfin_read_DMAC1_TC
_CNT() bfin_read16(DMAC1_TC_
CNT)
#define bfin_write_DMAC1_TC
_CNT(val) bfin_write16(DMAC1_TC_
CNT, val)
/* DMA Channel 12 Registers */
...
...
This diff is collapsed.
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arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
浏览文件 @
2b73a19f
...
...
@@ -198,8 +198,8 @@
/* DMAC0 Registers */
#define
DMAC0_TC
PER 0xffc00b0c
/* DMA Controller 0 Traffic Control Periods Register */
#define
DMAC0_TC
CNT 0xffc00b10
/* DMA Controller 0 Current Counts Register */
#define
DMAC0_TC_
PER 0xffc00b0c
/* DMA Controller 0 Traffic Control Periods Register */
#define
DMAC0_TC_
CNT 0xffc00b10
/* DMA Controller 0 Current Counts Register */
/* DMA Channel 0 Registers */
...
...
@@ -688,8 +688,8 @@
/* DMAC1 Registers */
#define
DMAC1_TC
PER 0xffc01b0c
/* DMA Controller 1 Traffic Control Periods Register */
#define
DMAC1_TC
CNT 0xffc01b10
/* DMA Controller 1 Current Counts Register */
#define
DMAC1_TC_
PER 0xffc01b0c
/* DMA Controller 1 Traffic Control Periods Register */
#define
DMAC1_TC_
CNT 0xffc01b10
/* DMA Controller 1 Current Counts Register */
/* DMA Channel 12 Registers */
...
...
This diff is collapsed.
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