Skip to content

R
raspberrypi-kernel

openeuler / raspberrypi-kernel

通知 13
Star 1
Fork 0
R
raspberrypi-kernel
“b211f02b687bf3b2462337df52521706c661d4d9”上不存在“...fluid/operators/git@gitcode.net:RobotFutures/Paddle.git”
提交 2990a1fc 编写于 作者: A Alex Deucher
浏览文件
操作

drm/amdgpu: rename ip block helper functions 

add device to the name for consistency.
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
上级 f5ec697e
隐藏空白更改
内联 并排
Showing with 252 addition and 246 deletion
drivers/gpu/drm/amd/amdgpu/amdgpu.h
浏览文件 @ 2990a1fc
...@@ -224,17 +224,18 @@ enum amdgpu_kiq_irq { ...@@ -224,17 +224,18 @@ enum amdgpu_kiq_irq {
AMDGPU_CP_KIQ_IRQ_LAST AMDGPU_CP_KIQ_IRQ_LAST
}; };
int amdgpu_set_clockgating_state(struct amdgpu_device *adev, int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
enum amd_ip_block_type block_type, enum amd_ip_block_type block_type,
enum amd_clockgating_state state); enum amd_clockgating_state state);
int amdgpu_set_powergating_state(struct amdgpu_device *adev, int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
enum amd_ip_block_type block_type, enum amd_ip_block_type block_type,
enum amd_powergating_state state); enum amd_powergating_state state);
void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
int amdgpu_wait_for_idle(struct amdgpu_device *adev, u32 *flags);
enum amd_ip_block_type block_type); int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
bool amdgpu_is_idle(struct amdgpu_device *adev, enum amd_ip_block_type block_type);
enum amd_ip_block_type block_type); bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
enum amd_ip_block_type block_type);
#define AMDGPU_MAX_IP_NUM 16 #define AMDGPU_MAX_IP_NUM 16
...@@ -259,15 +260,16 @@ struct amdgpu_ip_block { ...@@ -259,15 +260,16 @@ struct amdgpu_ip_block {
const struct amdgpu_ip_block_version *version; const struct amdgpu_ip_block_version *version;
}; };
int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
enum amd_ip_block_type type, enum amd_ip_block_type type,
u32 major, u32 minor); u32 major, u32 minor);
struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, struct amdgpu_ip_block *
enum amd_ip_block_type type); amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
enum amd_ip_block_type type);
int amdgpu_ip_block_add(struct amdgpu_device *adev, int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
const struct amdgpu_ip_block_version *ip_block_version); const struct amdgpu_ip_block_version *ip_block_version);
/* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
struct amdgpu_buffer_funcs { struct amdgpu_buffer_funcs {
......
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
浏览文件 @ 2990a1fc
...@@ -277,7 +277,7 @@ static int acp_hw_init(void *handle) ...@@ -277,7 +277,7 @@ static int acp_hw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
const struct amdgpu_ip_block *ip_block = const struct amdgpu_ip_block *ip_block =
amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
if (!ip_block) if (!ip_block)
return -EINVAL; return -EINVAL;
......
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
浏览文件 @ 2990a1fc
...@@ -937,9 +937,9 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { ...@@ -937,9 +937,9 @@ static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
.can_switch = amdgpu_switcheroo_can_switch, .can_switch = amdgpu_switcheroo_can_switch,
}; };
int amdgpu_set_clockgating_state(struct amdgpu_device *adev, int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
enum amd_ip_block_type block_type, enum amd_ip_block_type block_type,
enum amd_clockgating_state state) enum amd_clockgating_state state)
{ {
int i, r = 0; int i, r = 0;
...@@ -959,9 +959,9 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev, ...@@ -959,9 +959,9 @@ int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
return r; return r;
} }
int amdgpu_set_powergating_state(struct amdgpu_device *adev, int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
enum amd_ip_block_type block_type, enum amd_ip_block_type block_type,
enum amd_powergating_state state) enum amd_powergating_state state)
{ {
int i, r = 0; int i, r = 0;
...@@ -981,7 +981,8 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev, ...@@ -981,7 +981,8 @@ int amdgpu_set_powergating_state(struct amdgpu_device *adev,
return r; return r;
} }
void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
u32 *flags)
{ {
int i; int i;
...@@ -993,8 +994,8 @@ void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags) ...@@ -993,8 +994,8 @@ void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
} }
} }
int amdgpu_wait_for_idle(struct amdgpu_device *adev, int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
enum amd_ip_block_type block_type) enum amd_ip_block_type block_type)
{ {
int i, r; int i, r;
...@@ -1012,8 +1013,8 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev, ...@@ -1012,8 +1013,8 @@ int amdgpu_wait_for_idle(struct amdgpu_device *adev,
} }
bool amdgpu_is_idle(struct amdgpu_device *adev, bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
enum amd_ip_block_type block_type) enum amd_ip_block_type block_type)
{ {
int i; int i;
...@@ -1027,8 +1028,9 @@ bool amdgpu_is_idle(struct amdgpu_device *adev, ...@@ -1027,8 +1028,9 @@ bool amdgpu_is_idle(struct amdgpu_device *adev,
} }
struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, struct amdgpu_ip_block *
enum amd_ip_block_type type) amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,
enum amd_ip_block_type type)
{ {
int i; int i;
...@@ -1040,7 +1042,7 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, ...@@ -1040,7 +1042,7 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
} }
/** /**
* amdgpu_ip_block_version_cmp * amdgpu_device_ip_block_version_cmp
* *
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* @type: enum amd_ip_block_type * @type: enum amd_ip_block_type
...@@ -1050,11 +1052,11 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, ...@@ -1050,11 +1052,11 @@ struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
* return 0 if equal or greater * return 0 if equal or greater
* return 1 if smaller or the ip_block doesn't exist * return 1 if smaller or the ip_block doesn't exist
*/ */
int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,
enum amd_ip_block_type type, enum amd_ip_block_type type,
u32 major, u32 minor) u32 major, u32 minor)
{ {
struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type); struct amdgpu_ip_block *ip_block = amdgpu_device_ip_get_ip_block(adev, type);
if (ip_block && ((ip_block->version->major > major) || if (ip_block && ((ip_block->version->major > major) ||
((ip_block->version->major == major) && ((ip_block->version->major == major) &&
...@@ -1065,7 +1067,7 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, ...@@ -1065,7 +1067,7 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
} }
/** /**
* amdgpu_ip_block_add * amdgpu_device_ip_block_add
* *
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* @ip_block_version: pointer to the IP to add * @ip_block_version: pointer to the IP to add
...@@ -1073,8 +1075,8 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, ...@@ -1073,8 +1075,8 @@ int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
* Adds the IP block driver information to the collection of IPs * Adds the IP block driver information to the collection of IPs
* on the asic. * on the asic.
*/ */
int amdgpu_ip_block_add(struct amdgpu_device *adev, int amdgpu_device_ip_block_add(struct amdgpu_device *adev,
const struct amdgpu_ip_block_version *ip_block_version) const struct amdgpu_ip_block_version *ip_block_version)
{ {
if (!ip_block_version) if (!ip_block_version)
return -EINVAL; return -EINVAL;
...@@ -1569,10 +1571,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev) ...@@ -1569,10 +1571,10 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
amdgpu_virt_request_full_gpu(adev, false); amdgpu_virt_request_full_gpu(adev, false);
/* ungate SMC block first */ /* ungate SMC block first */
r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC, r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
AMD_CG_STATE_UNGATE); AMD_CG_STATE_UNGATE);
if (r) { if (r) {
DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r); DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n", r);
} }
for (i = adev->num_ip_blocks - 1; i >= 0; i--) { for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
......
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
浏览文件 @ 2990a1fc
...@@ -1278,16 +1278,16 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) ...@@ -1278,16 +1278,16 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
/* XXX select vce level based on ring/task */ /* XXX select vce level based on ring/task */
adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
mutex_unlock(&adev->pm.mutex); mutex_unlock(&adev->pm.mutex);
amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_UNGATE); AMD_CG_STATE_UNGATE);
amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_PG_STATE_UNGATE); AMD_PG_STATE_UNGATE);
amdgpu_pm_compute_clocks(adev); amdgpu_pm_compute_clocks(adev);
} else { } else {
amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_PG_STATE_GATE); AMD_PG_STATE_GATE);
amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_GATE); AMD_CG_STATE_GATE);
mutex_lock(&adev->pm.mutex); mutex_lock(&adev->pm.mutex);
adev->pm.dpm.vce_active = false; adev->pm.dpm.vce_active = false;
mutex_unlock(&adev->pm.mutex); mutex_unlock(&adev->pm.mutex);
...@@ -1584,7 +1584,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) ...@@ -1584,7 +1584,7 @@ static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
struct drm_device *ddev = adev->ddev; struct drm_device *ddev = adev->ddev;
u32 flags = 0; u32 flags = 0;
amdgpu_get_clockgating_state(adev, &flags); amdgpu_device_ip_get_clockgating_state(adev, &flags);
seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags); seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
amdgpu_parse_cg_state(m, flags); amdgpu_parse_cg_state(m, flags);
seq_printf(m, "\n"); seq_printf(m, "\n");
......
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
浏览文件 @ 2990a1fc
...@@ -244,7 +244,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) ...@@ -244,7 +244,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
} }
/* from uvd v5.0 HW addressing capacity increased to 64 bits */ /* from uvd v5.0 HW addressing capacity increased to 64 bits */
if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
adev->uvd.address_64_bit = true; adev->uvd.address_64_bit = true;
switch (adev->asic_type) { switch (adev->asic_type) {
...@@ -1153,10 +1153,10 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work) ...@@ -1153,10 +1153,10 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
} else { } else {
amdgpu_asic_set_uvd_clocks(adev, 0, 0); amdgpu_asic_set_uvd_clocks(adev, 0, 0);
/* shutdown the UVD block */ /* shutdown the UVD block */
amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_GATE); AMD_PG_STATE_GATE);
amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_GATE); AMD_CG_STATE_GATE);
} }
} else { } else {
schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT);
...@@ -1176,10 +1176,10 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) ...@@ -1176,10 +1176,10 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring)
amdgpu_dpm_enable_uvd(adev, true); amdgpu_dpm_enable_uvd(adev, true);
} else { } else {
amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_CG_STATE_UNGATE); AMD_CG_STATE_UNGATE);
amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_UNGATE); AMD_PG_STATE_UNGATE);
} }
} }
} }
......
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
浏览文件 @ 2990a1fc
...@@ -311,10 +311,10 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work) ...@@ -311,10 +311,10 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work)
amdgpu_dpm_enable_vce(adev, false); amdgpu_dpm_enable_vce(adev, false);
} else { } else {
amdgpu_asic_set_vce_clocks(adev, 0, 0); amdgpu_asic_set_vce_clocks(adev, 0, 0);
amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_PG_STATE_GATE); AMD_PG_STATE_GATE);
amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_GATE); AMD_CG_STATE_GATE);
} }
} else { } else {
schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT); schedule_delayed_work(&adev->vce.idle_work, VCE_IDLE_TIMEOUT);
...@@ -343,10 +343,10 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring) ...@@ -343,10 +343,10 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring)
amdgpu_dpm_enable_vce(adev, true); amdgpu_dpm_enable_vce(adev, true);
} else { } else {
amdgpu_asic_set_vce_clocks(adev, 53300, 40000); amdgpu_asic_set_vce_clocks(adev, 53300, 40000);
amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_CG_STATE_UNGATE); AMD_CG_STATE_UNGATE);
amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
AMD_PG_STATE_UNGATE); AMD_PG_STATE_UNGATE);
} }
} }
......
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
浏览文件 @ 2990a1fc
...@@ -741,7 +741,7 @@ void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev) ...@@ -741,7 +741,7 @@ void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
has_compute_vm_bug = false; has_compute_vm_bug = false;
ip_block = amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
if (ip_block) { if (ip_block) {
/* Compute has a VM bug for GFX version < 7. /* Compute has a VM bug for GFX version < 7.
Compute has a VM bug for GFX 8 MEC firmware version < 673.*/ Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
......
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
浏览文件 @ 2990a1fc
...@@ -891,12 +891,12 @@ static void ci_dpm_powergate_uvd(void *handle, bool gate) ...@@ -891,12 +891,12 @@ static void ci_dpm_powergate_uvd(void *handle, bool gate)
if (gate) { if (gate) {
/* stop the UVD block */ /* stop the UVD block */
amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_GATE); AMD_PG_STATE_GATE);
ci_update_uvd_dpm(adev, gate); ci_update_uvd_dpm(adev, gate);
} else { } else {
amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_UNGATE); AMD_PG_STATE_UNGATE);
ci_update_uvd_dpm(adev, gate); ci_update_uvd_dpm(adev, gate);
} }
} }
......
drivers/gpu/drm/amd/amdgpu/cik.c
浏览文件 @ 2990a1fc
...@@ -1974,77 +1974,77 @@ int cik_set_ip_blocks(struct amdgpu_device *adev) ...@@ -1974,77 +1974,77 @@ int cik_set_ip_blocks(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_BONAIRE: case CHIP_BONAIRE:
amdgpu_ip_block_add(adev, &cik_common_ip_block); amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_ip_block_add(adev, &cik_ih_ip_block); amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif #endif
else else
amdgpu_ip_block_add(adev, &dce_v8_2_ip_block); amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block);
amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
amdgpu_ip_block_add(adev, &cik_sdma_ip_block); amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break; break;
case CHIP_HAWAII: case CHIP_HAWAII:
amdgpu_ip_block_add(adev, &cik_common_ip_block); amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_ip_block_add(adev, &cik_ih_ip_block); amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif #endif
else else
amdgpu_ip_block_add(adev, &dce_v8_5_ip_block); amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block);
amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);
amdgpu_ip_block_add(adev, &cik_sdma_ip_block); amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break; break;
case CHIP_KAVERI: case CHIP_KAVERI:
amdgpu_ip_block_add(adev, &cik_common_ip_block); amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_ip_block_add(adev, &cik_ih_ip_block); amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif #endif
else else
amdgpu_ip_block_add(adev, &dce_v8_1_ip_block); amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);
amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);
amdgpu_ip_block_add(adev, &cik_sdma_ip_block); amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break; break;
case CHIP_KABINI: case CHIP_KABINI:
case CHIP_MULLINS: case CHIP_MULLINS:
amdgpu_ip_block_add(adev, &cik_common_ip_block); amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
amdgpu_ip_block_add(adev, &cik_ih_ip_block); amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif #endif
else else
amdgpu_ip_block_add(adev, &dce_v8_3_ip_block); amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block);
amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
amdgpu_ip_block_add(adev, &cik_sdma_ip_block); amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
amdgpu_ip_block_add(adev, &vce_v2_0_ip_block); amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
break; break;
default: default:
/* FIXME: not supported yet */ /* FIXME: not supported yet */
......
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
浏览文件 @ 2990a1fc
...@@ -5062,8 +5062,9 @@ static int gfx_v8_0_hw_fini(void *handle) ...@@ -5062,8 +5062,9 @@ static int gfx_v8_0_hw_fini(void *handle)
gfx_v8_0_cp_enable(adev, false); gfx_v8_0_cp_enable(adev, false);
gfx_v8_0_rlc_stop(adev); gfx_v8_0_rlc_stop(adev);
amdgpu_set_powergating_state(adev, amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_UNGATE); AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_UNGATE);
return 0; return 0;
} }
...@@ -5480,8 +5481,9 @@ static int gfx_v8_0_late_init(void *handle) ...@@ -5480,8 +5481,9 @@ static int gfx_v8_0_late_init(void *handle)
if (r) if (r)
return r; return r;
amdgpu_set_powergating_state(adev, amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_GFX, AMD_PG_STATE_GATE); AMD_IP_BLOCK_TYPE_GFX,
AMD_PG_STATE_GATE);
return 0; return 0;
} }
...@@ -5492,10 +5494,10 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade ...@@ -5492,10 +5494,10 @@ static void gfx_v8_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *ade
if ((adev->asic_type == CHIP_POLARIS11) || if ((adev->asic_type == CHIP_POLARIS11) ||
(adev->asic_type == CHIP_POLARIS12)) (adev->asic_type == CHIP_POLARIS12))
/* Send msg to SMU via Powerplay */ /* Send msg to SMU via Powerplay */
amdgpu_set_powergating_state(adev, amdgpu_device_ip_set_powergating_state(adev,
AMD_IP_BLOCK_TYPE_SMC, AMD_IP_BLOCK_TYPE_SMC,
enable ? enable ?
AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE); AMD_PG_STATE_GATE : AMD_PG_STATE_UNGATE);
WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0); WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
} }
......
drivers/gpu/drm/amd/amdgpu/kv_dpm.c
浏览文件 @ 2990a1fc
...@@ -1682,8 +1682,8 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate) ...@@ -1682,8 +1682,8 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate)
if (gate) { if (gate) {
/* stop the UVD block */ /* stop the UVD block */
ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_GATE); AMD_PG_STATE_GATE);
kv_update_uvd_dpm(adev, gate); kv_update_uvd_dpm(adev, gate);
if (pi->caps_uvd_pg) if (pi->caps_uvd_pg)
/* power off the UVD block */ /* power off the UVD block */
...@@ -1695,8 +1695,8 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate) ...@@ -1695,8 +1695,8 @@ static void kv_dpm_powergate_uvd(void *handle, bool gate)
/* re-init the UVD block */ /* re-init the UVD block */
kv_update_uvd_dpm(adev, gate); kv_update_uvd_dpm(adev, gate);
ret = amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,
AMD_PG_STATE_UNGATE); AMD_PG_STATE_UNGATE);
} }
} }
......
drivers/gpu/drm/amd/amdgpu/si.c
浏览文件 @ 2990a1fc
...@@ -1959,42 +1959,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev) ...@@ -1959,42 +1959,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_VERDE: case CHIP_VERDE:
case CHIP_TAHITI: case CHIP_TAHITI:
case CHIP_PITCAIRN: case CHIP_PITCAIRN:
amdgpu_ip_block_add(adev, &si_common_ip_block); amdgpu_device_ip_block_add(adev, &si_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
amdgpu_ip_block_add(adev, &si_ih_ip_block); amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
else else
amdgpu_ip_block_add(adev, &dce_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
amdgpu_ip_block_add(adev, &si_dma_ip_block); amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
/* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
/* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
break; break;
case CHIP_OLAND: case CHIP_OLAND:
amdgpu_ip_block_add(adev, &si_common_ip_block); amdgpu_device_ip_block_add(adev, &si_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
amdgpu_ip_block_add(adev, &si_ih_ip_block); amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
else else
amdgpu_ip_block_add(adev, &dce_v6_4_ip_block); amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
amdgpu_ip_block_add(adev, &si_dma_ip_block); amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
/* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */ /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */
/* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */ /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
break; break;
case CHIP_HAINAN: case CHIP_HAINAN:
amdgpu_ip_block_add(adev, &si_common_ip_block); amdgpu_device_ip_block_add(adev, &si_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
amdgpu_ip_block_add(adev, &si_ih_ip_block); amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
amdgpu_ip_block_add(adev, &si_dma_ip_block); amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
break; break;
default: default:
BUG(); BUG();
......
drivers/gpu/drm/amd/amdgpu/soc15.c
浏览文件 @ 2990a1fc
...@@ -533,43 +533,43 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) ...@@ -533,43 +533,43 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_VEGA10: case CHIP_VEGA10:
amdgpu_ip_block_add(adev, &vega10_common_ip_block); amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_ip_block_add(adev, &vega10_ih_ip_block); amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1) if (amdgpu_fw_load_type == 2 || amdgpu_fw_load_type == -1)
amdgpu_ip_block_add(adev, &psp_v3_1_ip_block); amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);
if (!amdgpu_sriov_vf(adev)) if (!amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#else #else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif #endif
amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
amdgpu_ip_block_add(adev, &uvd_v7_0_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);
amdgpu_ip_block_add(adev, &vce_v4_0_ip_block); amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
break; break;
case CHIP_RAVEN: case CHIP_RAVEN:
amdgpu_ip_block_add(adev, &vega10_common_ip_block); amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v9_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
amdgpu_ip_block_add(adev, &vega10_ih_ip_block); amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
amdgpu_ip_block_add(adev, &psp_v10_0_ip_block); amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#else #else
# warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15." # warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."
#endif #endif
amdgpu_ip_block_add(adev, &gfx_v9_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v4_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
amdgpu_ip_block_add(adev, &vcn_v1_0_ip_block); amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);
break; break;
default: default:
return -EINVAL; return -EINVAL;
...@@ -616,8 +616,8 @@ static int soc15_common_early_init(void *handle) ...@@ -616,8 +616,8 @@ static int soc15_common_early_init(void *handle)
adev->asic_funcs = &soc15_asic_funcs; adev->asic_funcs = &soc15_asic_funcs;
if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) && if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP) &&
(amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP))) (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_PSP)))
psp_enabled = true; psp_enabled = true;
adev->rev_id = soc15_get_rev_id(adev); adev->rev_id = soc15_get_rev_id(adev);
......
drivers/gpu/drm/amd/amdgpu/vi.c
浏览文件 @ 2990a1fc
...@@ -891,8 +891,8 @@ static int vi_common_early_init(void *handle) ...@@ -891,8 +891,8 @@ static int vi_common_early_init(void *handle)
adev->asic_funcs = &vi_asic_funcs; adev->asic_funcs = &vi_asic_funcs;
if (amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) && if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC) &&
(amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC))) (amdgpu_ip_block_mask & (1 << AMD_IP_BLOCK_TYPE_SMC)))
smc_enabled = true; smc_enabled = true;
adev->rev_id = vi_get_rev_id(adev); adev->rev_id = vi_get_rev_id(adev);
...@@ -1487,115 +1487,115 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) ...@@ -1487,115 +1487,115 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_TOPAZ: case CHIP_TOPAZ:
/* topaz has no DCE, UVD, VCE */ /* topaz has no DCE, UVD, VCE */
amdgpu_ip_block_add(adev, &vi_common_ip_block); amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v7_4_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
amdgpu_ip_block_add(adev, &iceland_ih_ip_block); amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v2_4_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
break; break;
case CHIP_FIJI: case CHIP_FIJI:
amdgpu_ip_block_add(adev, &vi_common_ip_block); amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v8_5_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
amdgpu_ip_block_add(adev, &tonga_ih_ip_block); amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif #endif
else else
amdgpu_ip_block_add(adev, &dce_v10_1_ip_block); amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
if (!amdgpu_sriov_vf(adev)) { if (!amdgpu_sriov_vf(adev)) {
amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
} }
break; break;
case CHIP_TONGA: case CHIP_TONGA:
amdgpu_ip_block_add(adev, &vi_common_ip_block); amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
amdgpu_ip_block_add(adev, &tonga_ih_ip_block); amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif #endif
else else
amdgpu_ip_block_add(adev, &dce_v10_0_ip_block); amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
if (!amdgpu_sriov_vf(adev)) { if (!amdgpu_sriov_vf(adev)) {
amdgpu_ip_block_add(adev, &uvd_v5_0_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
amdgpu_ip_block_add(adev, &vce_v3_0_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
} }
break; break;
case CHIP_POLARIS11: case CHIP_POLARIS11:
case CHIP_POLARIS10: case CHIP_POLARIS10:
case CHIP_POLARIS12: case CHIP_POLARIS12:
amdgpu_ip_block_add(adev, &vi_common_ip_block); amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
amdgpu_ip_block_add(adev, &tonga_ih_ip_block); amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif #endif
else else
amdgpu_ip_block_add(adev, &dce_v11_2_ip_block); amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v3_1_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
amdgpu_ip_block_add(adev, &uvd_v6_3_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
break; break;
case CHIP_CARRIZO: case CHIP_CARRIZO:
amdgpu_ip_block_add(adev, &vi_common_ip_block); amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
amdgpu_ip_block_add(adev, &cz_ih_ip_block); amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif #endif
else else
amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_0_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
amdgpu_ip_block_add(adev, &uvd_v6_0_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
amdgpu_ip_block_add(adev, &vce_v3_1_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
#if defined(CONFIG_DRM_AMD_ACP) #if defined(CONFIG_DRM_AMD_ACP)
amdgpu_ip_block_add(adev, &acp_ip_block); amdgpu_device_ip_block_add(adev, &acp_ip_block);
#endif #endif
break; break;
case CHIP_STONEY: case CHIP_STONEY:
amdgpu_ip_block_add(adev, &vi_common_ip_block); amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
amdgpu_ip_block_add(adev, &gmc_v8_0_ip_block); amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
amdgpu_ip_block_add(adev, &cz_ih_ip_block); amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block); amdgpu_device_ip_block_add(adev, &amdgpu_pp_ip_block);
if (adev->enable_virtual_display) if (adev->enable_virtual_display)
amdgpu_ip_block_add(adev, &dce_virtual_ip_block); amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
#if defined(CONFIG_DRM_AMD_DC) #if defined(CONFIG_DRM_AMD_DC)
else if (amdgpu_device_has_dc_support(adev)) else if (amdgpu_device_has_dc_support(adev))
amdgpu_ip_block_add(adev, &dm_ip_block); amdgpu_device_ip_block_add(adev, &dm_ip_block);
#endif #endif
else else
amdgpu_ip_block_add(adev, &dce_v11_0_ip_block); amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
amdgpu_ip_block_add(adev, &gfx_v8_1_ip_block); amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
amdgpu_ip_block_add(adev, &sdma_v3_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
amdgpu_ip_block_add(adev, &uvd_v6_2_ip_block); amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
amdgpu_ip_block_add(adev, &vce_v3_4_ip_block); amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
#if defined(CONFIG_DRM_AMD_ACP) #if defined(CONFIG_DRM_AMD_ACP)
amdgpu_ip_block_add(adev, &acp_ip_block); amdgpu_device_ip_block_add(adev, &acp_ip_block);
#endif #endif
break; break;
default: default:
......
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或