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raspberrypi-kernel
提交 1d7180e2 编写于 作者: S Shawn Guo
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Merge tag 'imx-cleanup-3.9' into imx6q-cpuidle

上级 a49f0d1e 7356420c
展开全部 隐藏空白更改
内联 并排
Showing with 11 addition and 1955 deletion
arch/arm/Kconfig.debug
浏览文件 @ 1d7180e2
......@@ -219,12 +219,12 @@ choice
Say Y here if you want kernel low-level debugging support
on i.MX51.
config DEBUG_IMX50_IMX53_UART
bool "i.MX50 and i.MX53 Debug UART"
depends on SOC_IMX50 || SOC_IMX53
config DEBUG_IMX53_UART
bool "i.MX53 Debug UART"
depends on SOC_IMX53
help
Say Y here if you want kernel low-level debugging support
on i.MX50 or i.MX53.
on i.MX53.
config DEBUG_IMX6Q_UART
bool "i.MX6Q Debug UART"
......@@ -497,7 +497,7 @@ config DEBUG_LL_INCLUDE
DEBUG_IMX21_IMX27_UART || \
DEBUG_IMX31_IMX35_UART || \
DEBUG_IMX51_UART || \
DEBUG_IMX50_IMX53_UART ||\
DEBUG_IMX53_UART ||\
DEBUG_IMX6Q_UART
default "debug/highbank.S" if DEBUG_HIGHBANK_UART
default "debug/mvebu.S" if DEBUG_MVEBU_UART
......
arch/arm/configs/imx_v6_v7_defconfig
浏览文件 @ 1d7180e2
......@@ -32,7 +32,6 @@ CONFIG_MACH_PCM043=y
CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_VPR200=y
CONFIG_MACH_IMX51_DT=y
CONFIG_MACH_MX51_3DS=y
CONFIG_MACH_EUKREA_CPUIMX51SD=y
CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y
......
arch/arm/include/debug/imx.S
浏览文件 @ 1d7180e2
......@@ -34,7 +34,7 @@
#define UART_PADDR 0x43f90000
#elif defined (CONFIG_DEBUG_IMX51_UART)
#define UART_PADDR 0x73fbc000
#elif defined (CONFIG_DEBUG_IMX50_IMX53_UART)
#elif defined (CONFIG_DEBUG_IMX53_UART)
#define UART_PADDR 0x53fbc000
#elif defined (CONFIG_DEBUG_IMX6Q_UART)
#define UART_PADDR IMX6Q_DEBUG_UART_BASE
......
arch/arm/mach-imx/Kconfig
浏览文件 @ 1d7180e2
......@@ -95,9 +95,6 @@ config MACH_MX27
config ARCH_MX5
bool
config ARCH_MX50
bool
config ARCH_MX51
bool
......@@ -164,11 +161,6 @@ config SOC_IMX5
select CPU_V7
select MXC_TZIC
config SOC_IMX50
bool
select ARCH_MX50
select SOC_IMX5
config SOC_IMX51
bool
select ARCH_MX5
......@@ -738,25 +730,10 @@ endif
if ARCH_MULTI_V7
comment "i.MX5 platforms:"
config MACH_MX50_RDP
bool "Support MX50 reference design platform"
depends on BROKEN
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select SOC_IMX50
help
Include support for MX50 reference design platform (RDP) board. This
includes specific configurations for the board and its peripherals.
comment "i.MX51 machines:"
config MACH_IMX51_DT
bool "Support i.MX51 platforms from device tree"
select MACH_MX51_BABBAGE
select SOC_IMX51
help
Include support for Freescale i.MX51 based platforms
......@@ -777,19 +754,6 @@ config MACH_MX51_BABBAGE
u-boot. This includes specific configurations for the board and its
peripherals.
config MACH_MX51_3DS
bool "Support MX51PDK (3DS)"
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_DEBUG_BOARD
select SOC_IMX51
help
Include support for MX51PDK (3DS) platform. This includes specific
configurations for the board and its peripherals.
config MACH_EUKREA_CPUIMX51SD
bool "Support Eukrea CPUIMX51SD module"
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
......
arch/arm/mach-imx/Makefile
浏览文件 @ 1d7180e2
......@@ -88,7 +88,6 @@ obj-$(CONFIG_MACH_EUKREA_CPUIMX35SD) += mach-cpuimx35.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
obj-$(CONFIG_DEBUG_LL) += lluart.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
......@@ -103,10 +102,8 @@ endif
# i.MX5 based machines
obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
......
arch/arm/mach-imx/Makefile.boot
浏览文件 @ 1d7180e2
......@@ -22,10 +22,6 @@ zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000
params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
zreladdr-$(CONFIG_SOC_IMX50) += 0x70008000
params_phys-$(CONFIG_SOC_IMX50) := 0x70000100
initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000
zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000
params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
......
arch/arm/mach-imx/clk-imx6q.c
浏览文件 @ 1d7180e2
......@@ -56,8 +56,6 @@
static void __iomem *ccm_base;
void __init imx6q_clock_map_io(void) { }
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
{
u32 val = readl_relaxed(ccm_base + CLPCR);
......
arch/arm/mach-imx/common.h
浏览文件 @ 1d7180e2
......@@ -21,7 +21,6 @@ extern void mx25_map_io(void);
extern void mx27_map_io(void);
extern void mx31_map_io(void);
extern void mx35_map_io(void);
extern void mx50_map_io(void);
extern void mx51_map_io(void);
extern void mx53_map_io(void);
extern void imx1_init_early(void);
......@@ -30,7 +29,6 @@ extern void imx25_init_early(void);
extern void imx27_init_early(void);
extern void imx31_init_early(void);
extern void imx35_init_early(void);
extern void imx50_init_early(void);
extern void imx51_init_early(void);
extern void imx53_init_early(void);
extern void mxc_init_irq(void __iomem *);
......@@ -41,7 +39,6 @@ extern void mx25_init_irq(void);
extern void mx27_init_irq(void);
extern void mx31_init_irq(void);
extern void mx35_init_irq(void);
extern void mx50_init_irq(void);
extern void mx51_init_irq(void);
extern void mx53_init_irq(void);
extern void imx1_soc_init(void);
......@@ -50,7 +47,6 @@ extern void imx25_soc_init(void);
extern void imx27_soc_init(void);
extern void imx31_soc_init(void);
extern void imx35_soc_init(void);
extern void imx50_soc_init(void);
extern void imx51_soc_init(void);
extern void imx51_init_late(void);
extern void imx53_init_late(void);
......@@ -109,18 +105,12 @@ void tzic_handle_irq(struct pt_regs *);
#define imx27_handle_irq avic_handle_irq
#define imx31_handle_irq avic_handle_irq
#define imx35_handle_irq avic_handle_irq
#define imx50_handle_irq tzic_handle_irq
#define imx51_handle_irq tzic_handle_irq
#define imx53_handle_irq tzic_handle_irq
#define imx6q_handle_irq gic_handle_irq
extern void imx_enable_cpu(int cpu, bool enable);
extern void imx_set_cpu_jump(int cpu, void *jump_addr);
#ifdef CONFIG_DEBUG_LL
extern void imx_lluart_map_io(void);
#else
static inline void imx_lluart_map_io(void) {}
#endif
extern void v7_cpu_resume(void);
extern u32 *pl310_get_save_ptr(void);
#ifdef CONFIG_SMP
......@@ -139,7 +129,6 @@ extern void imx_gpc_init(void);
extern void imx_gpc_pre_suspend(void);
extern void imx_gpc_post_resume(void);
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_clock_map_io(void);
extern void imx_cpu_die(unsigned int cpu);
......
arch/arm/mach-imx/cpu-imx5.c
浏览文件 @ 1d7180e2
......@@ -22,7 +22,6 @@
static int mx5_cpu_rev = -1;
#define IIM_SREV 0x24
#define MX50_HW_ADADIG_DIGPROG 0xB0
static int get_mx51_srev(void)
{
......@@ -108,41 +107,3 @@ int mx53_revision(void)
return mx5_cpu_rev;
}
EXPORT_SYMBOL(mx53_revision);
static int get_mx50_srev(void)
{
void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
u32 rev;
if (!anatop) {
mx5_cpu_rev = -EINVAL;
return 0;
}
rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
rev &= 0xff;
iounmap(anatop);
if (rev == 0x0)
return IMX_CHIP_REVISION_1_0;
else if (rev == 0x1)
return IMX_CHIP_REVISION_1_1;
return 0;
}
/*
* Returns:
* the silicon revision of the cpu
* -EINVAL - not a mx50
*/
int mx50_revision(void)
{
if (!cpu_is_mx50())
return -EINVAL;
if (mx5_cpu_rev == -1)
mx5_cpu_rev = get_mx50_srev();
return mx5_cpu_rev;
}
EXPORT_SYMBOL(mx50_revision);
arch/arm/mach-imx/devices-imx50.h 已删除 100644 → 0
浏览文件 @ a49f0d1e
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include "devices/devices-common.h"
extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
#define imx50_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
extern const struct imx_fec_data imx50_fec_data;
#define imx50_add_fec(pdata) \
imx_add_fec(&imx50_fec_data, pdata)
extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
#define imx50_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
arch/arm/mach-imx/devices/Kconfig
浏览文件 @ 1d7180e2
config IMX_HAVE_PLATFORM_FEC
bool
default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX50 || SOC_IMX51 || SOC_IMX53
default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51 || SOC_IMX53
config IMX_HAVE_PLATFORM_FLEXCAN
bool
......
arch/arm/mach-imx/devices/platform-fec.c
浏览文件 @ 1d7180e2
......@@ -35,12 +35,6 @@ const struct imx_fec_data imx35_fec_data __initconst =
imx_fec_data_entry_single(MX35, "imx27-fec");
#endif
#ifdef CONFIG_SOC_IMX50
/* i.mx50 has the i.mx25 type fec */
const struct imx_fec_data imx50_fec_data __initconst =
imx_fec_data_entry_single(MX50, "imx25-fec");
#endif
#ifdef CONFIG_SOC_IMX51
/* i.mx51 has the i.mx27 type fec */
const struct imx_fec_data imx51_fec_data __initconst =
......
arch/arm/mach-imx/devices/platform-imx-i2c.c
浏览文件 @ 1d7180e2
......@@ -70,16 +70,6 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_SOC_IMX50
const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst = {
#define imx50_imx_i2c_data_entry(_id, _hwid) \
imx_imx_i2c_data_entry(MX50, "imx21-i2c", _id, _hwid, SZ_4K)
imx50_imx_i2c_data_entry(0, 1),
imx50_imx_i2c_data_entry(1, 2),
imx50_imx_i2c_data_entry(2, 3),
};
#endif /* ifdef CONFIG_SOC_IMX51 */
#ifdef CONFIG_SOC_IMX51
const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
#define imx51_imx_i2c_data_entry(_id, _hwid) \
......
arch/arm/mach-imx/devices/platform-imx-uart.c
浏览文件 @ 1d7180e2
......@@ -94,18 +94,6 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX35 */
#ifdef CONFIG_SOC_IMX50
const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = {
#define imx50_imx_uart_data_entry(_id, _hwid) \
imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K)
imx50_imx_uart_data_entry(0, 1),
imx50_imx_uart_data_entry(1, 2),
imx50_imx_uart_data_entry(2, 3),
imx50_imx_uart_data_entry(3, 4),
imx50_imx_uart_data_entry(4, 5),
};
#endif /* ifdef CONFIG_SOC_IMX50 */
#ifdef CONFIG_SOC_IMX51
const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
#define imx51_imx_uart_data_entry(_id, _hwid) \
......
arch/arm/mach-imx/hardware.h
浏览文件 @ 1d7180e2
......@@ -72,11 +72,6 @@
* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
* X_MEMC 0xb8000000+0x010000 -> 0xf5c00000+0x010000
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
* mx50:
* TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
* AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
* AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
* mx51:
* TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
* IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
......@@ -108,7 +103,6 @@
#include "mxc.h"
#include "mx6q.h"
#include "mx50.h"
#include "mx51.h"
#include "mx53.h"
#include "mx3x.h"
......
arch/arm/mach-imx/iomux-mx50.h 已删除 100644 → 0
浏览文件 @ a49f0d1e
此差异已折叠。
arch/arm/mach-imx/lluart.c 已删除 100644 → 0
浏览文件 @ a49f0d1e
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <asm/page.h>
#include <asm/sizes.h>
#include <asm/mach/map.h>
#include "hardware.h"
#define IMX6Q_UART1_BASE_ADDR 0x02020000
#define IMX6Q_UART2_BASE_ADDR 0x021e8000
#define IMX6Q_UART3_BASE_ADDR 0x021ec000
#define IMX6Q_UART4_BASE_ADDR 0x021f0000
#define IMX6Q_UART5_BASE_ADDR 0x021f4000
/*
* IMX6Q_UART_BASE_ADDR is put in the middle to force the expansion
* of IMX6Q_UART##n##_BASE_ADDR.
*/
#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
#define IMX6Q_DEBUG_UART_BASE IMX6Q_UART_BASE(CONFIG_DEBUG_IMX6Q_UART_PORT)
static struct map_desc imx_lluart_desc = {
#ifdef CONFIG_DEBUG_IMX6Q_UART
.virtual = IMX_IO_P2V(IMX6Q_DEBUG_UART_BASE),
.pfn = __phys_to_pfn(IMX6Q_DEBUG_UART_BASE),
.length = 0x4000,
.type = MT_DEVICE,
#endif
};
void __init imx_lluart_map_io(void)
{
if (imx_lluart_desc.virtual)
iotable_init(&imx_lluart_desc, 1);
}
arch/arm/mach-imx/mach-imx6q.c
浏览文件 @ 1d7180e2
......@@ -31,6 +31,7 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>
......@@ -216,9 +217,8 @@ static void __init imx6q_init_late(void)
static void __init imx6q_map_io(void)
{
imx_lluart_map_io();
debug_ll_io_init();
imx_scu_map_io();
imx6q_clock_map_io();
}
static const struct of_device_id imx6q_irq_match[] __initconst = {
......
arch/arm/mach-imx/mach-mx50_rdp.c 已删除 100644 → 0
浏览文件 @ a49f0d1e
/*
* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "common.h"
#include "devices-imx50.h"
#include "hardware.h"
#include "iomux-mx50.h"
#define FEC_EN IMX_GPIO_NR(6, 23)
#define FEC_RESET_B IMX_GPIO_NR(4, 12)
static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
/* SD1 */
MX50_PAD_ECSPI2_SS0__GPIO_4_19,
MX50_PAD_EIM_CRE__GPIO_1_27,
MX50_PAD_SD1_CMD__SD1_CMD,
MX50_PAD_SD1_CLK__SD1_CLK,
MX50_PAD_SD1_D0__SD1_D0,
MX50_PAD_SD1_D1__SD1_D1,
MX50_PAD_SD1_D2__SD1_D2,
MX50_PAD_SD1_D3__SD1_D3,
/* SD2 */
MX50_PAD_SD2_CD__GPIO_5_17,
MX50_PAD_SD2_WP__GPIO_5_16,
MX50_PAD_SD2_CMD__SD2_CMD,
MX50_PAD_SD2_CLK__SD2_CLK,
MX50_PAD_SD2_D0__SD2_D0,
MX50_PAD_SD2_D1__SD2_D1,
MX50_PAD_SD2_D2__SD2_D2,
MX50_PAD_SD2_D3__SD2_D3,
MX50_PAD_SD2_D4__SD2_D4,
MX50_PAD_SD2_D5__SD2_D5,
MX50_PAD_SD2_D6__SD2_D6,
MX50_PAD_SD2_D7__SD2_D7,
/* SD3 */
MX50_PAD_SD3_CMD__SD3_CMD,
MX50_PAD_SD3_CLK__SD3_CLK,
MX50_PAD_SD3_D0__SD3_D0,
MX50_PAD_SD3_D1__SD3_D1,
MX50_PAD_SD3_D2__SD3_D2,
MX50_PAD_SD3_D3__SD3_D3,
MX50_PAD_SD3_D4__SD3_D4,
MX50_PAD_SD3_D5__SD3_D5,
MX50_PAD_SD3_D6__SD3_D6,
MX50_PAD_SD3_D7__SD3_D7,
/* PWR_INT */
MX50_PAD_ECSPI2_MISO__GPIO_4_18,
/* UART pad setting */
MX50_PAD_UART1_TXD__UART1_TXD,
MX50_PAD_UART1_RXD__UART1_RXD,
MX50_PAD_UART1_RTS__UART1_RTS,
MX50_PAD_UART2_TXD__UART2_TXD,
MX50_PAD_UART2_RXD__UART2_RXD,
MX50_PAD_UART2_CTS__UART2_CTS,
MX50_PAD_UART2_RTS__UART2_RTS,
MX50_PAD_I2C1_SCL__I2C1_SCL,
MX50_PAD_I2C1_SDA__I2C1_SDA,
MX50_PAD_I2C2_SCL__I2C2_SCL,
MX50_PAD_I2C2_SDA__I2C2_SDA,
MX50_PAD_EPITO__USBH1_PWR,
/* Need to comment below line if
* one needs to debug owire.
*/
MX50_PAD_OWIRE__USBH1_OC,
/* using gpio to control otg pwr */
MX50_PAD_PWM2__GPIO_6_25,
MX50_PAD_I2C3_SCL__USBOTG_OC,
MX50_PAD_SSI_RXC__FEC_MDIO,
MX50_PAD_SSI_RXFS__FEC_MDC,
MX50_PAD_DISP_D0__FEC_TXCLK,
MX50_PAD_DISP_D1__FEC_RX_ER,
MX50_PAD_DISP_D2__FEC_RX_DV,
MX50_PAD_DISP_D3__FEC_RXD1,
MX50_PAD_DISP_D4__FEC_RXD0,
MX50_PAD_DISP_D5__FEC_TX_EN,
MX50_PAD_DISP_D6__FEC_TXD1,
MX50_PAD_DISP_D7__FEC_TXD0,
MX50_PAD_I2C3_SDA__GPIO_6_23,
MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
MX50_PAD_CSPI_SS0__CSPI_SS0,
MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
MX50_PAD_CSPI_MOSI__CSPI_MOSI,
MX50_PAD_CSPI_MISO__CSPI_MISO,
/* SGTL500_OSC_EN */
MX50_PAD_UART1_CTS__GPIO_6_8,
/* SGTL_AMP_SHDN */
MX50_PAD_UART3_RXD__GPIO_6_15,
/* Keypad */
MX50_PAD_KEY_COL0__KEY_COL0,
MX50_PAD_KEY_ROW0__KEY_ROW0,
MX50_PAD_KEY_COL1__KEY_COL1,
MX50_PAD_KEY_ROW1__KEY_ROW1,
MX50_PAD_KEY_COL2__KEY_COL2,
MX50_PAD_KEY_ROW2__KEY_ROW2,
MX50_PAD_KEY_COL3__KEY_COL3,
MX50_PAD_KEY_ROW3__KEY_ROW3,
MX50_PAD_EIM_DA0__KEY_COL4,
MX50_PAD_EIM_DA1__KEY_ROW4,
MX50_PAD_EIM_DA2__KEY_COL5,
MX50_PAD_EIM_DA3__KEY_ROW5,
MX50_PAD_EIM_DA4__KEY_COL6,
MX50_PAD_EIM_DA5__KEY_ROW6,
MX50_PAD_EIM_DA6__KEY_COL7,
MX50_PAD_EIM_DA7__KEY_ROW7,
/*EIM pads */
MX50_PAD_EIM_DA8__GPIO_1_8,
MX50_PAD_EIM_DA9__GPIO_1_9,
MX50_PAD_EIM_DA10__GPIO_1_10,
MX50_PAD_EIM_DA11__GPIO_1_11,
MX50_PAD_EIM_DA12__GPIO_1_12,
MX50_PAD_EIM_DA13__GPIO_1_13,
MX50_PAD_EIM_DA14__GPIO_1_14,
MX50_PAD_EIM_DA15__GPIO_1_15,
MX50_PAD_EIM_CS2__GPIO_1_16,
MX50_PAD_EIM_CS1__GPIO_1_17,
MX50_PAD_EIM_CS0__GPIO_1_18,
MX50_PAD_EIM_EB0__GPIO_1_19,
MX50_PAD_EIM_EB1__GPIO_1_20,
MX50_PAD_EIM_WAIT__GPIO_1_21,
MX50_PAD_EIM_BCLK__GPIO_1_22,
MX50_PAD_EIM_RDY__GPIO_1_23,
MX50_PAD_EIM_OE__GPIO_1_24,
};
/* Serial ports */
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static const struct fec_platform_data fec_data __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
};
static inline void mx50_rdp_fec_reset(void)
{
gpio_request(FEC_EN, "fec-en");
gpio_direction_output(FEC_EN, 0);
gpio_request(FEC_RESET_B, "fec-reset_b");
gpio_direction_output(FEC_RESET_B, 0);
msleep(1);
gpio_set_value(FEC_RESET_B, 1);
}
static const struct imxi2c_platform_data i2c_data __initconst = {
.bitrate = 100000,
};
/*
* Board specific initialization.
*/
static void __init mx50_rdp_board_init(void)
{
imx50_soc_init();
mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
ARRAY_SIZE(mx50_rdp_pads));
imx50_add_imx_uart(0, &uart_pdata);
imx50_add_imx_uart(1, &uart_pdata);
mx50_rdp_fec_reset();
imx50_add_fec(&fec_data);
imx50_add_imx_i2c(0, &i2c_data);
imx50_add_imx_i2c(1, &i2c_data);
imx50_add_imx_i2c(2, &i2c_data);
}
static void __init mx50_rdp_timer_init(void)
{
mx50_clocks_init(32768, 24000000, 22579200);
}
static struct sys_timer mx50_rdp_timer = {
.init = mx50_rdp_timer_init,
};
MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
.map_io = mx50_map_io,
.init_early = imx50_init_early,
.init_irq = mx50_init_irq,
.handle_irq = imx50_handle_irq,
.timer = &mx50_rdp_timer,
.init_machine = mx50_rdp_board_init,
.restart = mxc_restart,
MACHINE_END
arch/arm/mach-imx/mach-mx51_3ds.c 已删除 100644 → 0
浏览文件 @ a49f0d1e
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "3ds_debugboard.h"
#include "common.h"
#include "devices-imx51.h"
#include "hardware.h"
#include "iomux-mx51.h"
#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
static iomux_v3_cfg_t mx51_3ds_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
MX51_PAD_UART1_RTS__UART1_RTS,
MX51_PAD_UART1_CTS__UART1_CTS,
/* UART2 */
MX51_PAD_UART2_RXD__UART2_RXD,
MX51_PAD_UART2_TXD__UART2_TXD,
MX51_PAD_EIM_D25__UART2_CTS,
MX51_PAD_EIM_D26__UART2_RTS,
/* UART3 */
MX51_PAD_UART3_RXD__UART3_RXD,
MX51_PAD_UART3_TXD__UART3_TXD,
MX51_PAD_EIM_D24__UART3_CTS,
MX51_PAD_EIM_D27__UART3_RTS,
/* CPLD PARENT IRQ PIN */
MX51_PAD_GPIO1_6__GPIO1_6,
/* KPP */
MX51_PAD_KEY_ROW0__KEY_ROW0,
MX51_PAD_KEY_ROW1__KEY_ROW1,
MX51_PAD_KEY_ROW2__KEY_ROW2,
MX51_PAD_KEY_ROW3__KEY_ROW3,
MX51_PAD_KEY_COL0__KEY_COL0,
MX51_PAD_KEY_COL1__KEY_COL1,
MX51_PAD_KEY_COL2__KEY_COL2,
MX51_PAD_KEY_COL3__KEY_COL3,
MX51_PAD_KEY_COL4__KEY_COL4,
MX51_PAD_KEY_COL5__KEY_COL5,
/* eCSPI2 */
MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
MX51_PAD_NANDF_RB3__ECSPI2_MISO,
MX51_PAD_NANDF_D15__ECSPI2_MOSI,
MX51_PAD_NANDF_D12__GPIO3_28,
};
/* Serial ports */
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static int mx51_3ds_board_keymap[] = {
KEY(0, 0, KEY_1),
KEY(0, 1, KEY_2),
KEY(0, 2, KEY_3),
KEY(0, 3, KEY_F1),
KEY(0, 4, KEY_UP),
KEY(0, 5, KEY_F2),
KEY(1, 0, KEY_4),
KEY(1, 1, KEY_5),
KEY(1, 2, KEY_6),
KEY(1, 3, KEY_LEFT),
KEY(1, 4, KEY_SELECT),
KEY(1, 5, KEY_RIGHT),
KEY(2, 0, KEY_7),
KEY(2, 1, KEY_8),
KEY(2, 2, KEY_9),
KEY(2, 3, KEY_F3),
KEY(2, 4, KEY_DOWN),
KEY(2, 5, KEY_F4),
KEY(3, 0, KEY_0),
KEY(3, 1, KEY_OK),
KEY(3, 2, KEY_ESC),
KEY(3, 3, KEY_ENTER),
KEY(3, 4, KEY_MENU),
KEY(3, 5, KEY_BACK)
};
static const struct matrix_keymap_data mx51_3ds_map_data __initconst = {
.keymap = mx51_3ds_board_keymap,
.keymap_size = ARRAY_SIZE(mx51_3ds_board_keymap),
};
static int mx51_3ds_spi2_cs[] = {
MXC_SPI_CS(0),
MX51_3DS_ECSPI2_CS,
};
static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
.chipselect = mx51_3ds_spi2_cs,
.num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
};
static struct spi_board_info mx51_3ds_spi_nor_device[] = {
{
.modalias = "m25p80",
.max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
.bus_num = 1,
.chip_select = 1,
.mode = SPI_MODE_0,
.platform_data = NULL,},
};
/*
* Board specific initialization.
*/
static void __init mx51_3ds_init(void)
{
imx51_soc_init();
mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
ARRAY_SIZE(mx51_3ds_pads));
imx51_add_imx_uart(0, &uart_pdata);
imx51_add_imx_uart(1, &uart_pdata);
imx51_add_imx_uart(2, &uart_pdata);
imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
spi_register_board_info(mx51_3ds_spi_nor_device,
ARRAY_SIZE(mx51_3ds_spi_nor_device));
if (mxc_expio_init(MX51_CS5_BASE_ADDR, IMX_GPIO_NR(1, 6)))
printk(KERN_WARNING "Init of the debugboard failed, all "
"devices on the board are unusable.\n");
imx51_add_sdhci_esdhc_imx(0, NULL);
imx51_add_imx_keypad(&mx51_3ds_map_data);
imx51_add_imx2_wdt(0);
}
static void __init mx51_3ds_timer_init(void)
{
mx51_clocks_init(32768, 24000000, 22579200, 0);
}
static struct sys_timer mx51_3ds_timer = {
.init = mx51_3ds_timer_init,
};
MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
/* Maintainer: Freescale Semiconductor, Inc. */
.atag_offset = 0x100,
.map_io = mx51_map_io,
.init_early = imx51_init_early,
.init_irq = mx51_init_irq,
.handle_irq = imx51_handle_irq,
.timer = &mx51_3ds_timer,
.init_machine = mx51_3ds_init,
.init_late = imx51_init_late,
.restart = mxc_restart,
MACHINE_END
arch/arm/mach-imx/mm-imx5.c
浏览文件 @ 1d7180e2
......@@ -23,16 +23,6 @@
#include "hardware.h"
#include "iomux-v3.h"
/*
* Define the MX50 memory map.
*/
static struct map_desc mx50_io_desc[] __initdata = {
imx_map_entry(MX50, TZIC, MT_DEVICE),
imx_map_entry(MX50, SPBA0, MT_DEVICE),
imx_map_entry(MX50, AIPS1, MT_DEVICE),
imx_map_entry(MX50, AIPS2, MT_DEVICE),
};
/*
* Define the MX51 memory map.
*/
......@@ -59,11 +49,6 @@ static struct map_desc mx53_io_desc[] __initdata = {
* system startup to create static physical to virtual memory mappings
* for the IO modules.
*/
void __init mx50_map_io(void)
{
iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
}
void __init mx51_map_io(void)
{
iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
......@@ -74,13 +59,6 @@ void __init mx53_map_io(void)
iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
}
void __init imx50_init_early(void)
{
mxc_set_cpu_type(MXC_CPU_MX50);
mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
}
/*
* The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
* the Freescale marketing division. However this did not remove the
......@@ -115,11 +93,6 @@ void __init imx53_init_early(void)
mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
}
void __init mx50_init_irq(void)
{
tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
}
void __init mx51_init_irq(void)
{
tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
......@@ -148,31 +121,10 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
.script_addrs = &imx51_sdma_script,
};
static const struct resource imx50_audmux_res[] __initconst = {
DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
};
static const struct resource imx51_audmux_res[] __initconst = {
DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
};
void __init imx50_soc_init(void)
{
mxc_device_init();
/* i.mx50 has the i.mx35 type gpio */
mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
/* i.mx50 has the i.mx31 type audmux */
platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
ARRAY_SIZE(imx50_audmux_res));
}
void __init imx51_soc_init(void)
{
mxc_device_init();
......
arch/arm/mach-imx/mx50.h 已删除 100644 → 0
浏览文件 @ a49f0d1e
#ifndef __MACH_MX50_H__
#define __MACH_MX50_H__
/*
* IROM
*/
#define MX50_IROM_BASE_ADDR 0x0
#define MX50_IROM_SIZE SZ_64K
/* TZIC */
#define MX50_TZIC_BASE_ADDR 0x0fffc000
#define MX50_TZIC_SIZE SZ_16K
/*
* IRAM
*/
#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */
#define MX50_IRAM_PARTITIONS 16
#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */
/*
* Databahn
*/
#define MX50_DATABAHN_BASE_ADDR 0x14000000
/*
* Graphics Memory of GPU
*/
#define MX50_GPU2D_BASE_ADDR 0x20000000
#define MX50_DEBUG_BASE_ADDR 0x40000000
#define MX50_DEBUG_SIZE SZ_1M
#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000)
#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000)
#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000)
#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000)
#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000)
#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000)
#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000)
#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000)
#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000)
#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000)
#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000)
#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000)
#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000)
#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000)
#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000)
#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000)
#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000)
#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000)
#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000)
#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000)
#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000)
#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000)
/*
* SPBA global module enabled #0
*/
#define MX50_SPBA0_BASE_ADDR 0x50000000
#define MX50_SPBA0_SIZE SZ_1M
#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000)
#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000)
#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000)
#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000)
#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000)
#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000)
#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000)
/*
* AIPS 1
*/
#define MX50_AIPS1_BASE_ADDR 0x53f00000
#define MX50_AIPS1_SIZE SZ_1M
#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000)
#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000)
#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000)
#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000)
#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000)
#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000)
#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000)
#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000)
#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000)
#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000)
#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000)
#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000)
#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000)
#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000)
#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000)
#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000)
#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000)
#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000)
#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000)
#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000)
#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000)
#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000)
#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000)
#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000)
/*
* AIPS 2
*/
#define MX50_AIPS2_BASE_ADDR 0x63f00000
#define MX50_AIPS2_SIZE SZ_1M
#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000)
#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000)
#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000)
#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000)
#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000)
#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000)
#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000)
#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000)
#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000)
#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000)
#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000)
#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000)
#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000)
#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000)
#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000)
#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000)
#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000)
/*
* Memory regions and CS
*/
#define MX50_CSD0_BASE_ADDR 0x70000000
#define MX50_CSD1_BASE_ADDR 0xb0000000
#define MX50_CS0_BASE_ADDR 0xf0000000
#define MX50_IO_P2V(x) IMX_IO_P2V(x)
#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x))
/*
* defines for SPBA modules
*/
#define MX50_SPBA_SDHC1 0x04
#define MX50_SPBA_SDHC2 0x08
#define MX50_SPBA_UART3 0x0c
#define MX50_SPBA_CSPI1 0x10
#define MX50_SPBA_SSI2 0x14
#define MX50_SPBA_SDHC3 0x20
#define MX50_SPBA_SDHC4 0x24
#define MX50_SPBA_SPDIF 0x28
#define MX50_SPBA_ATA 0x30
#define MX50_SPBA_SLIM 0x34
#define MX50_SPBA_HSI2C 0x38
#define MX50_SPBA_CTRL 0x3c
/*
* DMA request assignments
*/
#define MX50_DMA_REQ_GPC 1
#define MX50_DMA_REQ_ATA_UART4_RX 2
#define MX50_DMA_REQ_ATA_UART4_TX 3
#define MX50_DMA_REQ_CSPI1_RX 6
#define MX50_DMA_REQ_CSPI1_TX 7
#define MX50_DMA_REQ_CSPI2_RX 8
#define MX50_DMA_REQ_CSPI2_TX 9
#define MX50_DMA_REQ_I2C3_SDHC3 10
#define MX50_DMA_REQ_SDHC4 11
#define MX50_DMA_REQ_UART2_FIRI_RX 12
#define MX50_DMA_REQ_UART2_FIRI_TX 13
#define MX50_DMA_REQ_EXT0 14
#define MX50_DMA_REQ_EXT1 15
#define MX50_DMA_REQ_UART5_RX 16
#define MX50_DMA_REQ_UART5_TX 17
#define MX50_DMA_REQ_UART1_RX 18
#define MX50_DMA_REQ_UART1_TX 19
#define MX50_DMA_REQ_I2C1_SDHC1 20
#define MX50_DMA_REQ_I2C2_SDHC2 21
#define MX50_DMA_REQ_SSI2_RX2 22
#define MX50_DMA_REQ_SSI2_TX2 23
#define MX50_DMA_REQ_SSI2_RX1 24
#define MX50_DMA_REQ_SSI2_TX1 25
#define MX50_DMA_REQ_SSI1_RX2 26
#define MX50_DMA_REQ_SSI1_TX2 27
#define MX50_DMA_REQ_SSI1_RX1 28
#define MX50_DMA_REQ_SSI1_TX1 29
#define MX50_DMA_REQ_CSPI_RX 38
#define MX50_DMA_REQ_CSPI_TX 39
#define MX50_DMA_REQ_UART3_RX 42
#define MX50_DMA_REQ_UART3_TX 43
/*
* Interrupt numbers
*/
#include <asm/irq.h>
#define MX50_INT_MMC_SDHC1 (NR_IRQS_LEGACY + 1)
#define MX50_INT_MMC_SDHC2 (NR_IRQS_LEGACY + 2)
#define MX50_INT_MMC_SDHC3 (NR_IRQS_LEGACY + 3)
#define MX50_INT_MMC_SDHC4 (NR_IRQS_LEGACY + 4)
#define MX50_INT_DAP (NR_IRQS_LEGACY + 5)
#define MX50_INT_SDMA (NR_IRQS_LEGACY + 6)
#define MX50_INT_IOMUX (NR_IRQS_LEGACY + 7)
#define MX50_INT_UART4 (NR_IRQS_LEGACY + 13)
#define MX50_INT_USB_H1 (NR_IRQS_LEGACY + 14)
#define MX50_INT_USB_OTG (NR_IRQS_LEGACY + 18)
#define MX50_INT_DATABAHN (NR_IRQS_LEGACY + 19)
#define MX50_INT_ELCDIF (NR_IRQS_LEGACY + 20)
#define MX50_INT_EPXP (NR_IRQS_LEGACY + 21)
#define MX50_INT_SRTC_NTZ (NR_IRQS_LEGACY + 24)
#define MX50_INT_SRTC_TZ (NR_IRQS_LEGACY + 25)
#define MX50_INT_EPDC (NR_IRQS_LEGACY + 27)
#define MX50_INT_NIC (NR_IRQS_LEGACY + 28)
#define MX50_INT_SSI1 (NR_IRQS_LEGACY + 29)
#define MX50_INT_SSI2 (NR_IRQS_LEGACY + 30)
#define MX50_INT_UART1 (NR_IRQS_LEGACY + 31)
#define MX50_INT_UART2 (NR_IRQS_LEGACY + 32)
#define MX50_INT_UART3 (NR_IRQS_LEGACY + 33)
#define MX50_INT_RESV34 (NR_IRQS_LEGACY + 34)
#define MX50_INT_RESV35 (NR_IRQS_LEGACY + 35)
#define MX50_INT_CSPI1 (NR_IRQS_LEGACY + 36)
#define MX50_INT_CSPI2 (NR_IRQS_LEGACY + 37)
#define MX50_INT_CSPI (NR_IRQS_LEGACY + 38)
#define MX50_INT_GPT (NR_IRQS_LEGACY + 39)
#define MX50_INT_EPIT1 (NR_IRQS_LEGACY + 40)
#define MX50_INT_GPIO1_INT7 (NR_IRQS_LEGACY + 42)
#define MX50_INT_GPIO1_INT6 (NR_IRQS_LEGACY + 43)
#define MX50_INT_GPIO1_INT5 (NR_IRQS_LEGACY + 44)
#define MX50_INT_GPIO1_INT4 (NR_IRQS_LEGACY + 45)
#define MX50_INT_GPIO1_INT3 (NR_IRQS_LEGACY + 46)
#define MX50_INT_GPIO1_INT2 (NR_IRQS_LEGACY + 47)
#define MX50_INT_GPIO1_INT1 (NR_IRQS_LEGACY + 48)
#define MX50_INT_GPIO1_INT0 (NR_IRQS_LEGACY + 49)
#define MX50_INT_GPIO1_LOW (NR_IRQS_LEGACY + 50)
#define MX50_INT_GPIO1_HIGH (NR_IRQS_LEGACY + 51)
#define MX50_INT_GPIO2_LOW (NR_IRQS_LEGACY + 52)
#define MX50_INT_GPIO2_HIGH (NR_IRQS_LEGACY + 53)
#define MX50_INT_GPIO3_LOW (NR_IRQS_LEGACY + 54)
#define MX50_INT_GPIO3_HIGH (NR_IRQS_LEGACY + 55)
#define MX50_INT_GPIO4_LOW (NR_IRQS_LEGACY + 56)
#define MX50_INT_GPIO4_HIGH (NR_IRQS_LEGACY + 57)
#define MX50_INT_WDOG1 (NR_IRQS_LEGACY + 58)
#define MX50_INT_KPP (NR_IRQS_LEGACY + 60)
#define MX50_INT_PWM1 (NR_IRQS_LEGACY + 61)
#define MX50_INT_I2C1 (NR_IRQS_LEGACY + 62)
#define MX50_INT_I2C2 (NR_IRQS_LEGACY + 63)
#define MX50_INT_I2C3 (NR_IRQS_LEGACY + 64)
#define MX50_INT_RESV65 (NR_IRQS_LEGACY + 65)
#define MX50_INT_DCDC (NR_IRQS_LEGACY + 66)
#define MX50_INT_THERMAL_ALARM (NR_IRQS_LEGACY + 67)
#define MX50_INT_ANA3 (NR_IRQS_LEGACY + 68)
#define MX50_INT_ANA4 (NR_IRQS_LEGACY + 69)
#define MX50_INT_CCM1 (NR_IRQS_LEGACY + 71)
#define MX50_INT_CCM2 (NR_IRQS_LEGACY + 72)
#define MX50_INT_GPC1 (NR_IRQS_LEGACY + 73)
#define MX50_INT_GPC2 (NR_IRQS_LEGACY + 74)
#define MX50_INT_SRC (NR_IRQS_LEGACY + 75)
#define MX50_INT_NM (NR_IRQS_LEGACY + 76)
#define MX50_INT_PMU (NR_IRQS_LEGACY + 77)
#define MX50_INT_CTI_IRQ (NR_IRQS_LEGACY + 78)
#define MX50_INT_CTI1_TG0 (NR_IRQS_LEGACY + 79)
#define MX50_INT_CTI1_TG1 (NR_IRQS_LEGACY + 80)
#define MX50_INT_GPU2_IRQ (NR_IRQS_LEGACY + 84)
#define MX50_INT_GPU2_BUSY (NR_IRQS_LEGACY + 85)
#define MX50_INT_UART5 (NR_IRQS_LEGACY + 86)
#define MX50_INT_FEC (NR_IRQS_LEGACY + 87)
#define MX50_INT_OWIRE (NR_IRQS_LEGACY + 88)
#define MX50_INT_CTI1_TG2 (NR_IRQS_LEGACY + 89)
#define MX50_INT_SJC (NR_IRQS_LEGACY + 90)
#define MX50_INT_DCP_CHAN1_3 (NR_IRQS_LEGACY + 91)
#define MX50_INT_DCP_CHAN0 (NR_IRQS_LEGACY + 92)
#define MX50_INT_PWM2 (NR_IRQS_LEGACY + 94)
#define MX50_INT_RNGB (NR_IRQS_LEGACY + 97)
#define MX50_INT_CTI1_TG3 (NR_IRQS_LEGACY + 98)
#define MX50_INT_RAWNAND_BCH (NR_IRQS_LEGACY + 100)
#define MX50_INT_RAWNAND_GPMI (NR_IRQS_LEGACY + 102)
#define MX50_INT_GPIO5_LOW (NR_IRQS_LEGACY + 103)
#define MX50_INT_GPIO5_HIGH (NR_IRQS_LEGACY + 104)
#define MX50_INT_GPIO6_LOW (NR_IRQS_LEGACY + 105)
#define MX50_INT_GPIO6_HIGH (NR_IRQS_LEGACY + 106)
#define MX50_INT_MSHC (NR_IRQS_LEGACY + 109)
#define MX50_INT_APBHDMA_CHAN0 (NR_IRQS_LEGACY + 110)
#define MX50_INT_APBHDMA_CHAN1 (NR_IRQS_LEGACY + 111)
#define MX50_INT_APBHDMA_CHAN2 (NR_IRQS_LEGACY + 112)
#define MX50_INT_APBHDMA_CHAN3 (NR_IRQS_LEGACY + 113)
#define MX50_INT_APBHDMA_CHAN4 (NR_IRQS_LEGACY + 114)
#define MX50_INT_APBHDMA_CHAN5 (NR_IRQS_LEGACY + 115)
#define MX50_INT_APBHDMA_CHAN6 (NR_IRQS_LEGACY + 116)
#define MX50_INT_APBHDMA_CHAN7 (NR_IRQS_LEGACY + 117)
#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
extern int mx50_revision(void);
#endif
#endif /* ifndef __MACH_MX50_H__ */
arch/arm/mach-imx/mxc.h
浏览文件 @ 1d7180e2
......@@ -32,7 +32,6 @@
#define MXC_CPU_MX27 27
#define MXC_CPU_MX31 31
#define MXC_CPU_MX35 35
#define MXC_CPU_MX50 50
#define MXC_CPU_MX51 51
#define MXC_CPU_MX53 53
......@@ -126,18 +125,6 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx35() (0)
#endif
#ifdef CONFIG_SOC_IMX50
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
# else
# define mxc_cpu_type MXC_CPU_MX50
# endif
# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
#else
# define cpu_is_mx50() (0)
#endif
#ifdef CONFIG_SOC_IMX51
# ifdef mxc_cpu_type
# undef mxc_cpu_type
......
arch/arm/mach-imx/pm-imx5.c
浏览文件 @ 1d7180e2
......@@ -34,7 +34,7 @@
/*
* set cpu low power mode before WFI instruction. This function is called
* mx5 because it can be used for mx50, mx51, and mx53.
* mx5 because it can be used for mx51, and mx53.
*/
static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
{
......@@ -85,10 +85,7 @@ static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
__raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC);
__raw_writel(ccm_clpcr, MXC_CCM_CLPCR);
__raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR);
/* Enable NEON SRPG for all but MX50TO1.0. */
if (mx50_revision() != IMX_CHIP_REVISION_1_0)
__raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
__raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR);
if (stop_mode) {
empgc0 |= MXC_SRPGCR_PCR;
......
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