usb: dwc3: core: define bit 10 of GCTL register

This bit is necessary for implemeting workaround
for known issue with some revisions of this core.
Signed-off-by: NFelipe Balbi <balbi@ti.com>

drivers/usb/dwc3/core.h

@@ -157,6 +157,7 @@
 #define DWC3_GCTL_PRTCAP_OTG	3
 
 #define DWC3_GCTL_CORESOFTRESET		(1 << 11)
+#define DWC3_GCTL_SOFITPSYNC		(1 << 10)
 #define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
 #define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
 #define DWC3_GCTL_DISSCRAMBLE		(1 << 3)