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raspberrypi-kernel
提交 14b596c9 编写于 作者: K Kristina Martšenko 提交者： Greg Kroah-Hartman
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staging: cxt1e1: remove driver 

Remove the driver as it hasn't been cleaned up and it doesn't look like
anyone is going to work on it anymore. This can be reverted if someone
wants to work to fix the remaining issues the driver has.
Signed-off-by: NKristina Martšenko <kristina.martsenko@gmail.com>
Cc: Bob Beers <bob.beers@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
上级 19b1e769
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drivers/staging/Kconfig
浏览文件 @ 14b596c9
......@@ -72,8 +72,6 @@ source "drivers/staging/sep/Kconfig"
source "drivers/staging/iio/Kconfig"
source "drivers/staging/cxt1e1/Kconfig"
source "drivers/staging/xgifb/Kconfig"
source "drivers/staging/tidspbridge/Kconfig"
......
drivers/staging/Makefile
浏览文件 @ 14b596c9
......@@ -30,7 +30,6 @@ obj-$(CONFIG_VT6656) += vt6656/
obj-$(CONFIG_VME_BUS) += vme/
obj-$(CONFIG_DX_SEP) += sep/
obj-$(CONFIG_IIO) += iio/
obj-$(CONFIG_CXT1E1) += cxt1e1/
obj-$(CONFIG_FB_XGI) += xgifb/
obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/
obj-$(CONFIG_ACPI_QUICKSTART) += quickstart/
......
drivers/staging/cxt1e1/Kconfig 已删除 100644 → 0
浏览文件 @ 19b1e769
config CXT1E1
tristate "SBE wanPMC-C[421]E1T1 hardware support"
depends on HDLC && PCI
---help---
This driver supports the SBE wanPMC-CxT1E1 1, 2 and 4 port T3
channelized stream WAN adapter card which contains a HDLC/Transparent
mode controller.
If you want to compile this driver as a module say M here.
The module will be called 'cxt1e1'.
If unsure, say N.
config SBE_PMCC4_NCOMM
bool "SBE PMCC4 NCOMM support"
depends on CXT1E1
---help---
SBE supplies optional support for NCOMM products.
If you have purchased this optional support you must say Y
here to allow the driver to operate with the NCOMM product.
drivers/staging/cxt1e1/Makefile 已删除 100644 → 0
浏览文件 @ 19b1e769
obj-$(CONFIG_CXT1E1) += cxt1e1.o
ccflags-y := -DSBE_PMCC4_ENABLE
ccflags-y += -DSBE_ISR_TASKLET
cxt1e1-y := \
musycc.o \
pmcc4_drv.o \
comet.o \
linux.o \
functions.o \
hwprobe.o \
pmc93x6_eeprom.o \
sbecrc.o \
comet_tables.o \
sbeid.o
cxt1e1-$(CONFIG_PROC_FS) += sbeproc.o
drivers/staging/cxt1e1/comet.c 已删除 100644 → 0
浏览文件 @ 19b1e769
/* Copyright (C) 2003-2005 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/io.h>
#include <linux/hdlc.h>
#include "pmcc4_sysdep.h"
#include "sbecom_inline_linux.h"
#include "libsbew.h"
#include "pmcc4.h"
#include "comet.h"
#include "comet_tables.h"
#define COMET_NUM_SAMPLES 24 /* Number of entries in the waveform table */
#define COMET_NUM_UNITS 5 /* Number of points per entry in table */
/* forward references */
static void SetPwrLevel(struct s_comet_reg *comet);
static void WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet,
u_int32_t *table);
static void WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
u_int8_t table[COMET_NUM_SAMPLES]
[COMET_NUM_UNITS]);
static void *TWV_table[12] = {
TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
TWVShortHaul4, TWVShortHaul5,
/** PORT POINT - 75 Ohm not supported **/
TWV_E1_75Ohm,
TWV_E1_120Ohm
};
static int
lbo_tbl_lkup(int t1, int lbo) {
/* error switches to default */
if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
if (t1)
/* default T1 waveform table */
lbo = CFG_LBO_LH0;
else
/* default E1 waveform table */
lbo = CFG_LBO_E120;
}
/* make index ZERO relative */
return lbo - 1;
}
void init_comet(void *ci, struct s_comet_reg *comet, u_int32_t port_mode,
int clockmaster, u_int8_t moreParams)
{
u_int8_t isT1mode;
/* T1 default */
u_int8_t tix = CFG_LBO_LH0;
isT1mode = IS_FRAME_ANY_T1(port_mode);
/* T1 or E1 */
if (isT1mode) {
/* Select T1 Mode & PIO output enabled */
pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
/* default T1 waveform table */
tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
} else {
/* Select E1 Mode & PIO output enabled */
pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
/* default E1 waveform table */
tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
}
if (moreParams & CFG_LBO_MASK)
/* dial-in requested waveform table */
tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
/* Tx line Intfc cfg Set for analog & no special patterns */
/* Transmit Line Interface Config. */
pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
/* master test Ignore Test settings for now */
/* making sure it's Default value */
pci_write_32((u_int32_t *) &comet->mtest, 0x00);
/* Turn on Center (CENT) and everything else off */
/* RJAT cfg */
pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
/* Set Jitter Attenuation to recommend T1 values */
if (isT1mode) {
/* RJAT Divider N1 Control */
pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
/* RJAT Divider N2 Control */
pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
} else {
/* RJAT Divider N1 Control */
pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
/* RJAT Divider N2 Control */
pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
}
/* Turn on Center (CENT) and everything else off */
/* TJAT Config. */
pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
/* Do not bypass jitter attenuation and bypass elastic store */
/* rx opts */
pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
/* TJAT ctrl & TJAT divider ctrl */
/* Set Jitter Attenuation to recommended T1 values */
if (isT1mode) {
/* TJAT Divider N1 Control */
pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
/* TJAT Divider N2 Control */
pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
} else {
/* TJAT Divider N1 Control */
pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
/* TJAT Divider N2 Control */
pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
}
/* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */
/* Select 193-bit frame format */
if (isT1mode) {
pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
} else {
/* Select 256-bit frame format */
pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
/* disable T1 data link receive */
pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
/* disable T1 data link transmit */
pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
}
/* the following is a default value */
/* Enable 8 out of 10 validation */
/* t1RBOC enable(BOC:BitOriented Code) */
pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
if (isT1mode) {
/* IBCD cfg: aka Inband Code Detection ** loopback code length
* set to
*/
/* 6 bit down, 5 bit up (assert) */
pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
/* line loopback activate pattern */
pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
/* deactivate code pattern (i.e.001) */
pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
}
/* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */
/* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */
/* 60: t1 ALMI cfg */
/* Configure Line Coding */
switch (port_mode) {
/* 1 - T1 B8ZS */
case CFG_FRAME_SF:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
/* 5:B8ZS */
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
break;
/* 2 - T1 B8ZS */
case CFG_FRAME_ESF:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
/* Bit 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
/* 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
/* 4:ESF 5:ESFFA */
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
/* 2:ESF */
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
/* 4:ESF 5:B8ZS */
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
/* 4:ESF */
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
break;
/* 3 - HDB3 */
case CFG_FRAME_E1PLAIN:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
break;
/* 4 - HDB3 */
case CFG_FRAME_E1CAS:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
break;
/* 5 - HDB3 */
case CFG_FRAME_E1CRC:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
break;
/* 6 - HDB3 */
case CFG_FRAME_E1CRC_CAS:
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
break;
/* 7 - T1 AMI */
case CFG_FRAME_SF_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
break;
/* 8 - T1 AMI */
case CFG_FRAME_ESF_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
/* 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
/* 5: T1 DataLink Enable */
pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
/* Bit 4:ESF 5:ESFFA */
pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
/* 2:ESF */
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
/* 4:ESF */
pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
/* 4:ESF */
pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
break;
/* 9 - AMI */
case CFG_FRAME_E1PLAIN_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
break;
/* 10 - AMI */
case CFG_FRAME_E1CAS_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
break;
/* 11 - AMI */
case CFG_FRAME_E1CRC_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
break;
/* 12 - AMI */
case CFG_FRAME_E1CRC_CAS_AMI:
/* Enable AMI Line Decoding */
pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
break;
} /* end switch */
/***
* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
* CMODE=1: Clock slave mode with BRCLK as an input,
* DE=0: Use falling edge of BRCLK for data,
* FE=0: Use falling edge of BRCLK for frame,
* CMS=0: Use backplane freq,
* RATE[1:0]=0,0: T1
***/
/* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
/* note "rate bits can only be set once after reset" */
if (clockmaster) {
/* CMODE == clockMode, 0=clock master
* (so all 3 others should be slave)
*/
/* rate = 1.544 Mb/s */
if (isT1mode)
/* Comet 0 Master Mode(CMODE=0) */
pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
/* rate = 2.048 Mb/s */
else
/* Comet 0 Master Mode(CMODE=0) */
pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
/* 31: BRIF frame pulse cfg 06: tx timing options */
/* Master Mode i.e.FPMODE=0 (@0x20) */
pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
if (cxt1e1_log_level >= LOG_SBEBUG12)
pr_info(">> %s: clockmaster internal clock\n",
__func__);
/* internal oscillator */
pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
} else {
/* external clock source */
if (cxt1e1_log_level >= LOG_SBEBUG12)
pr_info(">> %s: clockmaster external clock\n",
__func__);
/* loop timing(external) */
pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
}
} else {
/* slave */
if (isT1mode)
/* Slave Mode(CMODE=1, see above) */
pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
else
/* Slave Mode(CMODE=1)*/
pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
/* Slave Mode i.e. FPMODE=1 (@0x20) */
pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
if (cxt1e1_log_level >= LOG_SBEBUG12)
pr_info(">> %s: clockslave internal clock\n", __func__);
/* oscillator timing */
pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
}
/* 32: BRIF parity F-bit cfg */
/* Totem-pole operation */
/* Receive Backplane Parity/F-bit */
pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
/* dc: RLPS equalizer V ref */
/* Configuration */
if (isT1mode)
/* RLPS Equalizer Voltage */
pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
else
/* RLPS Equalizer Voltage */
pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
/* Reserved bit set and SQUELCH enabled */
/* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */
/* RLPS Configuration Status */
pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
if (isT1mode)
/* ? */
pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
else
/* ? */
pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
/* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
/* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
/* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
/* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
/*** Transmit side is always an Input, Slave Clock*/
/* 40: BTIF cfg 41: loop timing(external) */
/*BTIF frame pulse cfg */
if (isT1mode)
/* BTIF Configuration Reg. */
pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
else
/* BTIF Configuration Reg. */
pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
/* BTIF Frame Pulse Config. */
pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
/* 0a: master diag 06: tx timing options */
/* if set Comet to loop back */
/* Comets set to normal */
pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
/* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted */
/* Store is enabled. */
WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
if (isT1mode)
WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
else
WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
SetPwrLevel(comet);
}
/*
** Name: WrtXmtWaveform
** Description: Formulate the Data for the Pulse Waveform Storage
** Write register, (F2), from the sample and unit inputs.
** Write the data to the Pulse Waveform Storage Data register.
** Returns: Nothing
*/
static void
WrtXmtWaveform(ci_t *ci, struct s_comet_reg *comet, u_int32_t sample,
u_int32_t unit, u_int8_t data)
{
u_int8_t WaveformAddr;
WaveformAddr = (sample << 3) + (unit & 7);
pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
/* for write order preservation when Optimizing driver */
pci_flush_write(ci);
pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
}
/*
** Name: WrtXmtWaveformTbl
** Description: Fill in the Transmit Waveform Values
** for driving the transmitter DAC.
** Returns: Nothing
*/
static void
WrtXmtWaveformTbl(ci_t *ci, struct s_comet_reg *comet,
u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
{
u_int32_t sample, unit;
for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
for (unit = 0; unit < COMET_NUM_UNITS; unit++)
WrtXmtWaveform(ci, comet, sample, unit,
table[sample][unit]);
}
/* Enable transmitter and set output amplitude */
pci_write_32((u_int32_t *) &comet->xlpg_cfg,
table[COMET_NUM_SAMPLES][0]);
}
/*
** Name: WrtXmtWaveform
** Description: Fill in the Receive Equalizer RAM from the desired
** table.
** Returns: Nothing
**
** Remarks: Per PM4351 Device Errata, Receive Equalizer RAM Initialization
** is coded with early setup of indirect address.
*/
static void
WrtRcvEqualizerTbl(ci_t *ci, struct s_comet_reg *comet, u_int32_t *table)
{
u_int32_t ramaddr;
u_int32_t value;
for (ramaddr = 0; ramaddr < 256; ramaddr++) {
/*** the following lines are per Errata 7, 2.5 ***/
{
/* Set up for a read operation */
pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
/* for write order preservation when Optimizing driver */
pci_flush_write(ci);
/* write the addr, initiate a read */
pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
(u_int8_t) ramaddr);
/* for write order preservation when Optimizing driver */
pci_flush_write(ci);
/*
* wait 3 line rate clock cycles to ensure address bits are
* captured by T1/E1 clock
*/
/* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
OS_uwait(4, "wret");
}
value = *table++;
pci_write_32((u_int32_t *) &comet->rlps_idata3,
(u_int8_t) (value >> 24));
pci_write_32((u_int32_t *) &comet->rlps_idata2,
(u_int8_t) (value >> 16));
pci_write_32((u_int32_t *) &comet->rlps_idata1,
(u_int8_t) (value >> 8));
pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
/* for write order preservation when Optimizing driver */
pci_flush_write(ci);
/* Storing RAM address, causes RAM to be updated */
/* Set up for a write operation */
pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
/* for write order preservation when optimizing driver */
pci_flush_write(ci);
/* write the addr, initiate a read */
pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
(u_int8_t) ramaddr);
/* for write order preservation when optimizing driver */
pci_flush_write(ci);
/*
* wait 3 line rate clock cycles to ensure address bits are captured
* by T1/E1 clock
*/
/* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
OS_uwait(4, "wret");
}
/* Enable Equalizer & set it to use 256 periods */
pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
}
/*
** Name: SetPwrLevel
** Description: Implement power level setting algorithm described below
** Returns: Nothing
*/
static void
SetPwrLevel(struct s_comet_reg *comet)
{
u_int32_t temp;
/*
** Algorithm to Balance the Power Distribution of Ttip Tring
**
** Zero register F6
** Write 0x01 to register F4
** Write another 0x01 to register F4
** Read register F4
** Remove the 0x01 bit by Anding register F4 with 0xFE
** Write the resultant value to register F4
** Repeat these steps for register F5
** Write 0x01 to register F6
*/
/* XLPG Fuse Data Select */
pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
/* XLPG Analog Test Positive control */
pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
/* XLPG Analog Test Negative control */
temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
/* XLPG */
pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
}
/*
** Name: SetCometOps
** Description: Set up the selected Comet's clock edge drive for both
** the transmit out the analog side and receive to the
** backplane side.
** Returns: Nothing
*/
#if 0
static void
SetCometOps(struct s_comet_reg *comet)
{
u_int8_t rd_value;
if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) {
/* read the BRIF Configuration */
rd_value = (u_int8_t) pci_read_32((u_int32_t *)
&comet->brif_cfg);
rd_value &= ~0x20;
pci_write_32((u_int32_t *) &comet->brif_cfg,
(u_int32_t) rd_value);
/* read the BRIF Frame Pulse Configuration */
rd_value = (u_int8_t) pci_read_32((u_int32_t *)
&comet->brif_fpcfg);
rd_value &= ~0x20;
pci_write_32((u_int32_t *) &comet->brif_fpcfg,
(u_int8_t) rd_value);
} else {
/* read the BRIF Configuration */
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
rd_value |= 0x20;
pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
/* read the BRIF Frame Pulse Configuration */
rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
rd_value |= 0x20;
pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
}
}
#endif
/*** End-of-File ***/
drivers/staging/cxt1e1/comet.h 已删除 100644 → 0
浏览文件 @ 19b1e769
#ifndef _INC_COMET_H_
#define _INC_COMET_H_
/*-----------------------------------------------------------------------------
* comet.h -
*
* Copyright (C) 2005 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* For further information, contact via email: support@sbei.com
* SBE, Inc. San Ramon, California U.S.A.
*-----------------------------------------------------------------------------
*/
#include <linux/types.h>
#define VINT32 volatile u_int32_t
struct s_comet_reg {
VINT32 gbl_cfg; /* 00 Global Cfg */
VINT32 clkmon; /* 01 Clk Monitor */
VINT32 rx_opt; /* 02 RX Options */
VINT32 rx_line_cfg; /* 03 RX Line Interface Cfg */
VINT32 tx_line_cfg; /* 04 TX Line Interface Cfg */
VINT32 tx_frpass; /* 05 TX Framing & Bypass Options */
VINT32 tx_time; /* 06 TX Timing Options */
VINT32 intr_1; /* 07 Intr Source #1 */
VINT32 intr_2; /* 08 Intr Source #2 */
VINT32 intr_3; /* 09 Intr Source #3 */
VINT32 mdiag; /* 0A Master Diagnostics */
VINT32 mtest; /* 0B Master Test */
VINT32 adiag; /* 0C Analog Diagnostics */
VINT32 rev_id; /* 0D Rev/Chip Id/Global PMON Update */
#define pmon rev_id
VINT32 reset; /* 0E Reset */
VINT32 prgd_phctl; /* 0F PRGD Positioning/Ctl & HDLC Ctl */
VINT32 cdrc_cfg; /* 10 CDRC Cfg */
VINT32 cdrc_ien; /* 11 CDRC Intr Enable */
VINT32 cdrc_ists; /* 12 CDRC Intr Sts */
VINT32 cdrc_alos; /* 13 CDRC Alternate Loss of Signal */
VINT32 rjat_ists; /* 14 RJAT Intr Sts */
VINT32 rjat_n1clk; /* 15 RJAT Reference Clk Divisor (N1) Ctl */
VINT32 rjat_n2clk; /* 16 RJAT Output Clk Divisor (N2) Ctl */
VINT32 rjat_cfg; /* 17 RJAT Cfg */
VINT32 tjat_ists; /* 18 TJAT Intr Sts */
VINT32 tjat_n1clk; /* 19 TJAT Reference Clk Divisor (N1) Ctl */
VINT32 tjat_n2clk; /* 1A TJAT Output Clk Divisor (N2) Ctl */
VINT32 tjat_cfg; /* 1B TJAT Cfg */
VINT32 rx_elst_cfg; /* 1C RX-ELST Cfg */
VINT32 rx_elst_ists; /* 1D RX-ELST Intr Sts */
VINT32 rx_elst_idle; /* 1E RX-ELST Idle Code */
VINT32 _rx_elst_res1f; /* 1F RX-ELST Reserved */
VINT32 tx_elst_cfg; /* 20 TX-ELST Cfg */
VINT32 tx_elst_ists; /* 21 TX-ELST Intr Sts */
VINT32 _tx_elst_res22; /* 22 TX-ELST Reserved */
VINT32 _tx_elst_res23; /* 23 TX-ELST Reserved */
VINT32 __res24; /* 24 Reserved */
VINT32 __res25; /* 25 Reserved */
VINT32 __res26; /* 26 Reserved */
VINT32 __res27; /* 27 Reserved */
VINT32 rxce1_ctl; /* 28 RXCE RX Data Link 1 Ctl */
VINT32 rxce1_bits; /* 29 RXCE RX Data Link 1 Bit Select */
VINT32 rxce2_ctl; /* 2A RXCE RX Data Link 2 Ctl */
VINT32 rxce2_bits; /* 2B RXCE RX Data Link 2 Bit Select */
VINT32 rxce3_ctl; /* 2C RXCE RX Data Link 3 Ctl */
VINT32 rxce3_bits; /* 2D RXCE RX Data Link 3 Bit Select */
VINT32 _rxce_res2E; /* 2E RXCE Reserved */
VINT32 _rxce_res2F; /* 2F RXCE Reserved */
VINT32 brif_cfg; /* 30 BRIF RX Backplane Cfg */
VINT32 brif_fpcfg; /* 31 BRIF RX Backplane Frame Pulse Cfg */
VINT32 brif_pfcfg; /* 32 BRIF RX Backplane Parity/F-Bit Cfg */
VINT32 brif_tsoff; /* 33 BRIF RX Backplane Time Slot Offset */
VINT32 brif_boff; /* 34 BRIF RX Backplane Bit Offset */
VINT32 _brif_res35; /* 35 BRIF RX Backplane Reserved */
VINT32 _brif_res36; /* 36 BRIF RX Backplane Reserved */
VINT32 _brif_res37; /* 37 BRIF RX Backplane Reserved */
VINT32 txci1_ctl; /* 38 TXCI TX Data Link 1 Ctl */
VINT32 txci1_bits; /* 39 TXCI TX Data Link 2 Bit Select */
VINT32 txci2_ctl; /* 3A TXCI TX Data Link 1 Ctl */
VINT32 txci2_bits; /* 3B TXCI TX Data Link 2 Bit Select */
VINT32 txci3_ctl; /* 3C TXCI TX Data Link 1 Ctl */
VINT32 txci3_bits; /* 3D TXCI TX Data Link 2 Bit Select */
VINT32 _txci_res3E; /* 3E TXCI Reserved */
VINT32 _txci_res3F; /* 3F TXCI Reserved */
VINT32 btif_cfg; /* 40 BTIF TX Backplane Cfg */
VINT32 btif_fpcfg; /* 41 BTIF TX Backplane Frame Pulse Cfg */
VINT32 btif_pcfgsts; /* 42 BTIF TX Backplane Parity Cfg & Sts */
VINT32 btif_tsoff; /* 43 BTIF TX Backplane Time Slot Offset */
VINT32 btif_boff; /* 44 BTIF TX Backplane Bit Offset */
VINT32 _btif_res45; /* 45 BTIF TX Backplane Reserved */
VINT32 _btif_res46; /* 46 BTIF TX Backplane Reserved */
VINT32 _btif_res47; /* 47 BTIF TX Backplane Reserved */
VINT32 t1_frmr_cfg; /* 48 T1 FRMR Cfg */
VINT32 t1_frmr_ien; /* 49 T1 FRMR Intr Enable */
VINT32 t1_frmr_ists; /* 4A T1 FRMR Intr Sts */
VINT32 __res_4B; /* 4B Reserved */
VINT32 ibcd_cfg; /* 4C IBCD Cfg */
VINT32 ibcd_ies; /* 4D IBCD Intr Enable/Sts */
VINT32 ibcd_act; /* 4E IBCD Activate Code */
VINT32 ibcd_deact; /* 4F IBCD Deactivate Code */
VINT32 sigx_cfg; /* 50 SIGX Cfg/Change of Signaling State */
VINT32 sigx_acc_cos; /* 51 SIGX
* uP Access Sts/Change of Signaling State */
VINT32 sigx_iac_cos; /* 52 SIGX Channel Indirect
* Addr/Ctl/Change of Signaling State */
VINT32 sigx_idb_cos; /* 53 SIGX Channel Indirect Data
* Buffer/Change of Signaling State */
VINT32 t1_xbas_cfg; /* 54 T1 XBAS Cfg */
VINT32 t1_xbas_altx; /* 55 T1 XBAS Alarm TX */
VINT32 t1_xibc_ctl; /* 56 T1 XIBC Ctl */
VINT32 t1_xibc_lbcode; /* 57 T1 XIBC Loopback Code */
VINT32 pmon_ies; /* 58 PMON Intr Enable/Sts */
VINT32 pmon_fberr; /* 59 PMON Framing Bit Err Cnt */
VINT32 pmon_feb_lsb; /* 5A PMON
* OFF/COFA/Far End Block Err Cnt (LSB) */
VINT32 pmon_feb_msb; /* 5B PMON
* OFF/COFA/Far End Block Err Cnt (MSB) */
VINT32 pmon_bed_lsb; /* 5C PMON Bit/Err/CRCE Cnt (LSB) */
VINT32 pmon_bed_msb; /* 5D PMON Bit/Err/CRCE Cnt (MSB) */
VINT32 pmon_lvc_lsb; /* 5E PMON LVC Cnt (LSB) */
VINT32 pmon_lvc_msb; /* 5F PMON LVC Cnt (MSB) */
VINT32 t1_almi_cfg; /* 60 T1 ALMI Cfg */
VINT32 t1_almi_ien; /* 61 T1 ALMI Intr Enable */
VINT32 t1_almi_ists; /* 62 T1 ALMI Intr Sts */
VINT32 t1_almi_detsts; /* 63 T1 ALMI Alarm Detection Sts */
VINT32 _t1_pdvd_res64; /* 64 T1 PDVD Reserved */
VINT32 t1_pdvd_ies; /* 65 T1 PDVD Intr Enable/Sts */
VINT32 _t1_xboc_res66; /* 66 T1 XBOC Reserved */
VINT32 t1_xboc_code; /* 67 T1 XBOC Code */
VINT32 _t1_xpde_res68; /* 68 T1 XPDE Reserved */
VINT32 t1_xpde_ies; /* 69 T1 XPDE Intr Enable/Sts */
VINT32 t1_rboc_ena; /* 6A T1 RBOC Enable */
VINT32 t1_rboc_sts; /* 6B T1 RBOC Code Sts */
VINT32 t1_tpsc_cfg; /* 6C TPSC Cfg */
VINT32 t1_tpsc_sts; /* 6D TPSC uP Access Sts */
VINT32 t1_tpsc_ciaddr; /* 6E TPSC Channel Indirect
* Addr/Ctl */
VINT32 t1_tpsc_cidata; /* 6F TPSC Channel Indirect Data
* Buffer */
VINT32 t1_rpsc_cfg; /* 70 RPSC Cfg */
VINT32 t1_rpsc_sts; /* 71 RPSC uP Access Sts */
VINT32 t1_rpsc_ciaddr; /* 72 RPSC Channel Indirect
* Addr/Ctl */
VINT32 t1_rpsc_cidata; /* 73 RPSC Channel Indirect Data
* Buffer */
VINT32 __res74; /* 74 Reserved */
VINT32 __res75; /* 75 Reserved */
VINT32 __res76; /* 76 Reserved */
VINT32 __res77; /* 77 Reserved */
VINT32 t1_aprm_cfg; /* 78 T1 APRM Cfg/Ctl */
VINT32 t1_aprm_load; /* 79 T1 APRM Manual Load */
VINT32 t1_aprm_ists; /* 7A T1 APRM Intr Sts */
VINT32 t1_aprm_1sec_2; /* 7B T1 APRM One Second Content Octet 2 */
VINT32 t1_aprm_1sec_3; /* 7C T1 APRM One Second Content Octet 3 */
VINT32 t1_aprm_1sec_4; /* 7D T1 APRM One Second Content Octet 4 */
VINT32 t1_aprm_1sec_5; /* 7E T1 APRM
* One Second Content MSB (Octect 5) */
VINT32 t1_aprm_1sec_6; /* 7F T1 APRM
* One Second Content MSB (Octect 6) */
VINT32 e1_tran_cfg; /* 80 E1 TRAN Cfg */
VINT32 e1_tran_txalarm; /* 81 E1 TRAN TX Alarm/Diagnostic Ctl */
VINT32 e1_tran_intctl; /* 82 E1 TRAN International Ctl */
VINT32 e1_tran_extrab; /* 83 E1 TRAN Extra Bits Ctl */
VINT32 e1_tran_ien; /* 84 E1 TRAN Intr Enable */
VINT32 e1_tran_ists; /* 85 E1 TRAN Intr Sts */
VINT32 e1_tran_nats; /* 86 E1 TRAN National Bit Codeword
* Select */
VINT32 e1_tran_nat; /* 87 E1 TRAN National Bit Codeword */
VINT32 __res88; /* 88 Reserved */
VINT32 __res89; /* 89 Reserved */
VINT32 __res8A; /* 8A Reserved */
VINT32 __res8B; /* 8B Reserved */
VINT32 _t1_frmr_res8C; /* 8C T1 FRMR Reserved */
VINT32 _t1_frmr_res8D; /* 8D T1 FRMR Reserved */
VINT32 __res8E; /* 8E Reserved */
VINT32 __res8F; /* 8F Reserved */
VINT32 e1_frmr_aopts; /* 90 E1 FRMR Frame Alignment Options */
VINT32 e1_frmr_mopts; /* 91 E1 FRMR Maintenance Mode Options */
VINT32 e1_frmr_ien; /* 92 E1 FRMR Framing Sts Intr Enable */
VINT32 e1_frmr_mien; /* 93 E1 FRMR
* Maintenance/Alarm Sts Intr Enable */
VINT32 e1_frmr_ists; /* 94 E1 FRMR Framing Sts Intr Indication */
VINT32 e1_frmr_mists; /* 95 E1 FRMR
* Maintenance/Alarm Sts Indication Enable */
VINT32 e1_frmr_sts; /* 96 E1 FRMR Framing Sts */
VINT32 e1_frmr_masts; /* 97 E1 FRMR Maintenance/Alarm Sts */
VINT32 e1_frmr_nat_bits; /* 98 E1 FRMR International/National Bits */
VINT32 e1_frmr_crc_lsb; /* 99 E1 FRMR CRC Err Cnt - LSB */
VINT32 e1_frmr_crc_msb; /* 9A E1 FRMR CRC Err Cnt - MSB */
VINT32 e1_frmr_nat_ien; /* 9B E1 FRMR
* National Bit Codeword Intr Enables */
VINT32 e1_frmr_nat_ists; /* 9C E1 FRMR
* National Bit Codeword Intr/Sts */
VINT32 e1_frmr_nat; /* 9D E1 FRMR National Bit Codewords */
VINT32 e1_frmr_fp_ien; /* 9E E1 FRMR
* Frame Pulse/Alarm Intr Enables */
VINT32 e1_frmr_fp_ists; /* 9F E1 FRMR Frame Pulse/Alarm Intr/Sts */
VINT32 __resA0; /* A0 Reserved */
VINT32 __resA1; /* A1 Reserved */
VINT32 __resA2; /* A2 Reserved */
VINT32 __resA3; /* A3 Reserved */
VINT32 __resA4; /* A4 Reserved */
VINT32 __resA5; /* A5 Reserved */
VINT32 __resA6; /* A6 Reserved */
VINT32 __resA7; /* A7 Reserved */
VINT32 tdpr1_cfg; /* A8 TDPR #1 Cfg */
VINT32 tdpr1_utl; /* A9 TDPR #1 Upper TX Threshold */
VINT32 tdpr1_ltl; /* AA TDPR #1 Lower TX Threshold */
VINT32 tdpr1_ien; /* AB TDPR #1 Intr Enable */
VINT32 tdpr1_ists; /* AC TDPR #1 Intr Sts/UDR Clear */
VINT32 tdpr1_data; /* AD TDPR #1 TX Data */
VINT32 __resAE; /* AE Reserved */
VINT32 __resAF; /* AF Reserved */
VINT32 tdpr2_cfg; /* B0 TDPR #2 Cfg */
VINT32 tdpr2_utl; /* B1 TDPR #2 Upper TX Threshold */
VINT32 tdpr2_ltl; /* B2 TDPR #2 Lower TX Threshold */
VINT32 tdpr2_ien; /* B3 TDPR #2 Intr Enable */
VINT32 tdpr2_ists; /* B4 TDPR #2 Intr Sts/UDR Clear */
VINT32 tdpr2_data; /* B5 TDPR #2 TX Data */
VINT32 __resB6; /* B6 Reserved */
VINT32 __resB7; /* B7 Reserved1 */
VINT32 tdpr3_cfg; /* B8 TDPR #3 Cfg */
VINT32 tdpr3_utl; /* B9 TDPR #3 Upper TX Threshold */
VINT32 tdpr3_ltl; /* BA TDPR #3 Lower TX Threshold */
VINT32 tdpr3_ien; /* BB TDPR #3 Intr Enable */
VINT32 tdpr3_ists; /* BC TDPR #3 Intr Sts/UDR Clear */
VINT32 tdpr3_data; /* BD TDPR #3 TX Data */
VINT32 __resBE; /* BE Reserved */
VINT32 __resBF; /* BF Reserved */
VINT32 rdlc1_cfg; /* C0 RDLC #1 Cfg */
VINT32 rdlc1_intctl; /* C1 RDLC #1 Intr Ctl */
VINT32 rdlc1_sts; /* C2 RDLC #1 Sts */
VINT32 rdlc1_data; /* C3 RDLC #1 Data */
VINT32 rdlc1_paddr; /* C4 RDLC #1 Primary Addr Match */
VINT32 rdlc1_saddr; /* C5 RDLC #1 Secondary Addr Match */
VINT32 __resC6; /* C6 Reserved */
VINT32 __resC7; /* C7 Reserved */
VINT32 rdlc2_cfg; /* C8 RDLC #2 Cfg */
VINT32 rdlc2_intctl; /* C9 RDLC #2 Intr Ctl */
VINT32 rdlc2_sts; /* CA RDLC #2 Sts */
VINT32 rdlc2_data; /* CB RDLC #2 Data */
VINT32 rdlc2_paddr; /* CC RDLC #2 Primary Addr Match */
VINT32 rdlc2_saddr; /* CD RDLC #2 Secondary Addr Match */
VINT32 __resCE; /* CE Reserved */
VINT32 __resCF; /* CF Reserved */
VINT32 rdlc3_cfg; /* D0 RDLC #3 Cfg */
VINT32 rdlc3_intctl; /* D1 RDLC #3 Intr Ctl */
VINT32 rdlc3_sts; /* D2 RDLC #3 Sts */
VINT32 rdlc3_data; /* D3 RDLC #3 Data */
VINT32 rdlc3_paddr; /* D4 RDLC #3 Primary Addr Match */
VINT32 rdlc3_saddr; /* D5 RDLC #3 Secondary Addr Match */
VINT32 csu_cfg; /* D6 CSU Cfg */
VINT32 _csu_resD7; /* D7 CSU Reserved */
VINT32 rlps_idata3; /* D8 RLPS Indirect Data, 24-31 */
VINT32 rlps_idata2; /* D9 RLPS Indirect Data, 16-23 */
VINT32 rlps_idata1; /* DA RLPS Indirect Data, 8-15 */
VINT32 rlps_idata0; /* DB RLPS Indirect Data, 0-7 */
VINT32 rlps_eqvr; /* DC RLPS Equalizer Voltage Reference
* (E1 missing) */
VINT32 _rlps_resDD; /* DD RLPS Reserved */
VINT32 _rlps_resDE; /* DE RLPS Reserved */
VINT32 _rlps_resDF; /* DF RLPS Reserved */
VINT32 prgd_ctl; /* E0 PRGD Ctl */
VINT32 prgd_ies; /* E1 PRGD Intr Enable/Sts */
VINT32 prgd_shift_len; /* E2 PRGD Shift Length */
VINT32 prgd_tap; /* E3 PRGD Tap */
VINT32 prgd_errin; /* E4 PRGD Err Insertion */
VINT32 _prgd_resE5; /* E5 PRGD Reserved */
VINT32 _prgd_resE6; /* E6 PRGD Reserved */
VINT32 _prgd_resE7; /* E7 PRGD Reserved */
VINT32 prgd_patin1; /* E8 PRGD Pattern Insertion #1 */
VINT32 prgd_patin2; /* E9 PRGD Pattern Insertion #2 */
VINT32 prgd_patin3; /* EA PRGD Pattern Insertion #3 */
VINT32 prgd_patin4; /* EB PRGD Pattern Insertion #4 */
VINT32 prgd_patdet1; /* EC PRGD Pattern Detector #1 */
VINT32 prgd_patdet2; /* ED PRGD Pattern Detector #2 */
VINT32 prgd_patdet3; /* EE PRGD Pattern Detector #3 */
VINT32 prgd_patdet4; /* EF PRGD Pattern Detector #4 */
VINT32 xlpg_cfg; /* F0 XLPG Line Driver Cfg */
VINT32 xlpg_ctlsts; /* F1 XLPG Ctl/Sts */
VINT32 xlpg_pwave_addr; /* F2 XLPG
* Pulse Waveform Storage Write Addr */
VINT32 xlpg_pwave_data; /* F3 XLPG Pulse Waveform Storage Data */
VINT32 xlpg_atest_pctl; /* F4 XLPG Analog Test Positive Ctl */
VINT32 xlpg_atest_nctl; /* F5 XLPG Analog Test Negative Ctl */
VINT32 xlpg_fdata_sel; /* F6 XLPG Fuse Data Select */
VINT32 _xlpg_resF7; /* F7 XLPG Reserved */
VINT32 rlps_cfgsts; /* F8 RLPS Cfg & Sts */
VINT32 rlps_alos_thresh; /* F9 RLPS
* ALOS Detection/Clearance Threshold */
VINT32 rlps_alos_dper; /* FA RLPS ALOS Detection Period */
VINT32 rlps_alos_cper; /* FB RLPS ALOS Clearance Period */
VINT32 rlps_eq_iaddr; /* FC RLPS Equalization Indirect Addr */
VINT32 rlps_eq_rwsel; /* FD RLPS Equalization Read/WriteB Select */
VINT32 rlps_eq_ctlsts; /* FE RLPS Equalizer Loop Sts & Ctl */
VINT32 rlps_eq_cfg; /* FF RLPS Equalizer Cfg */
};
/* 00AH: MDIAG Register bit definitions */
#define COMET_MDIAG_ID5 0x40
#define COMET_MDIAG_LBMASK 0x3F
#define COMET_MDIAG_PAYLB 0x20
#define COMET_MDIAG_LINELB 0x10
#define COMET_MDIAG_RAIS 0x08
#define COMET_MDIAG_DDLB 0x04
#define COMET_MDIAG_TXMFP 0x02
#define COMET_MDIAG_TXLOS 0x01
#define COMET_MDIAG_LBOFF 0x00
#undef VINT32
#ifdef __KERNEL__
extern void
init_comet(void *, struct s_comet_reg *, u_int32_t, int, u_int8_t);
#endif
#endif /* _INC_COMET_H_ */
drivers/staging/cxt1e1/comet_tables.c 已删除 100644 → 0
浏览文件 @ 19b1e769
此差异已折叠。
drivers/staging/cxt1e1/comet_tables.h 已删除 100644 → 0
浏览文件 @ 19b1e769
#ifndef _INC_COMET_TBLS_H_
#define _INC_COMET_TBLS_H_
/*-----------------------------------------------------------------------------
* comet_tables.h - Waveform Tables for the PM4351 'COMET'
*
* Copyright (C) 2005 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* For further information, contact via email: support@sbei.com
* SBE, Inc. San Ramon, California U.S.A.
*-----------------------------------------------------------------------------
*/
/*****************************************************************************
*
* Array names:
*
* TWVLongHaul0DB
* TWVLongHaul7_5DB
* TWVLongHaul15DB
* TWVLongHaul22_5DB
* TWVShortHaul0
* TWVShortHaul1
* TWVShortHaul2
* TWVShortHaul3
* TWVShortHaul4
* TWVShortHaul5
* TWV_E1_120Ohm
* TWV_E1_75Ohm <not supported>
* T1_Equalizer
* E1_Equalizer
*
*****************************************************************************/
extern u_int8_t TWVLongHaul0DB[25][5]; /* T1 Long Haul 0 DB */
extern u_int8_t TWVLongHaul7_5DB[25][5]; /* T1 Long Haul 7.5 DB */
extern u_int8_t TWVLongHaul15DB[25][5]; /* T1 Long Haul 15 DB */
extern u_int8_t TWVLongHaul22_5DB[25][5]; /* T1 Long Haul 22.5 DB */
extern u_int8_t TWVShortHaul0[25][5]; /* T1 Short Haul 0-110 ft */
extern u_int8_t TWVShortHaul1[25][5]; /* T1 Short Haul 110-220 ft */
extern u_int8_t TWVShortHaul2[25][5]; /* T1 Short Haul 220-330 ft */
extern u_int8_t TWVShortHaul3[25][5]; /* T1 Short Haul 330-440 ft */
extern u_int8_t TWVShortHaul4[25][5]; /* T1 Short Haul 440-550 ft */
extern u_int8_t TWVShortHaul5[25][5]; /* T1 Short Haul 550-660 ft */
extern u_int8_t TWV_E1_75Ohm[25][5]; /* E1 75 Ohm */
extern u_int8_t TWV_E1_120Ohm[25][5]; /* E1 120 Ohm */
extern u_int32_t T1_Equalizer[256]; /* T1 Receiver Equalizer */
extern u_int32_t E1_Equalizer[256]; /* E1 Receiver Equalizer */
#endif /* _INC_COMET_TBLS_H_ */
drivers/staging/cxt1e1/functions.c 已删除 100644 → 0
浏览文件 @ 19b1e769
/* Copyright (C) 2003-2005 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/slab.h>
#include <linux/io.h>
#include <asm/byteorder.h>
#include <linux/netdevice.h>
#include <linux/delay.h>
#include <linux/hdlc.h>
#include "pmcc4_sysdep.h"
#include "sbecom_inline_linux.h"
#include "libsbew.h"
#include "pmcc4.h"
#ifndef USE_MAX_INT_DELAY
static int dummy = 0;
#endif
extern int drvr_state;
#if 1
u_int32_t
pci_read_32(u_int32_t *p)
{
#ifdef FLOW_DEBUG
u_int32_t v;
FLUSH_PCI_READ();
v = le32_to_cpu(*p);
if (cxt1e1_log_level >= LOG_DEBUG)
pr_info("pci_read : %x = %x\n", (u_int32_t) p, v);
return v;
#else
FLUSH_PCI_READ(); /* */
return le32_to_cpu(*p);
#endif
}
void
pci_write_32(u_int32_t *p, u_int32_t v)
{
#ifdef FLOW_DEBUG
if (cxt1e1_log_level >= LOG_DEBUG)
pr_info("pci_write: %x = %x\n", (u_int32_t) p, v);
#endif
*p = cpu_to_le32 (v);
FLUSH_PCI_WRITE(); /* This routine is called from routines
* which do multiple register writes
* which themselves need flushing between
* writes in order to guarantee write
* ordering. It is less code-cumbersome
* to flush here-in then to investigate
* and code the many other register
* writing routines. */
}
#endif
void
pci_flush_write(ci_t *ci)
{
volatile u_int32_t v;
/* issue a PCI read to flush PCI write thru bridge */
v = *(u_int32_t *) &ci->reg->glcd; /* any address would do */
/*
* return nothing, this just reads PCI bridge interface to flush
* previously written data
*/
}
static void
watchdog_func(unsigned long arg)
{
struct watchdog *wd = (void *) arg;
if (drvr_state != SBE_DRVR_AVAILABLE) {
if (cxt1e1_log_level >= LOG_MONITOR)
pr_warning("%s: drvr not available (%x)\n",
__func__, drvr_state);
return;
}
schedule_work(&wd->work);
mod_timer(&wd->h, jiffies + wd->ticks);
}
int OS_init_watchdog(struct watchdog *wdp, void (*f) (void *),
void *c, int usec)
{
wdp->func = f;
wdp->softc = c;
wdp->ticks = (HZ) * (usec / 1000) / 1000;
INIT_WORK(&wdp->work, (void *)f);
init_timer(&wdp->h);
{
ci_t *ci = (ci_t *) c;
wdp->h.data = (unsigned long) &ci->wd;
}
wdp->h.function = watchdog_func;
return 0;
}
void
OS_uwait(int usec, char *description)
{
int tmp;
if (usec >= 1000) {
mdelay(usec / 1000);
/* now delay residual */
tmp = (usec / 1000) * 1000; /* round */
tmp = usec - tmp; /* residual */
if (tmp) { /* wait on residual */
udelay(tmp);
}
} else {
udelay(usec);
}
}
/* dummy short delay routine called as a subroutine so that compiler
* does not optimize/remove its intent (a short delay)
*/
void
OS_uwait_dummy(void)
{
#ifndef USE_MAX_INT_DELAY
dummy++;
#else
udelay(1);
#endif
}
void
OS_sem_init(void *sem, int state)
{
switch (state) {
case SEM_TAKEN:
sema_init((struct semaphore *) sem, 0);
break;
case SEM_AVAILABLE:
sema_init((struct semaphore *) sem, 1);
break;
default: /* otherwise, set sem.count to state's
* value */
sema_init(sem, state);
break;
}
}
int
sd_line_is_ok(void *user)
{
struct net_device *ndev = (struct net_device *) user;
return netif_carrier_ok(ndev);
}
void
sd_line_is_up(void *user)
{
struct net_device *ndev = (struct net_device *) user;
netif_carrier_on(ndev);
return;
}
void
sd_line_is_down(void *user)
{
struct net_device *ndev = (struct net_device *) user;
netif_carrier_off(ndev);
return;
}
void
sd_disable_xmit(void *user)
{
struct net_device *dev = (struct net_device *) user;
netif_stop_queue(dev);
return;
}
void
sd_enable_xmit(void *user)
{
struct net_device *dev = (struct net_device *) user;
netif_wake_queue(dev);
return;
}
int
sd_queue_stopped(void *user)
{
struct net_device *ndev = (struct net_device *) user;
return netif_queue_stopped(ndev);
}
void sd_recv_consume(void *token, size_t len, void *user)
{
struct net_device *ndev = user;
struct sk_buff *skb = token;
skb->dev = ndev;
skb_put(skb, len);
skb->protocol = hdlc_type_trans(skb, ndev);
netif_rx(skb);
}
/**
** Read some reserved location w/in the COMET chip as a usable
** VMETRO trigger point or other trace marking event.
**/
#include "comet.h"
extern ci_t *CI; /* dummy pointer to board ZERO's data */
void
VMETRO_TRIGGER(ci_t *ci, int x)
{
struct s_comet_reg *comet;
volatile u_int32_t data;
comet = ci->port[0].cometbase; /* default to COMET # 0 */
switch (x) {
default:
case 0:
data = pci_read_32((u_int32_t *) &comet->__res24); /* 0x90 */
break;
case 1:
data = pci_read_32((u_int32_t *) &comet->__res25); /* 0x94 */
break;
case 2:
data = pci_read_32((u_int32_t *) &comet->__res26); /* 0x98 */
break;
case 3:
data = pci_read_32((u_int32_t *) &comet->__res27); /* 0x9C */
break;
case 4:
data = pci_read_32((u_int32_t *) &comet->__res88); /* 0x220 */
break;
case 5:
data = pci_read_32((u_int32_t *) &comet->__res89); /* 0x224 */
break;
case 6:
data = pci_read_32((u_int32_t *) &comet->__res8A); /* 0x228 */
break;
case 7:
data = pci_read_32((u_int32_t *) &comet->__res8B); /* 0x22C */
break;
case 8:
data = pci_read_32((u_int32_t *) &comet->__resA0); /* 0x280 */
break;
case 9:
data = pci_read_32((u_int32_t *) &comet->__resA1); /* 0x284 */
break;
case 10:
data = pci_read_32((u_int32_t *) &comet->__resA2); /* 0x288 */
break;
case 11:
data = pci_read_32((u_int32_t *) &comet->__resA3); /* 0x28C */
break;
case 12:
data = pci_read_32((u_int32_t *) &comet->__resA4); /* 0x290 */
break;
case 13:
data = pci_read_32((u_int32_t *) &comet->__resA5); /* 0x294 */
break;
case 14:
data = pci_read_32((u_int32_t *) &comet->__resA6); /* 0x298 */
break;
case 15:
data = pci_read_32((u_int32_t *) &comet->__resA7); /* 0x29C */
break;
case 16:
data = pci_read_32((u_int32_t *) &comet->__res74); /* 0x1D0 */
break;
case 17:
data = pci_read_32((u_int32_t *) &comet->__res75); /* 0x1D4 */
break;
case 18:
data = pci_read_32((u_int32_t *) &comet->__res76); /* 0x1D8 */
break;
case 19:
data = pci_read_32((u_int32_t *) &comet->__res77); /* 0x1DC */
break;
}
}
/*** End-of-File ***/
drivers/staging/cxt1e1/hwprobe.c 已删除 100644 → 0
浏览文件 @ 19b1e769
/* Copyright (C) 2007 One Stop Systems
* Copyright (C) 2003-2005 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/netdevice.h>
#include <linux/hdlc.h>
#include <linux/if_arp.h>
#include <asm/uaccess.h>
#include <linux/rtnetlink.h>
#include <linux/pci.h>
#include "pmcc4_sysdep.h"
#include "sbecom_inline_linux.h"
#include "libsbew.h"
#include "pmcc4_private.h"
#include "pmcc4.h"
#include "pmcc4_ioctls.h"
#include "pmc93x6_eeprom.h"
#ifdef CONFIG_PROC_FS
#include "sbeproc.h"
#endif
extern int error_flag;
extern int drvr_state;
/* forward references */
void c4_stopwd(ci_t *);
struct net_device * __init c4_add_dev(hdw_info_t *, int, unsigned long,
unsigned long, int, int);
struct s_hdw_info hdw_info[MAX_BOARDS];
void __init
show_two(hdw_info_t *hi, int brdno)
{
ci_t *ci;
struct pci_dev *pdev;
char *bid;
char banner[80];
char sn[6] = {0,};
ci = (ci_t *)(netdev_priv(hi->ndev));
bid = sbeid_get_bdname(ci);
switch (hi->promfmt) {
case PROM_FORMAT_TYPE1:
memcpy(sn, hi->mfg_info.pft1.Serial, 6);
break;
case PROM_FORMAT_TYPE2:
memcpy(sn, hi->mfg_info.pft2.Serial, 6);
break;
}
sprintf(banner, "%s: %s S/N %06X, MUSYCC Rev %02X",
hi->devname, bid,
((sn[3] << 16) & 0xff0000) |
((sn[4] << 8) & 0x00ff00) |
(sn[5] & 0x0000ff),
(u_int8_t) hi->revid[0]);
pr_info("%s\n", banner);
pdev = hi->pdev[0];
pr_info("%s: %s at v/p=%lx/%lx (%02x:%02x.%x) irq %d\n",
hi->devname, "MUSYCC",
(unsigned long) hi->addr_mapped[0], hi->addr[0],
hi->pci_busno, (u_int8_t) PCI_SLOT(pdev->devfn),
(u_int8_t) PCI_FUNC(pdev->devfn), pdev->irq);
pdev = hi->pdev[1];
pr_info("%s: %s at v/p=%lx/%lx (%02x:%02x.%x) irq %d\n",
hi->devname, "EBUS ",
(unsigned long) hi->addr_mapped[1], hi->addr[1],
hi->pci_busno, (u_int8_t) PCI_SLOT(pdev->devfn),
(u_int8_t) PCI_FUNC(pdev->devfn), pdev->irq);
}
void __init
hdw_sn_get(hdw_info_t *hi, int brdno)
{
/* obtain hardware EEPROM information */
long addr;
addr = (long) hi->addr_mapped[1] + EEPROM_OFFSET;
/* read EEPROM with largest known format size... */
pmc_eeprom_read_buffer(addr, 0, (char *)hi->mfg_info.data,
sizeof(FLD_TYPE2));
#if 0
{
unsigned char *ucp = (unsigned char *) &hi->mfg_info.data;
pr_info("eeprom[00]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
*(ucp + 0), *(ucp + 1), *(ucp + 2), *(ucp + 3),
*(ucp + 4), *(ucp + 5), *(ucp + 6), *(ucp + 7));
pr_info("eeprom[08]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
*(ucp + 8), *(ucp + 9), *(ucp + 10), *(ucp + 11),
*(ucp + 12), *(ucp + 13), *(ucp + 14), *(ucp + 15));
pr_info("eeprom[16]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
*(ucp + 16), *(ucp + 17), *(ucp + 18), *(ucp + 19),
*(ucp + 20), *(ucp + 21), *(ucp + 22), *(ucp + 23));
pr_info("eeprom[24]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
*(ucp + 24), *(ucp + 25), *(ucp + 26), *(ucp + 27),
*(ucp + 28), *(ucp + 29), *(ucp + 30), *(ucp + 31));
pr_info("eeprom[32]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
*(ucp + 32), *(ucp + 33), *(ucp + 34), *(ucp + 35),
*(ucp + 36), *(ucp + 37), *(ucp + 38), *(ucp + 39));
pr_info("eeprom[40]: %02x %02x %02x %02x %02x %02x %02x %02x\n",
*(ucp + 40), *(ucp + 41), *(ucp + 42), *(ucp + 43),
*(ucp + 44), *(ucp + 45), *(ucp + 46), *(ucp + 47));
}
#endif
#if 0
pr_info("sn: %x %x %x %x %x %x\n",
hi->mfg_info.Serial[0],
hi->mfg_info.Serial[1],
hi->mfg_info.Serial[2],
hi->mfg_info.Serial[3],
hi->mfg_info.Serial[4],
hi->mfg_info.Serial[5]);
#endif
hi->promfmt = pmc_verify_cksum(&hi->mfg_info.data);
if (hi->promfmt == PROM_FORMAT_Unk) {
/* bad crc, data is suspect */
if (cxt1e1_log_level >= LOG_WARN)
pr_info("%s: EEPROM cksum error\n", hi->devname);
hi->mfg_info_sts = EEPROM_CRCERR;
} else
hi->mfg_info_sts = EEPROM_OK;
}
void __init
prep_hdw_info(void)
{
hdw_info_t *hi;
int i;
for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
hi->pci_busno = 0xff;
hi->pci_slot = 0xff;
hi->pci_pin[0] = 0;
hi->pci_pin[1] = 0;
hi->ndev = NULL;
hi->addr[0] = 0L;
hi->addr[1] = 0L;
hi->addr_mapped[0] = NULL;
hi->addr_mapped[1] = NULL;
}
}
void
cleanup_ioremap(void)
{
hdw_info_t *hi;
int i;
for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
if (hi->pci_slot == 0xff)
break;
if (hi->addr_mapped[0]) {
iounmap(hi->addr_mapped[0]);
release_mem_region((long) hi->addr[0], hi->len[0]);
hi->addr_mapped[0] = NULL;
}
if (hi->addr_mapped[1]) {
iounmap(hi->addr_mapped[1]);
release_mem_region((long) hi->addr[1], hi->len[1]);
hi->addr_mapped[1] = NULL;
}
}
}
void
cleanup_devs(void)
{
hdw_info_t *hi;
int i;
for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
if (hi->pci_slot == 0xff || !hi->ndev)
break;
c4_stopwd(netdev_priv(hi->ndev));
#ifdef CONFIG_PROC_FS
sbecom_proc_brd_cleanup(netdev_priv(hi->ndev));
#endif
unregister_netdev(hi->ndev);
free_irq(hi->pdev[0]->irq, hi->ndev);
#ifdef CONFIG_SBE_PMCC4_NCOMM
free_irq(hi->pdev[1]->irq, hi->ndev);
#endif
kfree(hi->ndev);
}
}
static int __init
c4_hdw_init(struct pci_dev *pdev, int found)
{
hdw_info_t *hi;
int i;
int fun, slot;
unsigned char busno = 0xff;
/* our MUSYCC chip supports two functions, 0 & 1 */
fun = PCI_FUNC(pdev->devfn);
if (fun > 1) {
pr_warning("unexpected devfun: 0x%x\n", pdev->devfn);
return 0;
}
/* obtain bus number */
if (pdev->bus)
busno = pdev->bus->number;
else
busno = 0; /* default for system PCI inconsistency */
slot = pdev->devfn & ~0x07;
/*
* Functions 0 & 1 for a given board (identified by same bus(busno) and
* slot(slot)) are placed into the same 'hardware' structure. The first
* part of the board's functionality will be placed into an unpopulated
* element, identified by "slot==(0xff)". The second part of a board's
* functionality will match the previously loaded slot/busno.
*/
for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
/*
* match with board's first found interface, otherwise this is
* fisrt found
*/
if ((hi->pci_slot == 0xff) || /* new board */
((hi->pci_slot == slot) && (hi->bus == pdev->bus)))
break; /* found for-loop exit */
}
/* no match in above loop means MAX exceeded */
if (i == MAX_BOARDS) {
pr_warning("exceeded number of allowed devices (>%d)?\n",
MAX_BOARDS);
return 0;
}
if (pdev->bus)
hi->pci_busno = pdev->bus->number;
else
hi->pci_busno = 0; /* default for system PCI inconsistency */
hi->pci_slot = slot;
pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &hi->pci_pin[fun]);
pci_read_config_byte(pdev, PCI_REVISION_ID, &hi->revid[fun]);
hi->bus = pdev->bus;
hi->addr[fun] = pci_resource_start(pdev, 0);
hi->len[fun] = pci_resource_end(pdev, 0) - hi->addr[fun] + 1;
hi->pdev[fun] = pdev;
{
/*
* create device name from module name, plus add the appropriate
* board number
*/
char *cp = hi->devname;
strcpy(cp, KBUILD_MODNAME);
cp += strlen(cp); /* reposition */
*cp++ = '-';
*cp++ = '0' + (found / 2); /* there are two found interfaces per
* board */
*cp = 0; /* termination */
}
return 1;
}
status_t __init
c4hw_attach_all(void)
{
hdw_info_t *hi;
struct pci_dev *pdev = NULL;
int found = 0, i, j;
error_flag = 0;
prep_hdw_info();
/*** scan PCI bus for all possible boards */
while ((pdev = pci_get_device(PCI_VENDOR_ID_CONEXANT,
PCI_DEVICE_ID_CN8474,
pdev))) {
if (c4_hdw_init(pdev, found))
found++;
}
if (!found) {
pr_warning("No boards found\n");
return -ENODEV;
}
/* sanity check for consistent hardware found */
for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
if (hi->pci_slot != 0xff && (!hi->addr[0] || !hi->addr[1])) {
pr_warning("%s: something very wrong with pci_get_device\n",
hi->devname);
return -EIO;
}
}
/* bring board's memory regions on/line */
for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
if (hi->pci_slot == 0xff)
break;
for (j = 0; j < 2; j++) {
if (!request_mem_region(hi->addr[j], hi->len[j], hi->devname)) {
pr_warning("%s: memory in use, addr=0x%lx, len=0x%lx ?\n",
hi->devname, hi->addr[j], hi->len[j]);
cleanup_ioremap();
return -ENOMEM;
}
hi->addr_mapped[j] = ioremap(hi->addr[j], hi->len[j]);
if (!hi->addr_mapped[j]) {
pr_warning("%s: ioremap fails, addr=0x%lx, len=0x%lx ?\n",
hi->devname, hi->addr[j], hi->len[j]);
cleanup_ioremap();
return -ENOMEM;
}
#ifdef SBE_MAP_DEBUG
pr_warning("%s: io remapped from phys %x to virt %x\n",
hi->devname, (u_int32_t) hi->addr[j],
(u_int32_t) hi->addr_mapped[j]);
#endif
}
}
drvr_state = SBE_DRVR_AVAILABLE;
/* Have now memory mapped all boards. Now allow board's access to system */
for (i = 0, hi = hdw_info; i < MAX_BOARDS; i++, hi++) {
if (hi->pci_slot == 0xff)
break;
if (pci_enable_device(hi->pdev[0]) ||
pci_enable_device(hi->pdev[1])) {
drvr_state = SBE_DRVR_DOWN;
pr_warning("%s: failed to enable card %d slot %d\n",
hi->devname, i, hi->pci_slot);
cleanup_devs();
cleanup_ioremap();
return -EIO;
}
pci_set_master(hi->pdev[0]);
pci_set_master(hi->pdev[1]);
hi->ndev = c4_add_dev(hi, i, (long) hi->addr_mapped[0],
(long) hi->addr_mapped[1],
hi->pdev[0]->irq,
hi->pdev[1]->irq);
if (!hi->ndev) {
drvr_state = SBE_DRVR_DOWN;
cleanup_ioremap();
/* NOTE: c4_add_dev() does its own device cleanup */
#if 0
cleanup_devs();
#endif
return error_flag; /* error_flag set w/in add_dev() */
}
show_two(hi, i); /* displays found information */
}
return 0;
}
/*** End-of-File ***/
drivers/staging/cxt1e1/libsbew.h 已删除 100644 → 0
浏览文件 @ 19b1e769
此差异已折叠。
drivers/staging/cxt1e1/linux.c 已删除 100644 → 0
浏览文件 @ 19b1e769
此差异已折叠。
drivers/staging/cxt1e1/musycc.c 已删除 100644 → 0
浏览文件 @ 19b1e769
此差异已折叠。
drivers/staging/cxt1e1/musycc.h 已删除 100644 → 0
浏览文件 @ 19b1e769
#ifndef _INC_MUSYCC_H_
#define _INC_MUSYCC_H_
/*-----------------------------------------------------------------------------
* musycc.h - Multichannel Synchronous Communications Controller
* CN8778/8474A/8472A/8471A
*
* Copyright (C) 2002-2005 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* For further information, contact via email: support@sbei.com
* SBE, Inc. San Ramon, California U.S.A.
*-----------------------------------------------------------------------------
*/
#include <linux/types.h>
#define VINT8 volatile u_int8_t
#define VINT32 volatile u_int32_t
#include "pmcc4_defs.h"
/*------------------------------------------------------------------------
// Vendor, Board Identification definitions
//------------------------------------------------------------------------
*/
#define PCI_VENDOR_ID_CONEXANT 0x14f1
#define PCI_DEVICE_ID_CN8471 0x8471
#define PCI_DEVICE_ID_CN8472 0x8472
#define PCI_DEVICE_ID_CN8474 0x8474
#define PCI_DEVICE_ID_CN8478 0x8478
#define PCI_DEVICE_ID_CN8500 0x8500
#define PCI_DEVICE_ID_CN8501 0x8501
#define PCI_DEVICE_ID_CN8502 0x8502
#define PCI_DEVICE_ID_CN8503 0x8503
#define INT_QUEUE_SIZE MUSYCC_NIQD
/* RAM image of MUSYCC registers laid out as a C structure */
struct musycc_groupr {
VINT32 thp[32]; /* Transmit Head Pointer [5-29] */
VINT32 tmp[32]; /* Transmit Message Pointer [5-30] */
VINT32 rhp[32]; /* Receive Head Pointer [5-29] */
VINT32 rmp[32]; /* Receive Message Pointer [5-30] */
VINT8 ttsm[128]; /* Time Slot Map [5-22] */
VINT8 tscm[256]; /* Subchannel Map [5-24] */
VINT32 tcct[32]; /* Channel Configuration [5-26] */
VINT8 rtsm[128]; /* Time Slot Map [5-22] */
VINT8 rscm[256]; /* Subchannel Map [5-24] */
VINT32 rcct[32]; /* Channel Configuration [5-26] */
VINT32 __glcd; /* Global Configuration Descriptor [5-10] */
VINT32 __iqp; /* Interrupt Queue Pointer [5-36] */
VINT32 __iql; /* Interrupt Queue Length [5-36] */
VINT32 grcd; /* Group Configuration Descriptor [5-16] */
VINT32 mpd; /* Memory Protection Descriptor [5-18] */
VINT32 mld; /* Message Length Descriptor [5-20] */
VINT32 pcd; /* Port Configuration Descriptor [5-19] */
};
/* hardware MUSYCC registers laid out as a C structure */
struct musycc_globalr {
VINT32 gbp; /* Group Base Pointer */
VINT32 dacbp; /* Dual Address Cycle Base Pointer */
VINT32 srd; /* Service Request Descriptor */
VINT32 isd; /* Interrupt Service Descriptor */
/*
* adjust __thp due to above 4 registers, which are not contained
* within musycc_groupr[]. All __XXX[] are just place holders,
* anyhow.
*/
VINT32 __thp[32 - 4]; /* Transmit Head Pointer [5-29] */
VINT32 __tmp[32]; /* Transmit Message Pointer [5-30] */
VINT32 __rhp[32]; /* Receive Head Pointer [5-29] */
VINT32 __rmp[32]; /* Receive Message Pointer [5-30] */
VINT8 ttsm[128]; /* Time Slot Map [5-22] */
VINT8 tscm[256]; /* Subchannel Map [5-24] */
VINT32 tcct[32]; /* Channel Configuration [5-26] */
VINT8 rtsm[128]; /* Time Slot Map [5-22] */
VINT8 rscm[256]; /* Subchannel Map [5-24] */
VINT32 rcct[32]; /* Channel Configuration [5-26] */
VINT32 glcd; /* Global Configuration Descriptor [5-10] */
VINT32 iqp; /* Interrupt Queue Pointer [5-36] */
VINT32 iql; /* Interrupt Queue Length [5-36] */
VINT32 grcd; /* Group Configuration Descriptor [5-16] */
VINT32 mpd; /* Memory Protection Descriptor [5-18] */
VINT32 mld; /* Message Length Descriptor [5-20] */
VINT32 pcd; /* Port Configuration Descriptor [5-19] */
VINT32 rbist; /* Receive BIST status [5-4] */
VINT32 tbist; /* Receive BIST status [5-4] */
};
/* Global Config Descriptor bit macros */
#define MUSYCC_GCD_ECLK_ENABLE 0x00000800 /* EBUS clock enable */
#define MUSYCC_GCD_INTEL_SELECT 0x00000400 /* MPU type select */
#define MUSYCC_GCD_INTA_DISABLE 0x00000008 /* PCI INTA disable */
#define MUSYCC_GCD_INTB_DISABLE 0x00000004 /* PCI INTB disable */
#define MUSYCC_GCD_BLAPSE 12 /* Position index for BLAPSE bit
* field */
#define MUSYCC_GCD_ALAPSE 8 /* Position index for ALAPSE bit
* field */
#define MUSYCC_GCD_ELAPSE 4 /* Position index for ELAPSE bit
* field */
#define MUSYCC_GCD_PORTMAP_3 3 /* Reserved */
#define MUSYCC_GCD_PORTMAP_2 2 /* Port 0=>Grp 0,1,2,3; Port 1=>Grp
* 4,5,6,7 */
#define MUSYCC_GCD_PORTMAP_1 1 /* Port 0=>Grp 0,1; Port 1=>Grp 2,3,
* etc... */
#define MUSYCC_GCD_PORTMAP_0 0 /* Port 0=>Grp 0; Port 1=>Grp 2,
* etc... */
/* and board specific assignments... */
#ifdef SBE_WAN256T3_ENABLE
#define BLAPSE_VAL 0
#define ALAPSE_VAL 0
#define ELAPSE_VAL 7
#define PORTMAP_VAL MUSYCC_GCD_PORTMAP_2
#endif
#ifdef SBE_PMCC4_ENABLE
#define BLAPSE_VAL 7
#define ALAPSE_VAL 3
#define ELAPSE_VAL 7
#define PORTMAP_VAL MUSYCC_GCD_PORTMAP_0
#endif
#define GCD_MAGIC (((BLAPSE_VAL)<<(MUSYCC_GCD_BLAPSE)) | \
((ALAPSE_VAL)<<(MUSYCC_GCD_ALAPSE)) | \
((ELAPSE_VAL)<<(MUSYCC_GCD_ELAPSE)) | \
(MUSYCC_GCD_ECLK_ENABLE) | PORTMAP_VAL)
/* Group Config Descriptor bit macros */
#define MUSYCC_GRCD_RX_ENABLE 0x00000001 /* Enable receive processing */
#define MUSYCC_GRCD_TX_ENABLE 0x00000002 /* Enable transmit processing */
#define MUSYCC_GRCD_SUBCHAN_DISABLE 0x00000004 /* Master disable for
* subchanneling */
#define MUSYCC_GRCD_OOFMP_DISABLE 0x00000008 /* Out of Frame message
* processing disabled all
* channels */
#define MUSYCC_GRCD_OOFIRQ_DISABLE 0x00000010 /* Out of Frame/In Frame irqs
* disabled */
#define MUSYCC_GRCD_COFAIRQ_DISABLE 0x00000020 /* Change of Frame Alignment
* irq disabled */
#define MUSYCC_GRCD_INHRBSD 0x00000100 /* Receive Buffer Status
* overwrite disabled */
#define MUSYCC_GRCD_INHTBSD 0x00000200 /* Transmit Buffer Status
* overwrite disabled */
#define MUSYCC_GRCD_SF_ALIGN 0x00008000 /* External frame sync */
#define MUSYCC_GRCD_MC_ENABLE 0x00000040 /* Message configuration bits
* copy enable. Conexant sez
* turn this on */
#define MUSYCC_GRCD_POLLTH_16 0x00000001 /* Poll every 16th frame */
#define MUSYCC_GRCD_POLLTH_32 0x00000002 /* Poll every 32nd frame */
#define MUSYCC_GRCD_POLLTH_64 0x00000003 /* Poll every 64th frame */
#define MUSYCC_GRCD_POLLTH_SHIFT 10 /* Position index for poll throttle
* bit field */
#define MUSYCC_GRCD_SUERM_THRESH_SHIFT 16 /* Position index for SUERM
* count threshold */
/* Port Config Descriptor bit macros */
#define MUSYCC_PCD_E1X2_MODE 2 /* Port mode in bits 0-2. T1 and E1 */
#define MUSYCC_PCD_E1X4_MODE 3 /* are defined in cn847x.h */
#define MUSYCC_PCD_NX64_MODE 4
#define MUSYCC_PCD_TXDATA_RISING 0x00000010 /* Sample Tx data on TCLK
* rising edge */
#define MUSYCC_PCD_TXSYNC_RISING 0x00000020 /* Sample Tx frame sync on
* TCLK rising edge */
#define MUSYCC_PCD_RXDATA_RISING 0x00000040 /* Sample Rx data on RCLK
* rising edge */
#define MUSYCC_PCD_RXSYNC_RISING 0x00000080 /* Sample Rx frame sync on
* RCLK rising edge */
#define MUSYCC_PCD_ROOF_RISING 0x00000100 /* Sample Rx Out Of Frame
* signal on RCLK rising edge */
#define MUSYCC_PCD_TX_DRIVEN 0x00000200 /* No mapped timeslots causes
* logic 1 on output, else
* tristate */
#define MUSYCC_PCD_PORTMODE_MASK 0xfffffff8 /* For changing the port mode
* between E1 and T1 */
/* Time Slot Descriptor bit macros */
#define MUSYCC_TSD_MODE_64KBPS 4
#define MUSYCC_TSD_MODE_56KBPS 5
#define MUSYCC_TSD_SUBCHANNEL_WO_FIRST 6
#define MUSYCC_TSD_SUBCHANNEL_WITH_FIRST 7
/* Message Descriptor bit macros */
#define MUSYCC_MDT_BASE03_ADDR 0x00006000
/* Channel Config Descriptor bit macros */
#define MUSYCC_CCD_BUFIRQ_DISABLE 0x00000002 /* BUFF and ONR irqs disabled */
#define MUSYCC_CCD_EOMIRQ_DISABLE 0x00000004 /* EOM irq disabled */
#define MUSYCC_CCD_MSGIRQ_DISABLE 0x00000008 /* LNG, FCS, ALIGN, and ABT
* irqs disabled */
#define MUSYCC_CCD_IDLEIRQ_DISABLE 0x00000010 /* CHABT, CHIC, and SHT irqs
* disabled */
#define MUSYCC_CCD_FILTIRQ_DISABLE 0x00000020 /* SFILT irq disabled */
#define MUSYCC_CCD_SDECIRQ_DISABLE 0x00000040 /* SDEC irq disabled */
#define MUSYCC_CCD_SINCIRQ_DISABLE 0x00000080 /* SINC irq disabled */
#define MUSYCC_CCD_SUERIRQ_DISABLE 0x00000100 /* SUERR irq disabled */
#define MUSYCC_CCD_FCS_XFER 0x00000200 /* Propagate FCS along with
* received data */
#define MUSYCC_CCD_PROTO_SHIFT 12 /* Position index for protocol bit
* field */
#define MUSYCC_CCD_TRANS 0 /* Protocol mode in bits 12-14 */
#define MUSYCC_CCD_SS7 1
#define MUSYCC_CCD_HDLC_FCS16 2
#define MUSYCC_CCD_HDLC_FCS32 3
#define MUSYCC_CCD_EOPIRQ_DISABLE 0x00008000 /* EOP irq disabled */
#define MUSYCC_CCD_INVERT_DATA 0x00800000 /* Invert data */
#define MUSYCC_CCD_MAX_LENGTH 10 /* Position index for max length bit
* field */
#define MUSYCC_CCD_BUFFER_LENGTH 16 /* Position index for internal data
* buffer length */
#define MUSYCC_CCD_BUFFER_LOC 24 /* Position index for internal data
* buffer starting location */
/****************************************************************************
* Interrupt Descriptor Information */
#define INT_EMPTY_ENTRY 0xfeedface
#define INT_EMPTY_ENTRY2 0xdeadface
/****************************************************************************
* Interrupt Status Descriptor
*
* NOTE: One must first fetch the value of the interrupt status descriptor
* into a local variable, then pass that value into the read macros. This
* is required to avoid race conditions.
***/
#define INTRPTS_NEXTINT_M 0x7FFF0000
#define INTRPTS_NEXTINT_S 16
#define INTRPTS_NEXTINT(x) ((x & INTRPTS_NEXTINT_M) >> INTRPTS_NEXTINT_S)
#define INTRPTS_INTFULL_M 0x00008000
#define INTRPTS_INTFULL_S 15
#define INTRPTS_INTFULL(x) ((x & INTRPTS_INTFULL_M) >> INTRPTS_INTFULL_S)
#define INTRPTS_INTCNT_M 0x00007FFF
#define INTRPTS_INTCNT_S 0
#define INTRPTS_INTCNT(x) ((x & INTRPTS_INTCNT_M) >> INTRPTS_INTCNT_S)
/****************************************************************************
* Interrupt Descriptor
***/
#define INTRPT_DIR_M 0x80000000
#define INTRPT_DIR_S 31
#define INTRPT_DIR(x) ((x & INTRPT_DIR_M) >> INTRPT_DIR_S)
#define INTRPT_GRP_M 0x60000000
#define INTRPT_GRP_MSB_M 0x00004000
#define INTRPT_GRP_S 29
#define INTRPT_GRP_MSB_S 12
#define INTRPT_GRP(x) (((x & INTRPT_GRP_M) >> INTRPT_GRP_S) | \
((x & INTRPT_GRP_MSB_M) >> INTRPT_GRP_MSB_S))
#define INTRPT_CH_M 0x1F000000
#define INTRPT_CH_S 24
#define INTRPT_CH(x) ((x & INTRPT_CH_M) >> INTRPT_CH_S)
#define INTRPT_EVENT_M 0x00F00000
#define INTRPT_EVENT_S 20
#define INTRPT_EVENT(x) ((x & INTRPT_EVENT_M) >> INTRPT_EVENT_S)
#define INTRPT_ERROR_M 0x000F0000
#define INTRPT_ERROR_S 16
#define INTRPT_ERROR(x) ((x & INTRPT_ERROR_M) >> INTRPT_ERROR_S)
#define INTRPT_ILOST_M 0x00008000
#define INTRPT_ILOST_S 15
#define INTRPT_ILOST(x) ((x & INTRPT_ILOST_M) >> INTRPT_ILOST_S)
#define INTRPT_PERR_M 0x00004000
#define INTRPT_PERR_S 14
#define INTRPT_PERR(x) ((x & INTRPT_PERR_M) >> INTRPT_PERR_S)
#define INTRPT_BLEN_M 0x00003FFF
#define INTRPT_BLEN_S 0
#define INTRPT_BLEN(x) ((x & INTRPT_BLEN_M) >> INTRPT_BLEN_S)
/* Buffer Descriptor bit macros */
#define OWNER_BIT 0x80000000 /* Set for MUSYCC owner on xmit, host
* owner on receive */
#define HOST_TX_OWNED 0x00000000 /* Host owns descriptor */
#define MUSYCC_TX_OWNED 0x80000000 /* MUSYCC owns descriptor */
#define HOST_RX_OWNED 0x80000000 /* Host owns descriptor */
#define MUSYCC_RX_OWNED 0x00000000 /* MUSYCC owns descriptor */
#define POLL_DISABLED 0x40000000 /* MUSYCC not allowed to poll buffer
* for ownership */
#define EOMIRQ_ENABLE 0x20000000 /* This buffer contains the end of
* the message */
#define EOBIRQ_ENABLE 0x10000000 /* EOB irq enabled */
#define PADFILL_ENABLE 0x01000000 /* Enable padfill */
#define REPEAT_BIT 0x00008000 /* Bit on for FISU descriptor */
#define LENGTH_MASK 0X3fff /* This part of status descriptor is
* length */
#define IDLE_CODE 25 /* Position index for idle code (2
* bits) */
#define EXTRA_FLAGS 16 /* Position index for minimum flags
* between messages (8 bits) */
#define IDLE_CODE_MASK 0x03 /* Gets rid of garbage before the
* pattern is OR'd in */
#define EXTRA_FLAGS_MASK 0xff /* Gets rid of garbage before the
* pattern is OR'd in */
#define PCI_PERMUTED_OWNER_BIT 0x00000080 /* For flipping the bit on
* the polled mode descriptor */
/* Service Request Descriptor bit macros */
#define SREQ 8 /* Position index for service request bit
* field */
#define SR_NOOP (0<<(SREQ)) /* No Operation. Generates SACK */
#define SR_CHIP_RESET (1<<(SREQ)) /* Soft chip reset */
#define SR_GROUP_RESET (2<<(SREQ)) /* Group reset */
#define SR_GLOBAL_INIT (4<<(SREQ)) /* Global init: read global
* config deswc and interrupt
* queue desc */
#define SR_GROUP_INIT (5<<(SREQ)) /* Group init: read Timeslot
* and Subchannel maps,
* Channel Config, */
/*
* Group Config, Memory Protect, Message Length, and Port Config
* Descriptors
*/
#define SR_CHANNEL_ACTIVATE (8<<(SREQ)) /* Init channel, read Head
* Pointer, process first
* Message Descriptor */
#define SR_GCHANNEL_MASK 0x001F /* channel portion (gchan) */
#define SR_CHANNEL_DEACTIVATE (9<<(SREQ)) /* Stop channel processing */
#define SR_JUMP (10<<(SREQ)) /* a: Process new Message
* List */
#define SR_CHANNEL_CONFIG (11<<(SREQ)) /* b: Read channel
* Configuration Descriptor */
#define SR_GLOBAL_CONFIG (16<<(SREQ)) /* 10: Read Global
* Configuration Descriptor */
#define SR_INTERRUPT_Q (17<<(SREQ)) /* 11: Read Interrupt Queue
* Descriptor */
#define SR_GROUP_CONFIG (18<<(SREQ)) /* 12: Read Group
* Configuration Descriptor */
#define SR_MEMORY_PROTECT (19<<(SREQ)) /* 13: Read Memory Protection
* Descriptor */
#define SR_MESSAGE_LENGTH (20<<(SREQ)) /* 14: Read Message Length
* Descriptor */
#define SR_PORT_CONFIG (21<<(SREQ)) /* 15: Read Port
* Configuration Descriptor */
#define SR_TIMESLOT_MAP (24<<(SREQ)) /* 18: Read Timeslot Map */
#define SR_SUBCHANNEL_MAP (25<<(SREQ)) /* 19: Read Subchannel Map */
#define SR_CHAN_CONFIG_TABLE (26<<(SREQ)) /* 20: Read Channel
* Configuration Table for
* the group */
#define SR_TX_DIRECTION 0x00000020 /* Transmit direction bit.
* Bit off indicates receive
* direction */
#define SR_RX_DIRECTION 0x00000000
/* Interrupt Descriptor bit macros */
#define GROUP10 29 /* Position index for the 2 LS group
* bits */
#define CHANNEL 24 /* Position index for channel bits */
#define INT_IQD_TX 0x80000000
#define INT_IQD_GRP 0x60000000
#define INT_IQD_CHAN 0x1f000000
#define INT_IQD_EVENT 0x00f00000
#define INT_IQD_ERROR 0x000f0000
#define INT_IQD_ILOST 0x00008000
#define INT_IQD_PERR 0x00004000
#define INT_IQD_BLEN 0x00003fff
/* Interrupt Descriptor Events */
#define EVE_EVENT 20 /* Position index for event bits */
#define EVE_NONE 0 /* No event to report in this
* interrupt */
#define EVE_SACK 1 /* Service Request acknowledge */
#define EVE_EOB 2 /* End of Buffer */
#define EVE_EOM 3 /* End of Message */
#define EVE_EOP 4 /* End of Padfill */
#define EVE_CHABT 5 /* Change to Abort Code */
#define EVE_CHIC 6 /* Change to Idle Code */
#define EVE_FREC 7 /* Frame Recovery */
#define EVE_SINC 8 /* MTP2 SUERM Increment */
#define EVE_SDEC 9 /* MTP2 SUERM Decrement */
#define EVE_SFILT 10 /* MTP2 SUERM Filtered Message */
/* Interrupt Descriptor Errors */
#define ERR_ERRORS 16 /* Position index for error bits */
#define ERR_BUF 1 /* Buffer Error */
#define ERR_COFA 2 /* Change of Frame Alignment Error */
#define ERR_ONR 3 /* Owner Bit Error */
#define ERR_PROT 4 /* Memory Protection Error */
#define ERR_OOF 8 /* Out of Frame Error */
#define ERR_FCS 9 /* FCS Error */
#define ERR_ALIGN 10 /* Octet Alignment Error */
#define ERR_ABT 11 /* Abort Termination */
#define ERR_LNG 12 /* Long Message Error */
#define ERR_SHT 13 /* Short Message Error */
#define ERR_SUERR 14 /* SUERM threshold exceeded */
#define ERR_PERR 15 /* PCI Parity Error */
/* Other Stuff */
#define TRANSMIT_DIRECTION 0x80000000 /* Transmit direction bit. Bit off
* indicates receive direction */
#define ILOST 0x00008000 /* Interrupt Lost */
#define GROUPMSB 0x00004000 /* Group number MSB */
#define SACK_IMAGE 0x00100000 /* Used in IRQ for semaphore test */
#define INITIAL_STATUS 0x10000 /* IRQ status should be this after
* reset */
/* This must be defined on an entire channel group (Port) basis */
#define SUERM_THRESHOLD 0x1f
#undef VINT32
#undef VINT8
#endif /*** _INC_MUSYCC_H_ ***/
/*** End-of-File ***/
drivers/staging/cxt1e1/pmc93x6_eeprom.c 已删除 100644 → 0
浏览文件 @ 19b1e769
/* pmc93x6_eeprom.c - PMC's 93LC46 EEPROM Device
*
* The 93LC46 is a low-power, serial Electrically Erasable and
* Programmable Read Only Memory organized as 128 8-bit bytes.
*
* Accesses to the 93LC46 are done in a bit serial stream, organized
* in a 3 wire format. Writes are internally timed by the device
* (the In data bit is pulled low until the write is complete and
* then is pulled high) and take about 6 milliseconds.
*
* Copyright (C) 2003-2005 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/types.h>
#include "pmcc4_sysdep.h"
#include "sbecom_inline_linux.h"
#include "pmcc4.h"
#include "sbe_promformat.h"
#include "pmc93x6_eeprom.h"
#ifndef TRUE
#define TRUE 1
#define FALSE 0
#endif
/*------------------------------------------------------------------------
* EEPROM address definitions
*------------------------------------------------------------------------
*
* The offset in the definitions below allows the test to skip over
* areas of the EEPROM that other programs (such a VxWorks) are
* using.
*/
#define EE_MFG (long)0 /* Index to manufacturing record */
#define EE_FIRST 0x28 /* Index to start testing at */
#define EE_LIMIT 128 /* Index to end testing at */
/* Bit Ordering for Instructions
*
* A0, A1, A2, A3, A4, A5, A6, OP0, OP1, SB (lsb, or 1st bit out)
*
*/
#define EPROM_EWEN 0x0019 /* Erase/Write enable (reversed) */
#define EPROM_EWDS 0x0001 /* Erase/Write disable (reversed) */
#define EPROM_READ 0x0003 /* Read (reversed) */
#define EPROM_WRITE 0x0005 /* Write (reversed) */
#define EPROM_ERASE 0x0007 /* Erase (reversed) */
#define EPROM_ERAL 0x0009 /* Erase All (reversed) */
#define EPROM_WRAL 0x0011 /* Write All (reversed) */
#define EPROM_ADR_SZ 7 /* Number of bits in offset address */
#define EPROM_OP_SZ 3 /* Number of bits in command */
#define SIZE_ADDR_OP (EPROM_ADR_SZ + EPROM_OP_SZ)
#define LC46A_MAX_OPS 10 /* Number of bits in Instruction */
#define NUM_OF_BITS 8 /* Number of bits in data */
/* EEPROM signal bits */
#define EPROM_ACTIVE_OUT_BIT 0x0001 /* Out data bit */
#define EPROM_ACTIVE_IN_BIT 0x0002 /* In data bit */
#define ACTIVE_IN_BIT_SHIFT 0x0001 /* Shift In data bit to LSB */
#define EPROM_ENCS 0x0004 /* Set EEPROM CS during operation */
/*------------------------------------------------------------------------
* The ByteReverse table is used to reverses the 8 bits within a byte
*------------------------------------------------------------------------
*/
static unsigned char ByteReverse[256];
static int ByteReverseBuilt = FALSE;
/*------------------------------------------------------------------------
* mfg_template - initial serial EEPROM data structure
*------------------------------------------------------------------------
*/
static u8 mfg_template[sizeof(FLD_TYPE2)] = {
PROM_FORMAT_TYPE2, /* type; */
0x00, 0x1A, /* length[2]; */
0x00, 0x00, 0x00, 0x00, /* Crc32[4]; */
0x11, 0x76, /* Id[2]; */
0x07, 0x05, /* SubId[2] E1; */
0x00, 0xA0, 0xD6, 0x00, 0x00, 0x00, /* Serial[6]; */
0x00, 0x00, 0x00, 0x00, /* CreateTime[4]; */
0x00, 0x00, 0x00, 0x00, /* HeatRunTime[4]; */
0x00, 0x00, 0x00, 0x00, /* HeatRunIterations[4]; */
0x00, 0x00, 0x00, 0x00, /* HeatRunErrors[4]; */
};
/*------------------------------------------------------------------------
* BuildByteReverse - build the 8-bit reverse table
*------------------------------------------------------------------------
*
* The 'ByteReverse' table reverses the 8 bits within a byte
* (the MSB becomes the LSB etc.).
*/
static void BuildByteReverse(void)
{
/* Used to build by powers to 2 */
long half;
int i;
ByteReverse[0] = 0;
for (half = 1; half < sizeof(ByteReverse); half <<= 1)
for (i = 0; i < half; i++)
ByteReverse[half + i] =
(char)(ByteReverse[i] | (0x80 / half));
ByteReverseBuilt = TRUE;
}
/*------------------------------------------------------------------------
* eeprom_delay - small delay for EEPROM timing
*------------------------------------------------------------------------
*/
static void eeprom_delay(void)
{
int timeout;
for (timeout = 20; timeout; --timeout)
OS_uwait_dummy();
}
/*------------------------------------------------------------------------
* eeprom_put_byte - Send a byte to the EEPROM serially
*------------------------------------------------------------------------
*
* Given the PCI address and the data, this routine serially sends
* the data to the EEPROM.
*/
static void eeprom_put_byte(long addr, long data, int count)
{
u_int32_t output;
while (--count >= 0) {
/* Get next data bit */
output = (data & EPROM_ACTIVE_OUT_BIT) ? 1 : 0;
/* Add Chip Select */
output |= EPROM_ENCS;
data >>= 1;
eeprom_delay();
/* Output it */
pci_write_32((u_int32_t *) addr, output);
}
}
/*------------------------------------------------------------------------
* eeprom_get_byte - Receive a byte from the EEPROM serially
*------------------------------------------------------------------------
*
* Given the PCI address, this routine serially fetches the data
* from the EEPROM.
*/
static u_int32_t eeprom_get_byte(long addr)
{
u_int32_t input;
u_int32_t data;
int count;
/* Start the Reading of DATA
*
* The first read is a dummy as the data is latched in the
* EPLD and read on the next read access to the EEPROM.
*/
input = pci_read_32((u_int32_t *) addr);
data = 0;
count = NUM_OF_BITS;
while (--count >= 0) {
eeprom_delay();
input = pci_read_32((u_int32_t *) addr);
/* Shift data over */
data <<= 1;
data |= (input & EPROM_ACTIVE_IN_BIT) ? 1 : 0;
}
return data;
}
/*------------------------------------------------------------------------
* disable_pmc_eeprom - Disable writes to the EEPROM
*------------------------------------------------------------------------
*
* Issue the EEPROM command to disable writes.
*/
static void disable_pmc_eeprom(long addr)
{
eeprom_put_byte(addr, EPROM_EWDS, SIZE_ADDR_OP);
/* this removes Chip Select from EEPROM */
pci_write_32((u_int32_t *) addr, 0);
}
/*------------------------------------------------------------------------
* enable_pmc_eeprom - Enable writes to the EEPROM
*------------------------------------------------------------------------
*
* Issue the EEPROM command to enable writes.
*/
static void enable_pmc_eeprom(long addr)
{
eeprom_put_byte(addr, EPROM_EWEN, SIZE_ADDR_OP);
/* this removes Chip Select from EEPROM */
pci_write_32((u_int32_t *) addr, 0);
}
/*------------------------------------------------------------------------
* pmc_eeprom_read - EEPROM location read
*------------------------------------------------------------------------
*
* Given a EEPROM PCI address and location offset, this routine returns
* the contents of the specified location to the calling routine.
*/
static u_int32_t pmc_eeprom_read(long addr, long mem_offset)
{
/* Data from chip */
u_int32_t data;
if (!ByteReverseBuilt)
BuildByteReverse();
/* Reverse address */
mem_offset = ByteReverse[0x7F & mem_offset];
/*
* NOTE: The max offset address is 128 or half the reversal table. So
* the LSB is always zero and counts as a built in shift of one bit.
* So even though we need to shift 3 bits to make room for the command,
* we only need to shift twice more because of the built in shift.
*/
/* Shift for command */
mem_offset <<= 2;
/* Add command */
mem_offset |= EPROM_READ;
/* Output chip address */
eeprom_put_byte(addr, mem_offset, SIZE_ADDR_OP);
/* Read chip data */
data = eeprom_get_byte(addr);
/* Remove Chip Select from EEPROM */
pci_write_32((u_int32_t *) addr, 0);
return (data & 0x000000FF);
}
/*------------------------------------------------------------------------
* pmc_eeprom_write - EEPROM location write
*------------------------------------------------------------------------
*
* Given a EEPROM PCI address, location offset and value, this
* routine writes the value to the specified location.
*
* Note: it is up to the caller to determine if the write
* operation succeeded.
*/
static int pmc_eeprom_write(long addr, long mem_offset, u_int32_t data)
{
u_int32_t temp;
int count;
if (!ByteReverseBuilt)
BuildByteReverse();
/* Reverse address */
mem_offset = ByteReverse[0x7F & mem_offset];
/*
* NOTE: The max offset address is 128 or half the reversal table. So
* the LSB is always zero and counts as a built in shift of one bit.
* So even though we need to shift 3 bits to make room for the command,
* we only need to shift twice more because of the built in shift.
*/
/* Shift for command */
mem_offset <<= 2;
/* Add command */
mem_offset |= EPROM_WRITE;
/* Output chip address */
eeprom_put_byte(addr, mem_offset, SIZE_ADDR_OP);
/* Reverse data */
data = ByteReverse[0xFF & data];
/* Output chip data */
eeprom_put_byte(addr, data, NUM_OF_BITS);
/* Remove Chip Select from EEPROM */
pci_write_32((u_int32_t *) addr, 0);
/*
* Must see Data In at a low state before completing this transaction.
*
* Afterwards, the data bit will return to a high state, ~6 ms, terminating
* the operation.
*/
/* Re-enable Chip Select */
pci_write_32((u_int32_t *) addr, EPROM_ENCS);
/* discard first read */
temp = pci_read_32((u_int32_t *) addr);
temp = pci_read_32((u_int32_t *) addr);
if (temp & EPROM_ACTIVE_IN_BIT) {
temp = pci_read_32((u_int32_t *) addr);
if (temp & EPROM_ACTIVE_IN_BIT) {
/* Remove Chip Select from EEPROM */
pci_write_32((u_int32_t *) addr, 0);
return 1;
}
}
count = 1000;
while (count--) {
for (temp = 0; temp < 0x10; temp++)
OS_uwait_dummy();
if (pci_read_32((u_int32_t *) addr) & EPROM_ACTIVE_IN_BIT)
break;
}
if (count == -1)
return 2;
return 0;
}
/*------------------------------------------------------------------------
* pmcGetBuffValue - read the specified value from buffer
*------------------------------------------------------------------------
*/
static long pmcGetBuffValue(char *ptr, int size)
{
long value = 0;
int index;
for (index = 0; index < size; ++index) {
value <<= 8;
value |= ptr[index] & 0xFF;
}
return value;
}
/*------------------------------------------------------------------------
* pmcSetBuffValue - save the specified value to buffer
*------------------------------------------------------------------------
*/
static void pmcSetBuffValue(char *ptr, long value, int size)
{
int index = size;
while (--index >= 0) {
ptr[index] = (char)(value & 0xFF);
value >>= 8;
}
}
/*------------------------------------------------------------------------
* pmc_eeprom_read_buffer - read EEPROM data into specified buffer
*------------------------------------------------------------------------
*/
void
pmc_eeprom_read_buffer(long addr, long mem_offset, char *dest_ptr, int size)
{
while (--size >= 0)
*dest_ptr++ = (char)pmc_eeprom_read(addr, mem_offset++);
}
/*------------------------------------------------------------------------
* pmc_eeprom_write_buffer - write EEPROM data from specified buffer
*------------------------------------------------------------------------
*/
void
pmc_eeprom_write_buffer(long addr, long mem_offset, char *dest_ptr, int size)
{
enable_pmc_eeprom(addr);
while (--size >= 0)
pmc_eeprom_write(addr, mem_offset++, *dest_ptr++);
disable_pmc_eeprom(addr);
}
/*------------------------------------------------------------------------
* pmcCalcCrc - calculate the CRC for the serial EEPROM structure
*------------------------------------------------------------------------
*/
static u_int32_t pmcCalcCrc_T01(void *bufp)
{
FLD_TYPE2 *buf = bufp;
/* CRC of the structure */
u_int32_t crc;
/* Calc CRC for type and length fields */
sbeCrc((u_int8_t *) &buf->type,
(u_int32_t) STRUCT_OFFSET(FLD_TYPE1, Crc32),
(u_int32_t) 0, (u_int32_t *) &crc);
#ifdef EEPROM_TYPE_DEBUG
/* RLD DEBUG */
pr_info("sbeCrc: crc 1 calculated as %08x\n", crc);
#endif
return ~crc;
}
static u_int32_t pmcCalcCrc_T02(void *bufp)
{
FLD_TYPE2 *buf = bufp;
/* CRC of the structure */
u_int32_t crc;
/* Calc CRC for type and length fields */
sbeCrc((u_int8_t *) &buf->type,
(u_int32_t) STRUCT_OFFSET(FLD_TYPE2, Crc32),
(u_int32_t) 0, (u_int32_t *) &crc);
/* Calc CRC for remaining fields */
sbeCrc((u_int8_t *) &buf->Id[0],
(u_int32_t) (sizeof(FLD_TYPE2) - STRUCT_OFFSET(FLD_TYPE2, Id)),
(u_int32_t) crc, (u_int32_t *) &crc);
#ifdef EEPROM_TYPE_DEBUG
/* RLD DEBUG */
pr_info("sbeCrc: crc 2 calculated as %08x\n", crc);
#endif
return crc;
}
/*------------------------------------------------------------------------
* pmc_init_seeprom - initialize the serial EEPROM structure
*------------------------------------------------------------------------
*
* At the front of the serial EEPROM there is a record that contains
* manufacturing information. If the info does not already exist, it
* is created. The only field modifiable by the operator is the
* serial number field.
*/
void pmc_init_seeprom(u_int32_t addr, u_int32_t serialNum)
{
/* Memory image of structure */
PROMFORMAT buffer;
/* CRC of structure */
u_int32_t crc;
time_t createTime;
createTime = get_seconds();
/* use template data */
memcpy(&buffer.fldType2, mfg_template, sizeof(buffer.fldType2));
/* Update serial number field in buffer */
pmcSetBuffValue(&buffer.fldType2.Serial[3], serialNum, 3);
/* Update create time field in buffer */
pmcSetBuffValue(&buffer.fldType2.CreateTime[0], createTime, 4);
/* Update CRC field in buffer */
crc = pmcCalcCrc_T02(&buffer);
pmcSetBuffValue(&buffer.fldType2.Crc32[0], crc, 4);
#ifdef DEBUG
for (i = 0; i < sizeof(FLD_TYPE2); ++i)
pr_info("[%02X] = %02X\n", i, buffer.bytes[i] & 0xFF);
#endif
/* Write structure to serial EEPROM */
pmc_eeprom_write_buffer(addr, EE_MFG, (char *)&buffer,
sizeof(FLD_TYPE2));
}
char pmc_verify_cksum(void *bufp)
{
FLD_TYPE1 *buf1 = bufp;
FLD_TYPE2 *buf2 = bufp;
/* CRC read from EEPROM */
u_int32_t crc1, crc2;
/* Retrieve contents of CRC field */
crc1 = pmcGetBuffValue(&buf1->Crc32[0], sizeof(buf1->Crc32));
#ifdef EEPROM_TYPE_DEBUG
/* RLD DEBUG */
pr_info("EEPROM: chksum 1 reads as %08x\n", crc1);
#endif
if ((buf1->type == PROM_FORMAT_TYPE1) &&
(pmcCalcCrc_T01((void *)buf1) == crc1))
return PROM_FORMAT_TYPE1; /* checksum type 1 verified */
crc2 = pmcGetBuffValue(&buf2->Crc32[0], sizeof(buf2->Crc32));
#ifdef EEPROM_TYPE_DEBUG
/* RLD DEBUG */
pr_info("EEPROM: chksum 2 reads as %08x\n", crc2);
#endif
if ((buf2->type == PROM_FORMAT_TYPE2) &&
(pmcCalcCrc_T02((void *)buf2) == crc2))
return PROM_FORMAT_TYPE2; /* checksum type 2 verified */
/* failed to validate */
return PROM_FORMAT_Unk;
}
drivers/staging/cxt1e1/pmc93x6_eeprom.h 已删除 100644 → 0
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#ifndef _INC_PMC93X6_EEPROM_H_
#define _INC_PMC93X6_EEPROM_H_
/*-----------------------------------------------------------------------------
* pmc93x6_eeprom.h -
*
* Copyright (C) 2002-2004 SBE, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* For further information, contact via email: support@sbei.com
* SBE, Inc. San Ramon, California U.S.A.
*-----------------------------------------------------------------------------
*/
#include <linux/types.h>
#ifdef __KERNEL__
#include "pmcc4_private.h"
void pmc_eeprom_read_buffer (long, long, char *, int);
void pmc_eeprom_write_buffer (long, long, char *, int);
void pmc_init_seeprom (u_int32_t, u_int32_t);
char pmc_verify_cksum (void *);
#endif /*** __KERNEL__ ***/
#endif
/*** End-of-File ***/
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